Memory Iterface CEN433 Kig Saud Uiversity Dr. 1
Address Decodig Whe iterfaced to a microprocessor with 20 address sigals there is a mismatch. The extra 9 address pis (A11-A19) are decoded usig a decoder such that they select the memory device for a uique positio i the memory map of the processor. BA0-19 19 11 10 0 Memory chip A10-A0 For example, the 2716 is 2 K x 8 memory device has 11 (= 1 + 10) address iputs (A0-A10). LS (11 bits) MS (9 bits) Memory devices iterfaced are usually of smaller storage capacity tha the full address space of the processor 11 Address bits 9 Selector bits 9 to 1 Decoder FFFFFH 511 MS (9 bits) LS (11 bits)... 00FFFH Decodig A11-A19 ad usig them for selectig the memory chip fixes the positio of the memory locatios i the mp address map High Memory (ROM) 510 000000001 xxxxxxxxxxx Here the mp address space is 29 times the size of the memory chip CS/ 00800H 211 = 1 2048 00000H 0 29 = 512 times Low Memory (RAM) mp Memory Map 2
Example 1: Exhaustive Address Decodig (Simple NAND Gate Decoder) Memory locatios:ff800h-fffffh 3
Example 2: Exhaustive Address Decodig 4
Example 3: Exhaustive Address Decodig (Simple NAND Gate Decoder) 32 K x 8 memory device: 15 bit address: 215 locatios U2A BA19 Selector address: 20 15 = 5 bits If we wat the memory locatios to start at 10000H, What is the selector address to decode?: Start Address 00010000000000000000 = 10000H Ed address 00010111111111111111 = 17FFFH Selector 5 bits: fixed) 2 74LS04 U2B BA18 3 1 2 3 4 U1 8 4 CS/ 5 6 11 12 74LS30 74LS04 U2C BA17 5 6 74LS04 BA16 U2C BA15 00010 (Remai 1 5 6 74LS04 Check: These are 7FFF+1 = 8000H = 215 locatios 5
Exhaustive Address Decodig (74LS138 74LS139) 6
Example 4: Exhaustive Address Decodig (74LS138) Module 0: 1111 000X XXXX XXXX XXXX 1111 0000 0000 0000 0000 to 1111 0001 1111 1111 1111... Module 7: 1111 111X XXXX XXXX XXXX 1111 1110 0000 0000 0000 to 1111 1111 1111 1111 1111 Memory locatios:f0000h-fffffh 7
Example 5: Exhaustive Address Decodig (74LS138) 64 KB EPROM Startig at F0000H Aswer: à F0000 FFFFFH. à BA0-BA15: Locatio Addressig. à BA16-BA19: Space Addressig. BA16 BA17 1 U1A 2 BA18 BA19 4 5 6 CS/ 74LS20 Assume that 64 KB EPROM is ot foud! We ca replace it with 8 of 8KB EPROM. Startig address is F0000H. Aswer: à BA16-BA19: Space Addressig. à 8KB EPROM U2 BA16 BA17 1 U1A 2 BA18 BA19 4 5 BA13 BA14 BA15 6 1 2 3 6 4 5 A B C G1 G2A G2B 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7 CS0/ CS1/ CS2/ CS3/ CS4/ CS5/ CS6/ CS7/ 74LS20 à à BA0-BA12: Locatio Addressig 74LS138 BA13-BA15: 8KB Module Addressig 8
Example 6: Exhaustive Address Decodig (74LS139) 64 KB EPROM Startig at F0000H Aswer: à F0000 FFFFFH. à BA0-BA15: Locatio Addressig. à BA16-BA19: Space Addressig. à 1 U1A 2 BA18 BA19 4 5 6 CS/ 74LS20 Assume that 64 KB EPROM is ot foud! We ca replace it with 4 of 16KB EPROM. Startig address is F0000H. Aswer: à BA16-BA19: Space Addressig. à 16KB EPROM à BA16 BA17 U2A BA16 BA17 1 U1A 2 BA18 BA19 4 5 BA14 BA15 6 2 3 1 A B G 4 Y0 5 Y1 6 Y2 7 Y3 CS0/ CS1/ CS2/ CS3/ 74LS139 74LS20 BA0-BA13: Locatio Addressig BA14-BA15: 8KB Module Addressig 9
Exhaustive Address Decodig (PLD Decoders ) May moder systems use programmable logic decoders i place of itegrated decoders They give total freedom i decodig differet addresses for idividual memory devices Programmable logic devices have may be called: PLDs: Programmable logic devices PLAs: Programmable logic array PALs: Programmable array logic GALs: Gate Array Logic SPLDs: Simple programmable logic devices CPLDs: Complex programmable logic devices They are all programmable logic devices. Nowadays they ca be programmed usig VHDL (Verilog Hardware Defiitio Laguage) Some types are programmed oly oce (fused liks), similar to PROMs Some types are erasable like EPROMs The ext slide shows oe of the most commo low cost devices: the PAL16L8 10
PAL16LR 11
PAL16LR xx yy zz xyz xyz x x x x x F = (xyz)+(xyz) x y z 12
Example 7: Exhaustive Decodig 13
Example 7: Exhaustive Decodig library ieee; use ieee.std_logic_1164.all; etity DECODER_10_17 is port ( BA19, BA18, BA17: i STD_LOGIC; Iput declaratio ROMCS/, RAMCS/ : out STD_LOGIC; output declaratio ); ed; architecture V1 of DECODER_10_17 is begi ROMCS/ <= ot BA19 or ot BA18 or ot BA17 ; ROMCS/ = 0 for BA19BA18BA17 = 111 RAMCS/ <= A17 or A18 or BA19 ; RAMCS/ = 0 for BA19BA18BA17 = 000 ed V1; 14
Example 8: Exhaustive Decodig A19 A18 A17 A16 A15 1 1 1 0 1 32 K x 8 E8000-EFFFF 15 A19 A18 A17 A16 A15 1 1 1 1 0 32 K x 8 F0000-F7000 A19 A18 A17 A16 A15 1 1 1 1 1 32 K x 8 F8000-FFFFF
Iterfacig EEPROM (Flash) Memories Mai Flash memory applicatios: Used whe cotets eed to be chaged oly ifrequetly, e.g.: Similarities with SRAMs: Storig system BIOS USB pe drives MP3 audio players Both eed the 3 basic memory cotrol iputs: CE, OE, ad WE Differeces with SRAMs: 1. EEPROM eeds a additioal programmig cotrols ad programmig (erasig) supply voltage. Used to be 25 or 12V, ow 5 or eve 3.3V. 2. EEPROM is much slower to write (erase) a byte: 0.4 s Versus 10s for SRAM 16
Example 9: Iterfacig EEPROM Select Byte (ot Word) operatio 28F400 Flash Memory I Byte operatio, DQ15 is a iput acceptig A0 address bit. 512K x 8 (I the Byte Mode) I the word mode: 256 K x 16 18-bit address startig with A1 FFFFFH Address: Start: 10000000000000000000 Ed: 11111111111111111111 i.e. 80000H to FFFFFH Eable Power dow mode Programmig supply voltage Additioal cotrol s for Flash memory. Used for programmig (erasig) 17 80000H 7FFFFH 00000H Flash occupies the top Half of the memory map
Example 10: Exhaustive Decodig Iterface a 16KB RAM ad a 64KB EPROM to a 8088 buffered system. Assume the startig address of the RAM is 0H ad the startig address of the EPROM is F0000H. Use NAND gates, as eeded, to geerate the chip selects. 18
Solutio of Example 10: 19
Example 11: Exhaustive Decodig Iterface a 4KB RAM ad a 8KB EPROM to a 8088 buffered system. Assume the startig address of the RAM is 0H ad the last address of the EPROM is FFFFFH. Use NAND gates, as eeded, to geerate the chip selects. 20
Solutio of Example 11: 21
Example 1: Partial Decodig Igorig both BA18 ad BA19 22
Example 2: Partial Decodig Igorig both BA17, BA18 ad BA19 23
Example 3: Partial Decodig Igorig both BA17 ad BA18 24
Example 4: Partial Decodig Igorig BA16, BA17 ad A18 25
Example 5: Partial Decodig Assume that the 1M memory space is divided ito 16 blocks. Oe of these blocks is used, ad the rest are igored. The block is divided further ito 4 segmets. The first segmet is used oly by a 2KB RAM, the secod ad the third segmet are left for future expasio, ad the fourth segmet is used oly by a 8KB EPROM. Iterface both 2KB RAM ad 8KB EPROM to the 8088 system usig partial decodig. 26
Solutio of Example 5: 27
Iterfacig 16-bit Memory to the 8086, 80286, ad 80386SX Mai differeces: 8086 from the 8088: The M/#IO replaces the IO/#M cotrol sigal The data bus is ow 16 bits ot 8 bits A ew cotrol output, A0 has a special use as BLE/ [Bus (byte) Low Eable] BHE/ [Bus (byte) High Eable] Mai differeces betwee 8086/186 ad 80286/386SX: 80286/386SX has 24-bit address bus (A23-A0) The M/#IO, RD/, WR/ are replaced with MRDC/, MWTC/, IORDC/ ad IOWTC/- more specific sigals 28
16-Bit Wide Memory 16-bit wide memory is orgaized i two separate 8-bit wide memory baks: Low bak (eve-umbered byte locatios: 0, 2, 4, 6, ) à low 8 bits of the data bus (D0-D7): LS Byte High bak (odd-umbered byte locatios: 1, 3, 5, 7, ) à high 8 bits of the data bus (D8-D15): MS Byte Processor must be able to access ay 16 or 8 bit locatios Baks are selected by the microprocessor through bak selectio (Bak Eable) sigals O the 8086, these byte selectio sigals are - The BLE/ (A0) sigal selectig low bak - The BHE/ sigal selectig high bak Oly with writes. For Reads, the processor will take the byte it wats ad o eed to eforce byte (bak) selectio 29
16-Bit Wide Memory FFFFF FFFFE FFFFD FFFFC FFFFB FFFFA...... 00005 00004 00003 00002 00001 00000 High Bak (Odd Bak) Low Bak (E ve Bak) BBHE/ BA0 0 0 Both baks eabled for a 16-bit trasfer 0 1 High bak eabled for a 8-bit trasfer 1 0 Low bak eabled for a 8-bit trasfer 1 1 No baks eabled Fuctio 30
16-Bit Wide Memory Ecodig Separate Write Sigals Why cosider this oly with write access (ot Reads)? Because the processor ca choose oly the byte(s) it wats to read from the full 16-bit data placed o the data bus by the 2 baks. So always eable both baks for READs. 31
Example 1: 16-Bit Wide Memory High bak data bits Low bak data bits Note: A1 ot A0 32K x 8 32K x 8 No bak selectio for READs Commo to both baks Low Bak Write Eable for low bak Write Eable for high bak High Bak Commo CE for both baks Active Low (oe decoder) If start byte address is 060000, Last address is 06FFFFH SEL = A23 + A22 + A21 + A20 + A19 + #A18 + #A17 + A16 (active low) 32
Example 1: 16-Bit Wide Memory library ieee; use ieee.std_logic_1164.all; etity DECODER_10_28 is port ( A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: i STD_LOGIC; SEL, LWR, HWR: out STD_LOGIC ); ed; architecture V1 of DECODER_10_28 is begi SEL <= A23 or A22 or A21 or A20 or A19 or (ot A18) or (ot A17) or A16; LWR <= A0 or MWTC; HWR <= BHE or MWTC; ed V1; 33
Example 2: Memory Iterface to 8086 We wat to iterface 64 KB RAM ad 64KB EPROM chips to 8086 microprocessor accordig to the followig assumptios: The startig address of the RAM is 0H. The last address of the EPROM is FFFFFH. Exhaustive decodig is used. The RAM ad EPROM chips are orgaized as followig: 34
Example 2: Memory Iterface to 8086 35
Example 3: Memory Iterface to 8086 We wat to iterface 64 KB RAM to 8086 microprocessor accordig to the followig assumptios: The startig address of 64 KB RAM i the memory space is 0H. Exhaustive decodig is used. The RAM chips are orgaized as followig: 36
Example 3: Memory Iterface to 8086 BBHE/ = 0 BA0 = 0 00000 00000 8K 8 RAM 32K 8 RAM 8K 8 RAM BA1-13 03FFF BD0-7 RAML1CS/ 04000 MEMR/ LWR/ 07FFF BA1-15 08000 BD8-15 RAMHCS/ 16K 8 RAM BA1-13 MEMR/ HWR/ BD0-7 RAML2CS/ MEMR/ LWR/ 0FFFF 0FFFF BA1-14 BD0-7 RAML3CS/ RAMHCS / BA14 BA15 A B G MEMR/ LWR/ RAML1 CS / RAML2 CS / RAML3 CS / 74LS139 37