EUROPRACTICE IC service The right cocktail of ASIC Services

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2 EUROPRACTICE IC service The right cocktail of ASIC Services IC SERVICE ALLIANCE PARTNER EUROPRACTICE IC Service offers you a proven route to ASICs that features: Low-cost ASIC prototyping Flexible access to silicon capacity for small and medium volume production quantities Partnerships with leading world-class foundries, assembly and testhouses Wide choice of IC technologies Distribution and full support of high-quality cell libraries and design kits for the most popular CAD tools RTL-to-Layout service for deep-submicron technologies Front-end ASIC design through Alliance Partners Industry is rapidly discovering the benefits of using the EUROPRACTICE IC service to help bring new product designs to market quickly and cost-effectively. The EUROPRACTICE ASIC route supports especially those companies who don t need always the full range of services or high production volumes. Those companies will gain from the flexible access to silicon prototype and production capacity at leading foundries, design services, high quality support and manufacturing expertise that includes IC manufacturing, packaging and test. This you can get all from EUROPRACTICE IC service, a service that is already established for more than 10 years in the market. The EUROPRACTICE IC Services are offered by the following centers: IMEC, Leuven (Belgium) Fraunhofer-Institut fuer Integrierte Schaltungen (Fraunhofer IIS), Erlangen (Germany) By courtesy of IMEC The European Commission is funding the Europractice IC Service under the IST programme in the 6 th framework. This funding is exclusively used to support European universities and research laboratories.

3 Foreword Dear EUROPRACTICE customers, When writing this foreword last year, we noticed an increased number of designs submitted on MPW runs at the end of February. This trend has been continued over the whole year and we are extremely pleased that we received 539 designs in Table of contents total in This is a large increase (+24%) compared to the 433 designs in The increase mainly comes from university designs. We noticed that several universities have sent in several small designs under the mini@sic program. The effect of the mini@sic program together with the discounted prices for European universities and research institutes (financed Foreword by the European Commission under the 6 th Framework Program EUROPRACTICE IC3) indeed 1 has stimulated several universities to design integrated circuits in more advanced technologies, resulting in a strong increase Your of designs Total in and 0.18µ, Turn-Key 0.13µ and ASIC 90nm. Solution 3 More specifically, the overall (coming from universities and research centers world-wide) number of mini@sic designs increased from 140 in 2006 to 207 last year. Easy access 3 Phase I: ASIC Design 4 For universities Phase and research II: Prototyping centers, we and will test keep development focusing on a good and affordable mini@sic service. As such 5 we will continue in 2008 to offer a large number of mini@sic runs in most of the offered technologies. Phase III: First test & Characterization of prototype 5 In 2008 we will Phase start to IV: cooperate Qualification very of closely the ASIC together with the EC-funded project IDESA. The aim of IDESA 6 is to stimulate universities designing in advanced technologies by offering training courses in analog, digital and mixedsignal design flow in 90nm TSMC technology. These courses will be organized, starting in May 2008, several times Phase V: Volume production & test activities 6 per year in different EUROPRACTICE locations in offers Europe. deep Basically submicron these design are free support to European service universities and research institutes. 7 In addition several Low cost lectures IC-prototyping on 65 and 45nm design topics will be recorded and be made available on demand. 8 EUROPRACTICE will support the IDESA project by offering mini@sic runs in the 90nm TSMC technology. For details: Technologies / Supply partners / mini@sic 9 In 2008 we will EUROPRACTICE also start to offer offers MPW full services test solutions in MEMS technologies. for production As such we plan to offer MEMS technologies 10 from TRONICS and MEMSCAP starting in first half of Web site / EUROPRACTICE-online 11 We are also pleased to announce that we have signed a new agreement with the European Commission under the 7 th Framework Program (EUROPRACTICE IC4) so that a supported CAD service and discounted MPW offering towards Results 12 the European universities and research institutes is secured until the end of MPW prototyping service 12 For the industry, we have further elaborated our easycot prototype and small/medium volume service. Through Small volume projects 15 our easycot service we offer easy access and technical support in various aspects such as access to standard cell libraries, foundry design rules and technology parameters, RTL-to-layout service, prototyping, advanced packaging Examples of ASIC projects 16 such BGA, test software and hardware development, debugging, characterization, qualification, product ramp-up and small to medium volume production. With strong partners such as AMIS, austriamicrosystems, IHP, TSMC, UMC, Microtest List and of ASE, customers we offer our customers a solid, guaranteed and high quality access to wafer manufacturing, 29 assembly and test. I thank you for your continuous support and look forward to future cooperation, Sincerely yours, Dr. C. Das Chairman EUROPRACTICE IC Service IMEC (Belgium) europractice foreword 1

4 Table of contents Foreword Foreword Your Total and Turn-Key ASIC Solution 3 Your Total Easy and access Turn-Key ASIC Solution Phase I: ASIC Design Easy access Phase II: Prototyping and test development 5 Phase I: ASIC Design... 4 Phase III: First test & Characterization of prototype 5 Phase II: Prototyping and test development... 5 Phase IV: Qualification of the ASIC 6 Phase Phase III: V: First Volume test & production Characterization & test of prototype activities Phase EUROPRACTICE IV: Qualification offers the deep ASIC submicron... design support service 6 7 Low cost IC-prototyping Phase V: Volume production & test activities Technologies / Supply partners / mini@sic 9 EUROPRACTICE offers deep submicron design support service... 7 EUROPRACTICE offers full test solutions for production 10 Low Web cost site IC-prototyping... / EUROPRACTICE-online 8 11 Technologies / Supply partners / mini@sic... 9 Results 12 EUROPRACTICE offers full test solutions for production...10 MPW prototyping service 12 Web Small site / volume EUROPRACTICE-online... projects Examples of ASIC projects 16 Results...12 List of customers 29 MPW prototyping service...12 Small volume projects...13 Examples of ASIC projects...16 List of customers europractice table of contents

5 EUROPRACTICE: : Your Total and Turn-Key ASIC Solution EUROPRACTICE provides semiconductor semiconduc- and system New fables com-startup companies as well as small companies or compa- panies tor and with system a total companies and turn-key with a ASIC total solution nies including having : small ASIC volume products in niche markets experience and easy turn-key access ASIC to foundry solution design including rules, : cell libraries huge problems and to Through get access its to agreement foundries with since foundries their volume and library is too design easy access kits to foundry design rules, deep cell libraries submicron and RTL-to-layout design kits service small. partners, EUROPRACTICE is allowed to distribute foundry technology information and cell libraries low deep cost submicron prototype RTL-to-layout fabrication service service EUROPRACTICE has upon wafer simple foundry signature agreements of a standard with different Non-Disclosure leading fabrication service including wafer fabrication, suppliers, allowing to Agreements offer the most or a advanced Design Kit as well License as specific Agreement. tech- volume packaging low cost prototype and test fabrication service qualification ASIC logistics volume fabrication service including technical wafer fabrication, customer support packaging and test nologies to those customers. Those agreements Our foundry can be partners downloaded acknowledge from the EU- the EUROPRACTICE Service ROPRACTICE as the optimal website. solution In this to way provide you wafer have access capacity to smaller customers. in a few Suppliers days without see EUROPRACTICE having to go through as one big a painful about customer 600 universities qualification and procedure 300 companies at the foundry. world- customer representing wide. Through agreements Foundry information with foundry includes partners, design EUROPRACTICE rules, spice parameters, is ranging design from & layout a few manuals wafers and to thousands DRC/ERC/LVS of New ASIC fables qualification startup companies as well as small able companies to offer ASIC solutions or logistics companies having small ASIC volume products wafers in per niche year. markets technical experience customer huge support problems to get access to foundries decks. Cell library information includes library manuals and design kits for most of the popular CAD tools since their volume is too small. (Cadence, Synopsys, Mentor Graphics, Tanner, etc.). Easy access EUROPRACTICE has wafer foundry agreements with different leading suppliers, allowing to offer the most ad- Easy access This foundry and library information is distributed on the EUROPRACTICE CD-ROM or via vanced as well as specific technologies to those FTP. Through its agreement with foundries customers. Our foundry partners acknowledge the EUROPRACTICE Service as the and library partners, EUROPRACTICE is allowed to distribute foundry technology information and cell libraries upon optimal solution to provide wafer capacity to smaller customers. Suppliers see EUROPRACTICE as one big simple signature of a standard Non- Disclosure Agreements or a Design Kit customer representing about License Agreement. Those agreements 600 universities and 300 companies world-wide. Through can be downloaded from the EURO- PRACTICE website. In this way you agreements with foundry have access in a few days without partners, EUROPRACTICE having to go through a painful customer qualification procedure at the is able to offer ASIC solutions ranging from a few foundry. Foundry information includes most of the popular CAD tools (Cadence, Synopsys, Mentor Graphics, wafers to thousands of design rules, spice parameters, design wafers per year. & layout manuals and DRC/ERC/LVS Tanner, etc.). This foundry and library decks. Cell library information includes information is distributed on the EUlibrary manuals and design kits for ROPRACTICE CD-ROM or via FTP. europractice a total solution 3

6 Phase I: ASIC Design When customers have received design rules, cell libraries, etc., they can can start the ASIC design. design. ASIC ASIC design design can can be be split split up up into into front-end end design design and and back-end back-end design. design. Front- Front-end design design covers covers ASIC ASIC specifica- specification feasibility study study and and design design in- including tasks such as schematic entry, VHDL description, scan insertion, simulation and synthesis. The front-end design can be carried out by by the the customer himself or can be subcontracted to to a design house. During this this design phase, Europractice offers technical support support on tion, on technology, test, test, type type of of package, package, etc. etc. Important Important know-how know-how and feed- and feedback from from the the test test house house will will be be used used to to improve the DFT (Design For For Testability). State-of-the-art CAD CAD tools are are used during the ASIC design phase. When the netlist is ready the backend design activity starts including layout generation using state-ofthe art layout tools. Deep submicron digital place & route tasks are in most cases not performed by the customers. For those customers that have not their own layout tools, EUROPRACTICE is offering such deep submicron layout When service the (see netlist deep is submicron ready the backenout design service on activity page starts 7). After including initial layout, generation timing verification using state-of-the is car- lay- art ried layout by tools. the customer Deep submicron using digital parasitic place layout & route information tasks are andin most layout cases is iterated not performed until timing by the is customers. met. Verification For those of customers the design that have needs not to their be done own in layout all technology tools, EU- ROPRACTICE corners. is offering such deep submicron layout service (see deep submicron When layout layout is service finished, on page a final 7). After DRC initial (Design layout, Rule timing Check) verification and LVS (Layout versus Schematic) is performed on the GDS-II database in order to deliver a correct GDS-II to the foundry for manufacturing. is carried out by the customer using parasitic layout information and layout is iterated until timing is met. Verification of the design needs to be done in all technology corners. By courtesy of IMEC When layout is finished, a final DRC (Design Rule Check) and LVS (Layout versus Schematic) is performed on the GDS-II database in order to deliver a correct GDS-II to the foundry for manufacturing. Design House know-how Design for testability (DFT) > > ASIC specifications Initial design review Preliminary design review customer design foundry, IP provider Foundry, IP provider Design rules, IP & cell libraries models Foundry, IP provider IP cell libraries layout Foundry Golden rules file for DRC, LPE, LVS > > > Digital, analog front-end design Physical layout generation Design verification assembly test Critical design review Tape out EUROPRACTICE Correct GDS-II database for manufacturing 4 europractice a total solution

7 Phase II: Prototyping and test development After all the the checks checks have have been been per- performed and the the GDS-II GDS-II database database is is correct for for manufacturing, manufacturing, Europracticpractice sends sends the database the database to the to foun- the Eurodry foundry for prototyping. for prototyping. Masks Masks will will be generated be generated by the by the foundry foundry and and first silicon first silicon will be will produced. be produced. Prototyping Prototyping be done can on be MPW done (Multi on Project MPW can Wafer) (Multi Project runs or Wafer) SPW (Single runs or Project SPW Wafer) (Single pilot Project runs Wafer) (see Low pilot Cost runsic prototyping (see Low Cost on page IC prototyping 8). on page 8). In parallel with prototype fabrication and In parallel prototype with packaging prototype fabrica- the test solution and including prototype test packaging hardware the and software test solution is developed. including EUROPRAC- test hardware will and generate software bonding is developed. diagram TICE and EUROPRACTICE assembly instructions. will generate For prototyping bonding diagram ceramic and packages assembly well instructions. the production For prototyping plastic packages ceramic as packages as well as the production can be plastic used. packages Prototype can packaging be used. is done Prototype through packaging one of the is assembly through partners one in of Europe the as-osembly the Far-East. partners in Europe or done the Far-East. Correct GDS-II database for manufacturing Correct Correct GDS-II GDS-II database database for for manufacturing manufacturing Test hardware development Mask generation Test hardware development Mask Mask generation generation Test Probe hardware card / development test board Probe Probe card card / / test test board board Wafer fabrication Test software (MPW Wafer Wafer or engineering fabrication fabrication lot) Test development Test software software (MPW (MPW or or engineering engineering lot) lot) development development Packaging prototypes Debugging hardware Packaging Packaging prototypes prototypes Debugging Debugging hardware hardware Prototypes and test solution available Prototypes Prototypes and and test test solution solution available available Phase III: First test & Characterization of prototype When packaged prototypes are When packaged prototypes are available, they will be shipped to available, they will be shipped to the test house for debugging. Debugging includes continuity and the test house for debugging. Debugging includes continuity and leakage tests, ATPG test and test of leakage tests, ATPG test and test the different analog blocks (when of the different analog blocks available on the ASIC) at room (RT) (when available on the ASIC) at temperature. When prototypes are room (RT) temperature. When prototypes are working correctly ac- working correctly according to the ASIC specification, low (LT) and high cording to the ASIC specification, (HT) temperature are performed. low (LT) and high (HT) temperature are performed. The next stage The next stage is a full characterization of the ASIC at the corners of the is a full characterization of the voltage supply and frequency at LT, ASIC at the corners of the voltage RT and HT. supply and frequency at LT, RT and During each test a datalog is generated of the measured values and HT. histograms and cpk reports are sent to the customer. In case of specific During each test a datalog is generated of the measured values and problems, failure analysis can be done to determine the reason of the histograms and cpk reports are failing. sent to the customer. In case of specific problems, failure analysis can be done to determine the reason of the failing. By courtesy of Microtest Prototypes and test solution available Prototypes Prototypes and and test test solution solution available available Test and debug Test Test prototypes and and debug debug prototypes prototypes Test at RT, Test Test LT, at at HT RT, RT, LT, LT, HT HT Characterization Characterization Characterization prototypes prototypes prototypes Datalog, histograms, drift Datalog, Datalog, analysis, histograms, histograms, CPK, CP drift drift analysis, analysis, CPK, CPK, CP CP europractice a total solution 5

8 ments: > Start new batch of wafers Phase Packaging IV: Qualification of of the ASIC When customers customers only only need need prototypes of prototypes their Development ASIC, of qualification their ASIC, of qualification qualification is not needed. procedure is not needed. Qualification requirements: However when prototypes are working correctly However Qualification and when the prototypes customer hardware would are Medical like to Qualification requirements: have working volume development correctly production and the it customer to would think about like to the have product vol- qualifi- Industrial is the right Medical time Space Industrial > cation. ume Qualification production it software is the right Consumer Space time to think development about the product qualification. offers within their test so- Consumer Europractice lution Datalog, service a histograms, full qualification through Europractice offers within their test solution one of the CPK, test CP house partners. service The a full qualification through one of the qualification procedure can range from test house partners. The qualification procedure till can Space range qualification from Consumer, according Industry to the Mil- and Consumer, Industry and Medical Medical itary, till Space JEDEC qualification standards... according to the Military, The JEDEC qualification standards... procedure will be discussed between procedure Europractice, will be discussed cus- The qualification between tomer Europractice, and test house customer and and a full test qualification full qualification flow will be flow prepared. will be To prepared. speed house and a To speed up up the the procedure, most of of the tests are running are running parallel. in parallel. Special Special burn-in burn-in boards will be boards developed will for be reliability developed tests. for reliability tests. By courtesy of MASER Engineering > Phase V: Volume production & test activities Phase V: Volume production & test activities Once the ASIC has been Wafer production qualified, the ASIC is Once the ASIC has been qualified, the ready ASIC for is volume ready for production. will During be monitored. the ramp-up Once the ASIC runs into volume production. During the ramp-up phase, yield and process Probe test higher volume, the test solution can be phase, transferred yield and to test process houses in the Far East. In that case the test boards are copied, will the original be monitored. test board Once will remain in our European test houses so that yield and process the ASIC monitoring runs into is higher Packaging still possible. volume, the test solution can be transferred Final test to test houses in the Far East. In that case the test boards are copied, Yield & process the original test board monitoring will remain in our European test houses so that Delivery tested yield and process monitoring is still components By courtesy of Microtest possible. Start new batch of wafers Start new batch of wafers Packaging Packaging Development of qualification procedure Development of qualification procedure Qualification hardware Qualification development hardware development Qualification software Qualification software development development Datalog, Datalog, histograms, histograms, CPK, CPK, CP Wafer production Wafer production Probe test Packaging Probe test Final test Packaging Yield & process monitoring Final test Delivery tested components Yield & process monitoring 6 europractice a total solution Delivery tested components

9 EUROPRACTICE offers deep submicron design support service Synthesis and layout of deep submicron chips is not straightforward. You need a highly trained team of engineers equipped with expensive state-of-the art software tools. The chips are growing in size whereas the technology dimensions are getting smaller. Because of this, designers have to to understand how how to tackle to tackle issues issues clock-skew, like: clock-skew, latencies latencies of interacting of interacting clock clock domains, do- like: IR-drop mains, IR-drop on the on power the power distribution, distribution, electro-migration electro-migration signal and integrity signal integrity issues, handling issues, handling up to 8 layers up to of 8 and metal layers in of metal the back-end, in the back-end, incorporating incorporating IP blocks IP blocks in the design, in the design, on-chip on-chip variation, variation, design design for packaging, for packaging, etc. etc. Supporting high-level designers, EUROPRACTICE IC Service Supporting provides high-level a design designers, support EUROPRACTICE service starting IC from Service code provides or synthesized a design support netlist. service The service starting includes from RTL the RTL whole code or back-end synthesized design netlist. flow: The virtual service prototyping, includes physical the whole synthesis, back-end deep-submicron design flow: virtual layout, prototyping, timing analysis, physical simulation, synthesis, ATPG, deep-submicron tape-out preparation, layout, etc. timing analysis, simulation, ATPG, tape-out preparation, etc. The service is equipped with state-of-the art tools from the The major service vendors: is equipped the Synopsys with state-of-the Galaxy art and tools Cadence from Encounter the major Platforms. vendors: the Synopsys Galaxy and Cadence Encounter Platforms. In the past many circuits were taped out successfully In the both past for many in-house circuits developed were taped Systems-On-a-Chip out successfully as both for for ASICs in-house developed developed by third Systems-On-a-Chip party design houses, as for research ASICs developed institutes by and third universities. party design Many of houses, these circuitsearch included institutes IP blocks and universities. like analog Many full custom of these blocks, cir- re- memory cuits included macro s IP (even blocks from like analog different full vendors), custom blocks, special I/O memory and RTL macro s level (even (soft or from firm) different IP. vendors), special I/O and RTL level (soft or firm) IP. Procedures are in place to offer standard and staggered Procedures I/O configurations are in place and to configurations offer standard with and bondingered pads I/O equally configurations spread over and configurations the standard-cell with core, bond- for stag- flip-chip ing pads application. equally spread over the standard-cell core, for flip-chip application. Some circuit complexities handled are: up to 71 million transistors, Some circuit several complexities hundred handled interrelated are: up to gated 71 million clock domains transistors, and several technologies hundred from interrelated many different gated vendors clock down domains to 90nm. and technologies from many different vendors down to 90nm. IMEC s flexible-air-interface baseband plaform (TSMC 90nm CMOS) Layout of a 40 million transistor circuit featuring RAMS and other (By courtesy of IMEC) IP in Chartered Semiconductor 0.13µ CMOS 46.5 mm 2 (By courtesy of IMEC) A mixed signal control ASIC designed in IMEC s radiation-hardened-by-design Layout of a 3.7 DARE180 million-transistor (UMC 0.18) circuit library featuring for the digital several part memory plus analog blocks blocks and PLL using UMC layout-based 0.18µ CMOS radiation (6 metal countermeasures. layers) 20 mm 2 (By courtesy of of IMEC) europractice a total solution 7

10 Low cost IC prototyping The The cost cost of of producing producing a new new ASIC for for a a dedicated dedicated application application within within a small a small market market can can be high, be high, if directly if directly produced by a commercial by a commercial foundry. produced This foundry. is largely This due is largely to the due NRE to (Non- the Recurring NRE (Non-Recurring Engineering) Engineering) overheads associated overheads with associated design, with manufacturing manufacturing and test. and design, test. EUROPRACTICE EUROPRACTICE has has reduced reduced the the NRE, NRE, especially especially for for ASIC ASIC prototyping, by by two two techniques: techniques: ing, (i) (i) Multi Multi Project Project Wafer Wafer Runs Runs or or (ii) (ii) Multi Multi Level Level Masks. Masks. Multi Multi Project Project Wafer Wafer Runs Runs By By combining combining several several designs designs from different different customers customers onto onto one one mask set set and and prototype prototype run, run, known known as as Multi Multi Project Project Wafer Wafer (MPW) (MPW) runs, the the high high NRE NRE costs costs of of a mask mask set set is shared among the participating customers. is Fabrication shared among of prototypes the participating can thus customers. be as low as 5% to 10% of the Fabrication cost of a of full prototypes prototyping can wafer thus be run. as Alow limited as 5% number to 10% of of tested the cost or of untested a full prototyping ASIC prototypes, wafer run. typically A limited 20-50, number are delivered of tested to or the untested customer prototypes, for evaluation, typically either 20-50, are as ASIC delivered naked dies to or the as customer encapsulated for evaluationvices. either Only as prototypes naked dies from or as fully en- decapsulated qualified wafers devices. are Only taken prototypes ensure fully that qualified the chips wafers delivered are taken will from to function ensure right that first the time. chips delivered will function right first time. In order to achieve this, extensive In Design order Rule to achieve and Electrical this, extensive Rule Design Checkings Rule are and performed Electrical on Rule all Checkings designs submitted are performed to the on Service. all designs EUROPRACTICE submitted is to organising the Service. about EUROPRACTICE 130 MPW runs is per organising year in various about 200 technologies. MPW runs per year in various technologies. Multi Level Mask Single User Runs Another technique to reduce the high mask costs is called Multi Level Mask (MLM). With this Multi technique Level Mask the available mask area Single (20 User mm x Runs 20 mm field) is typically Another divided technique in four to quadrants reduce the (4L/R: high mask four layer costs per is called reticle) Multi wherebel Mask each quadrant (MLM). With is filled this with technique one Lev- design the available layer. As mask an example area (20: mm one x mask 20 mm can field) contain is typically four layers divided suchin as four nwell, quadrants poly, (4L/R ndiff : four and layer active. per The reticle) total whereby number of each masks quadrant is thusis reduced filled with by one a factor design of layer. four. As Byan adapting example : the one lithographical mask can contain procedure layers it such is possible as nwell, poly, to use ndiff one and four mask active. four The times total number for the of different masks is layers thus reduced by using by a the factor appropriate of four. By quadrants. adapting the Using lithographical this technique procedure mask it is costs possible can to be use reduced one mask by the about four times 60%. for the different layers by using the appropriate quadrants. The Using advantages this technique of using the mask MLM single can user be reduced runs are by : about (i) lower 60%. mask costs costs, (ii) can be started any date and The advantages not restricted of using to scheduled MLM single MPW user runs runs, are (iii): single (i) lower user mask and costs, (iv) customer (ii) can be receives started any minimal date and a fewnot wafers, restricted so to a few scheduled hundreds MPW of prototypes. (iii) single user and (iv) customer runs, receives minimal a few wafers, so a This few hundreds technique of is prototypes. preferred over MPW runs when the chip area becomes This technique large and is when preferred the customer MPW runs wants when to get the a higher chip area num- be- over ber comes of large prototypes and when or the preserie. customer When wants the to prototypes get a higher are number success-oful, this mask or preserie. set can be When used the prototypes prototypes under certain are successful, conditions this for mask low set can volume be used production. under certain conditions for low volume production. This technique is only This technique available is for only technologies available for technologies from AMI from Semiconductor AMI Semiconductor and IHP. and IHP. By courtesy of IMEC 8 europractice a total solution

11 Technologies For For 2008, 2006, EUROPRACTICE EUROPRACTICE has extended has extended its technology its technology portfolio. Currently customers can have access to prototype and production fabrication in the following technologies : portfolio. Currently customers can have access to prototype and production fabrication in the following AMIS technologies 0.7µ C07M-D : 2M/1P & AMIS 0.7µ C07M-A 2M/1P/PdiffC/HR AMIS AMIS 0.5µ 0.35µ C05M-D C035M-A 3M/1P 5M/2P/HR & AMIS 0.5µ C05M-A 3M/2P/HR AMIS 0.5µ CMOS EEPROM C5F & C5N AMIS 0.35µ C035M-D 5M/1P AMIS 0.35µ C035M-D 5M/1P & AMIS 0.35µ C035M-A 5M/2P/HR AMIS AMIS 0.35µ 0.35µ C035U C035M-I3T80U 4M (3M & 5M 80 optional) V - 3M & 4M AMIS AMIS 0.7µ 0.5µ C07M-I2T100 C05M-A 3M/2P/HR 100 V - 2M & 3M options AMIS AMIS 0.7µ 0.5µ C07M-I2T30 C05M-D 3M/1P & I2T30E 30 V - 2M AMIS AMIS 0.35µ 0.5µ C035 CMOS - I3T80U EEPROM 80 V C5F 4M & - C5N 3M optional (5M on special request) AMIS 0.7µ C07M-A 2M/1P/PdiffC/HR AMIS 0.35µ C035 - I3T50 50 V 4M - 3M optional (5M AMIS on special 0.7µ C07M-D request) 2M/1P austriamicrosystems AMIS 0.7µ C07M-I2T µ CMOS 100V CXQ 2M 2M/2P/HR & 3M option austriamicrosystems AMIS 0.7µ C07M-I2T30 0.8µ HV 30 CMOS V - 2MCXZ 50V 2M/2P/HR austriamicrosystems AMIS 0.7µ C07M-I2T30E 0.35µ CMOS 30 V C35B3C3-2M 3M/2P/HR/5V IO austriamicrosystems 0.35µ CMOS C35B4C3 4M/2P/HR/5V IO UMC L90N Logic/Mixed-Mode/RFCMOS 1P9M lowk austriamicrosystems 0.35µ CMOS C35OPTO 4M/2P/5V IO austriamicrosystems UMC L130E FSG 1P8M 0.35µ Cu HV Logic/Mixed-Mode CMOS H35 50V 3M(HS/SP/LL) austriamicrosystems UMC L130E FSG 1P8M 0.35µ Cu HV Mixed-Mode/RFCMOS H35 50V 4M(HS/SP/LL) austriamicrosystems UMC L180 CIS 2P5M 0.35µ + MMC HV CMOS (Color w/eeprom filter + µlens H35 sup.) 4M/2P - austriamicrosystems OPTO process 0.35µ SiGe-BiCMOS S35 4M/4P austriamicrosystems 0.18µ HV CMOS UMC L180 Logic GII 1P6M 1.8V/3.3V + MMC IHP SG25V 0.25µ SiGe:C Ft=30GHz@BVCEO>7V IHP UMC SG25VD L µ Mixed-Mode/RFCMOS SiGe:C Ft=30GHz@BVCEO>7V+RF 1.8V/3.3V HV- LDMOS UMC L250 Mixed-Mode/RFCMOS 1P5M 2.5V/3.3V IHP austriamicrosystems SG25H1 0.25µ SiGe:C 0.35µ Ft/Fmax=180GHz/220GHz SiGe-BiCMOS S35 4M/4P 4M/MIM IHP austriamicrosystems SG25H2 0.25µ complementary 0.35µ CMOS SiGe:C C35B3C1 3M/2P/5V IO Ft/Fmax (npn)170/170ghz/ (pnp)90/120ghz 4M/MIM austriamicrosystems 0.35µ CMOS C35B4C3 IHP SG25H3 0.25µ SiGe:C Ft/Fmax= 120/140GHz 4M/MIM IHP 4M/2P/HR/5V SG13B SiGe:C IOBipolar/Analog-CMOS Ft/Fmax= austriamicrosystems 250/300GHz 4M/MIM 0.35µ CMOS CSI 3M/2P/5V IO IHP austriamicrosystems SG25H1/H2/H3/VD and 0.35µ SG13B CMOS with C35OPTO Top Metal 4M/2P/5V 2 IO (5 th thick metal) option austriamicrosystems 0.35µ CMOS w/eeprom C35 4M/2P TSMC 0.25µ CMOS General LOGIC, MS OR MS RF austriamicrosystems 0.35µ HV CMOS H35 50V 3M & 4M TSMC 0.18µ CMOS General LOGIC, MS OR MS RF TSMC austriamicrosystems 0.13µ CMOS General 0.8µ LOGIC, CMOS MS CXQ or MS 2M/2P/HR RF (8-inch) TSMC austriamicrosystems 0.13µ CMOS General 0.8µ LOGIC, CXZ 2M/2P/HR MS or MS 50V RF (12-inch) UMC IHPL250 SG25H1 1P5M MM/RFCMOS 0.25µ SiGe:C Ft/Fmax=180GHz/220GHz UMC L180 1P6M GII Logic/LL 4M/MIM UMC L180 1P6M GII Logic + MiM IHP SG25H1/H2/H3/VD with 5th thick metal option UMC L180 1P6M MM/RFCMOS UMC IHPL180 SG25H2 CIS 1P4M 0.25µ Conventional comp. SiGe:C diode 4M/MIM UMC IHPL180 SG25H3 CIS 2P4M 0.25µ SiGe:C Ultra diode Ft/Fmax= 120/140GHz 4M/MIM UMC IHPL130E SGB25VD 1P8M FSG 0.25µ Logic SiGe:C + MiMFt=30GHz@BVCEO>7V+RF UMC L130E 1P8M MM/RFCMOS HV-LDMOS UMC L90N 1P9M2T1F Low K Logic IHP SGC25B 0.25µ SiGe:C Ft=120GHz/4M/MIM UMC L90N 1P9M2T1F Low K Logic/MM Supply Supply Partners Partners IMEC IMEC is working is working together together with with several several partners partners to to get access to wafer fabrication, assembly and test. get access to wafer fabrication, assembly and test. Foundry partners AMI Semiconductor Foundry partners (AMIS) austriamicrosystems austriamicrosystems IHP IHP UMCTSMC Assembly UMC partners ASAT ASE Assembly partners ASE Edgetek Edgetek HCM HCM Selmic AMI Semiconductor (AMIS) Library partner Virtual Library Silicon partners Faraday ARM-ARTISAN Test partners ASETest partners DELTA ASE MASER Engineering Microtec Microtec Microtest Microtest Rood Technology MASER Engineering mini@sic prototyping mini@sic prototyping conditions for universities conditions and research for universities and research laboratories laboratories In order to stimulate universities and research laboratories to prototype their ASIC designs, Europractice has In order to stimulate universities and research laboratories to introduced prototype in 2003 their the ASIC concept designs, of mini@sic. Europractice has introduced in 2003 the concept of mini@sic. That means that Europractice has selected several MPW That means runs in that different Europractice technologies has on selected which universities several and research labs can prototype very small ASIC designs MPW runs in different technologies on which universities and research labs can prototype very small ASIC with reduced minimum prototype fee as follows : All MPW runs in AMIS technologies are open to designs with the mini@sic reduced conditions minimum with prototype minimum fee prototyping as follows : fee of equivalent of 2mm 2 All MPW (4mm runs 2 for in AMIS non-european technologies customers) are open to the mini@sic Selected conditions MPW with runs minimum selected prototyping austriamicrosystems technologies fee of equivalent of 1 mm 2 are open to the mini@sic conditions with minimum prototyping fee of equivalent Selected MPW runs in selected austriamicrosystems of 3 or 2mm 2 technologies (5 or 4mm are open to the mini@sic conditions 2 for non-european customers) with minimum All MPW prototyping runs IHP technologies fee of equivalent are open of 4 to orthe 5 mm 2 mini@sic conditions with minimum prototyping fee All MPW of runs equivalent in IHPof technologies 0,5mm 2 are open to the mini@sic (1,0mm conditions 2 for non-european with zero minimum customers) prototyping Selected MPW runs in UMC 0.18μ, 0.13μ and 90nm fee CMOS mixed/rf technology are open to the mini@ Selected MPW runs in UMC 0.18µ and 0.13µ CMOS sic conditions with minimum prototyping fee of mixed/rf equivalent technology of ~2.3mm are open 2. Special to the conditions mini@sic for conditions CMOS: with minimum ~3.5mm 2 prototyping for 7,000 (15,500 fee of equivalent for non- 90nm of ~ 2.3 European mm 2 customers). europractice a total solution 9

12 Europractice offers full full test test solution solution Electrical Test Additional services Electrical Electrical test Testof Analog, Digital, Mixed ASIC s Laser marking Electrical test of Analog, Digital, Mixed ASIC s Multilayer boards (up to 12 layers) Single and Multi-site test Dry pack and Vacuum seal Single and Multi-site test Stud probing, V-probes Wafer test under cleanroom class 1000 up to 8 wafers Barcode labelling Wafer test under cleanroom class 1000 up to 8 wafers Characterisation: Cp and Cpk datalog Yield and process monitoring Final Yield test and on process each type monitoring of package Failure analysis Multilayer Final test boards on each (up type to of 12 package layers) Decapsulation of plastic packages Stud probing, V-probes Reliability and qualification test Characterisation: Cp and Cpk datalog The product can be qualified according to the military standards for: Space qualification Reliability and qualification test Medical qualification The product can be qualified according to Industrial qualification the military standards for: Consumer qualification Space qualification Medical 1. Qualification qualification Industrial Visual Inspection qualification Consumer High Temperature qualification Operating Life test (HTOL) Low Temperature Operating Life test (LTOL) High 1. Qualification Temperature Bias (HTB) Latch-up Visual Inspection test ESD High HBM, Temperature CDM Operating Life test (HTOL) Low Temperature Operating Life test (LTOL) High Temperature Bias (HTB) Latch-up test Burn-in ESD and HBM, life CDM test Static and dynamic burn-in Probe Bench & Curve Tracer 2. Package Reliability Temperature Cycle Test (TCT) Temperature Humidity Bias (THB) High Accelerated Stress Testing (HAST) Pressure Cooker Test (PCT) Gross/Fine Leakage Test PIND Vibration, centrifuge, solderability Moisture level qualification Bondpull and die shear SEM, SAM, X-ray, EMI imaging Optical Microscopy Plasma Etching Design kits Max 2. Package clockfreq Reliability up to 40 MHz Designers need the necessary information HTOL Temperature Cycle Test (TCT) (design rules, electrical parameters, cell Design kits Temperature Humidity Bias (THB) library, etc.) of the chosen technology before necessary they can infor- start the design phase. Additional services High Accelerated Stress Testing (HAST) Designers need the Laser marking Pressure Cooker Test (PCT) mation (design rules, All this electrical information parameters, cell library, etc.) foundry of the in the chosen so-called tech- design kit. is put together by the Dry pack and Vacuum seal Gross/Fine Leakage Test Barcode labelling PIND nology before they EUROPRACTICE can start the design distributes phase. more than 55 Vibration, centrifuge, solderability All this information different is put together design kits by the and foundry cell libraries in the of Failure analysis Moisture level qualification so-called design the kit. supported EUROPRACTICE technologies distributes for most more popular CAD kits tools and (Cadence, cell libraries Mentor of the Graphics, sup- Decapsulation of plastic packages Bondpull and die shear than 55 different design SEM, SAM, X-ray, EMI imaging ported technologies Synopsys, for most Tanner, popular etc.) CAD on tools CD-ROM. (Cadence, Optical Microscopy Burn-in and life test Mentor Graphics, Synopsys, Customers Tanner, can have etc.) a on copy CD-ROM. of the CD-ROM Plasma Etching Static and dynamic burn-in Customers can have with a copy the cell of the libraries CD-ROM & design with the kits cell by libraries & design kits ing by a Non-Disclosure signing a Non-Disclosure or Design Kit or License De- sign- Probe Bench & Curve Tracer Max clockfreq up to 40 MHz HTOL sign Kit License Agreement Agreement with with EUROPRACTICE. EUROPRACTICE. 10 europractice a total solution

13 WEB site The Europractice IC web Service site web for IC site prototyping provides full information been such totally as: renewed and provides full in- has formation Technologies such as: Technologies Specification sheets Specification Available and sheets supported cell libraries and design kits Available MPW runsand supported cell libraries and design MPW prices kits MPW Small runs volume possibilities MPW Deep prices submicron netlist-to-layout service Small Procedures volume for possibilities registration of designs for prototyping Deep Etc. submicron netlist-to-layout service Procedures for registration of designs for prototyping Etc. Europractice-online Europractice-online In 2003 Europractice introduced Europracticeonline, a platform for information exchange. This In 2003 platform Europractice is hosted introduced by IMEC s Europractice-online, Microelectronics a platform Training for information Center. exchange. This platform is hosted by IMEC s Microelectronics Training Center. Users can register to access information available on Users Europractice-online. can register to access The information information that available is on available Europractice-online. is grouped per The technology information and that contains: is available is grouped Public information per technology and contains: Confidential Public information information in closed domains, accessible Confidential after information signature in of closed Non-Disclosure domains, accessible after signature Agreement or Design of Kit Non-Disclosure License Agreement Agreement or News Design flashes Kit License Agreement Frequently News flashes Asked Questions Mailing Frequently lists Asked Questions Mailing lists The user can personalize the mailing lists in such a way that he is automatically informed by whenever a new The user document can personalize is posted, the news mailing is posted, lists in FAQ such is posted, a way that etc. he The is user automatically can choose informed for which by technologies whenever he will a be new notified. document As such is posted, managers news can is posted, select to FAQ be is informed posted, on etc. latest The user news, can whereas choose designers for which can technologies ask to be he notified will on be all notified. new items As such for managers a specific can technology. select to be informed on latest news, whereas designers can ask to be notified on all new items for a specific technology. europractice a total solution 11

14 Europractice Research Europractice Academic Results Results MPW prototyping service Industry + non- European univ/research 31% ASICs prototyped on MPW runs ASICs In 2007, prototyped a total of 539 on MPW ASICs runs have In been 2005, prototyped. a total of 450 Whereas ASICs have the been number prototyped. of designs Whereas on MPW the number have of been designs decreased on MPW over runs the have last runs been years, decreased we are very over much the pleased last years, to we see are an very increase much in pleased 2007, after to see consolidation again in 2004 and 2005, an increase as 71% well of the as for designs designs are from sent Euro- in by European universities, research and research institutes laboratories as from industry. while the remaining 69% 29% of the designs are is being sent in sent by European in by non-european universities universities and research and laboratories companies world-wide. while the remaining 31% of the designs is being sent in by Geometry non-european mix universities and companies Year over year world-wide. we see a shift towards newest technologies. Also in Geometry 2007 the same mixtrend is shown. The Year majority over of year the designs we see is a still shift being towards newest technologies. Also in Industry + non-european univ/research 29% Europractice Research 15% MWP designs in 2005 Europractice Academic 54% 2005 Europractice the same Research trend is 16% shown. The Europractice Academic 55% 2004, 54 in 2003). This is a big increase in 2007and confirms that reducing majority of the designs MPW is now designs being done in 0.35µ and below (77%) done in while 0.35μ a and few years below ago while thea majority few years of ago the the designs majority was of still the done designs in 0.7/0.8µ. was still done in 0.7/0.8μ. We see also that for the first time, mini@sic the number of designs in 0.35μ is Very decreasing encouraging while is the the number fact that of the designs the prototyping cost for education mini@sic helps to stimulate universities to be Very more encouraging active ASIC is the design. fact that the mini@sic Interesting concept to see was is that accepted under very the well mini@sic by universities conditions, in 2007 the more with 207 advanced prototyped technologies (140 are in even 2006). more designs used (due to the drastic price re- 0.25μ concept technologies was accepted and beduction). mini@sic Geometry mix very yond well is increasing. by 450 universities in 2005 with 139 designs prototyped (90 in >1µ µ 0.35µ 0.25µ 0.18µ 0.13µ 90nm Industry Industry + non-european + non-european univ/research univ/research Europractice Research Europractice Research Europractice Academic Europractice Academic europractice results

15 0.18µ 26% 0.25µ 13% MPW designs in 2007 technology node and number of designs % 0.7/0.8 21% Europractice Research % 21% Europractice Academic 55% Small volume projects More and 0.5/0.6 more 5% customers are using the COT (Customer Own Tooling) % model when they need vol- ume production. Through this COT model they have full control about every aspect of the total design and production flow. Large customers % with sufficient ASIC starts and volume production can invest MPW designs in 2007: technology node and number of designs MWP designs: technology used: 2004 in the COT model as it requires a Geometry mix considerable knowledge and experience about all aspects such as % libraries, design kits, transistor /0.8 20% % models, testing, packaging, yield, 350 etc. For smaller customers the COT 0.5/0.6 3% 300 model is very attractive but very % difficult due to the lack of experience. For those customers EURO- 200 PRACTICE offers the solution by 150 guiding the customers through the full production flow applying the 100 COT model. EUROPRACTICE helps % MWP designs: technology used: 2005 you with technical assistance in 0 the selection of the right package, 600 >1µ µ 0.35µ 0.25µ 0.18µ 0.13µ 90nm setting up the test solution, yield 500 Geometry mix analysis, qualification, etc nm µ µ non-european µ Industry + univ/research Europractice Research µ 237 Europractice Academic & µ & Through EUROPRACTICE you can also experience the benefits of the COT model % 0.7/0.8 9% 0.5/0.6 2% % mini@sic designs per gatelength µ 5% 0.13µ 19% 90nm 4% 0.35µ 33% By courtesy of IMEC nm 0.13µ 0.18µ 0.25µ 0.35µ Industry + non-european univ/research 29% % µ 26% mini@sic designs per gatelength mini@sic designs per gatelength in µ 13% % Europractice Research 16% Europractice Academic 55% MPW designs in 2007 technology node and number of designs europractice europractice results results Geometry mix

16 EUROPRACTICE is offering its services world-wide EUROPRACTICE has offered since 1996 its low cost ASIC MPW prototyping services to customers from 48 countries worldwide. As the service is based in Europe, the majority of the designs come from European customers. But the interest from non-european countries is growing fast. Europractice MPW prototypes in designs being submitted from customers from 33 countries. A strong increase compared to the 433 designs in Traditionally a strong activity in Germany and in overall good activity in all European countries. We notice an increase interest in the Europractice service from customers from countries like USA and India europractice results

17 EUROPRACTICE is offering its services world-wide EUROPRACTICE has offered since 1996 its low cost ASIC MPW prototyping services to customers from 48 countries worldwide. As the service is based in Europe, the majority of the designs come from European customers. But the interest from non-european countries is growing fast. Total designs EUROPRACTICE has offered since 1996 its low cost ASIC MPW prototyping services to customers from 50 countries worldwide. As the service is based in Europe, the majority of the designs come from European customers. But the interest from non-european countries is growing fast europractice europractice results results 15

18 Examples of ASIC projects Digital Circuits - Low power memories Katholieke Universiteit Leuven, Belgium Contacts: W. Dehaene, P. Geens, S. Cosemans, A. Vignon [email protected] Technology: UMC 90nm Mixed-signal Description Seen today s paradigm shift towards a wireless world, battery operated devices are becoming the standard. In this wireless world energy efficiency has not only become a sales argument, but also a necessity. Cooling, and thus power dissipation, becomes more and more problematic for small sized applications. In an ubiquitous computing environment (smart dust) energy has to be harvested in the environment, yielding very small amounts of power... At the same time the performance demands on the devices increase, from GSM to UMTS functionality while providing a longer battery lifetime.. The combination of this ultra low power and performance requirements demands for a highly scalable design. This high scalability leads to systems that are very versatile and can operate at the optimum of the power versus speed trade-off. With the advent of ultra-deep submicron technologies, the leakage currents in circuits start to dominate the total power consumption. At the same time, the impact of variability on the performance of circuits becomes unacceptably large. As the existing design methodologies and tools are unable to cope with these new challenges, new methodologies and circuitry have to be developed. This research Figure 1: 3 prototypes of low power memories project has taken up that challenge. Embedded SRAM memories have been chosen as a first proving ground for these new methodologies and circuitry. Their regular structure and their rising importance in the power budget of contemporary systems make them an excellent target. In a SRAM the majority of cells is not being actively accessed on one given time. This makes that the leakage currents dominate the power budget. A SRAM chip has been developed that reduces the power consumption by selectively reducing the supply voltages on non-activated words. This chip, which is currently being tested, is expected to accomplish a factor 10 in total power reduction. To reduce the impact of variability on memory performance, advanced new memory architectures have been developed. In these architectures, the constraints on the memory cells are greatly relaxed, mainly through smart subdivision of the bitlines. These more relaxed cell constraints solve most problems regarding cell stability and reduce the variability of the memory delay due to intra-die variability. Furthermore, these new architectures reduce the active energy consumption. A memory has been designed using such a new architecture. Why Europractice? Europratice allows us to have access to state-of-the-art technologies at affordable prices. The strong front end support with the software design tools, fabrication process design kits and the back-end support for design verification and design submission for fabrication, gives us the logistical infrastructure we need for our designs at the fore front of development and academic research. Without Europractice academic research on integrated circuits would be impossible in Europe. 16 europractice examples

19 A field programmable analog array for continuous-time analog filters University of Freiburg, Germany Department of Microsystems Engineering (IMTEK) Contact: Yiannos Manoli, Joachim Becker Technology: UMC 0.13 um 1P8M2T MM/RFCMOS Die size: 1.5 mm x 1.5 mm Description - application Due to the high demands in time and cost of integrated circuit design, rapid-prototyping has become an important field of microelectronics. The laboratory for microelectronics at the department of microsystems engineering (IMTEK) at the university of Freiburg, Germany, develops field programmable analog arrays (FPAAs) for reconfigurable instancing of continuous-time high-frequency filters. In the latest hexfpaa chip, 55 tunable Gm-cells with a GBW of 186 MHz are arranged in a hexagonal grid. Through this special topology, it it possible to enable reconfigurable signal routing without switches in the signal path by switching the power supplies of the Gm-cells and yet provide all connectivity necessary for all orders of feedback needed in such filters. The figures illustrate the layout of an array with 7 CABs, which features 6 inputs and one fully enclosed CAB. Each CAB consists of one current summation node, which can be represented by one state variable of a filter. The integrating capacitance at each node is made up of the parasitic inputand output-capacitances of the numerous Gm-cells connected to the node. Since the network topology is fixed and always connected, these capacitances can be held constant. A complex filter topology, which can been used for demonstration of the performance of the FPAA, is a 6th order biquad bandpass filter. Through the intuitive system-level structure of the chip, mapping of a filter s system-level schematic to the FPAA is straight forward as the schematic shows. After the availability of the hardware, a test bench has been set up, which allows automated transfer function measurements of the FPAA on an embedded platform. A Genetic Algorithm (GA) has been set up, which is able to map arbitrary filter functions to the FPAA without prior knowledge of the underlying structure. Heart of the GA is the fitness evaluation of single configurations of the FPAA, which is done on the chip hardware, taking into account all parasitic properties of the device under test. Experiments show that the GA delivers functional implementations of desired filter functions on the FPAA. The whole system represents a complete rapid-prototyping platform for high-frequency continuos-time analog filters and delivers an automated design flow from an ideal transfer function description to a working prototype. Why Europractice? The Europractice mini@sic program is a perfect possibility for universities to manufacture designs that are not related to industry collaborations but fundamental research. The excellent service provided by the experienced staff at Europractice provides us with all information needed to successfully implement such advanced mixed-signal circuits in modern CMOS technologies. europractice examples 17

20 EMBRACE Beamformer chip Astron: The Netherlands Foundation for Research in Astronomy Contact: Mark Ruiter, Erik van der Wal, Dion Kant and Klaas Visser Technology: SH25H1 process of IHP microelectronics Die size: 3.4 x 3 mm 2 ASTRON is working on design studies for The Square Kilometre Array (SKA), which should become the world biggest telescope. SKA should become more sensitive and should have a much larger field of view than the present radio telescopes. Several design studies are carried out all over the world. Astron focuses on the development of the Aperture Array concept (EMBRACE), in which 64 elementary antennas are densely packed into a tile and connected with beam-forming circuitry. A tile provides a physical collecting area of around one square metre. The idea is that the station at Westerbork should have a collecting area of 17 m x 17 m and the size of the station at Nancay should have a collecting area of 10 m x 10 m. Analogue beam forming and combiners in the signal chain of the total system are used to reduce the required density of digital receivers. In order to achieve the EMBRACE cost targets both a higher integration density and a lower cost technology are required. Apart from gain stages the beam-former chip will replace roughly 90 percent of the electronics of the current prototype boards. The beam-former chip replaces 8 vector modulators. To meet the targets the chip has been designed in a Silicon Germanium process, a more or less standard Silicon process with Germanium added for high frequency performance while maintaining all the benefits of mainstream Silicon technology. The Astron implementation of a beam former Monolithic Microwave Integrated Circuit (MMIC) for the SKA demonstrator project EMBRACE is carried out in the SH25H1 process of IHP microelectronics. The main reason to go for a BFC is the analogue processing power. The analogue processing power of the chip can be expressed in equivalent number of Flops, as a digital solution would need to perform a similar task. A conservative number leads to 24 GFlops of processing power for signal processing of four antennas. A tile of approximately of 1 x 1 meter size consists of 64 antennas has thus an equivalent digital process power of 384 GFlops. A large number of tiles will form the collecting area. Imagine the digital process power you need for a square kilometre array. Digital processing is not capable of handling now and in the near future this amount of data. The chip will take care of the beam control by means of phase-shift and amplitude control. Four antennas (RF inputs) are connected to the chip, in which two independent beams are generated by a beam forming technique. The design includes a Low Noise differential Amplifier with multiple feedback loops, a polyphase filter, switching and combining network, amplitude correction facility as well as output drivers. All settings of the chip are under full digital control by a SPI interface. A total of 40 buffered registers are interfaced internally to the analogue part, of which some registers are combined as input for D/A conversion. The large ft/fmax is required to accomplish the specified bandwidth of the negative feedback amplifiers implemented in the design. Figure1 Measured phase states of one channel Chip1 EMBRACE Beam-former chip 18 europractice examples

21 RF Power Amplifier with on-chip Lumped Element Wilkinson Power Splitter/Combiner Sabanci University, Faculty of Engineering and Natural Sciences, Tuzla, 34956, Istanbul, Turkey Contact: Tel: Technology: AMS 0.35 SiGe BiCMOS Die Size: 1.25 x 1.2 mm 2 This work represents a 5.2GHz fully integrated operating as class-a mode RF power amplifier with on-chip power combining circuits for WLAN applications. The RF power amplifier (PA), on-chip Wilkinson power combiner and on-chip splitter are designed using AMS 0.35 SiGe BiCMOS technology library elements. Onchip Wilkinson power combiner/splitter are designed with optimum load and source impedance levels for the amplifier block so that no additional impedance matching is needed. This on-chip combining technique can be used in high power single chip transceivers. Designing high power devices at RF frequencies present challenges. The idea of combining power from several small amplifiers to generate high output power is being used for several years in RF industry. For the power combining, the input signal is split into two branches and after amplifying each branch, the signals are recombined at the output. Splitter and combiner are designed and optimized in Agilent ADS (Advanced Design Systems). The AMS library inductors and capacitors which include parasitic are used to design lumped element Wilkinson power splitter/ combiner. The splitter is designed such that input port is matched to 50 ohm and two output ports are matched to optimum source impedances which is the complex conjugate of the amplifier block input impedance. The combiner s output impedance is matched to 50 ohms and two input ports have the optimum load impedance of which is found by load pull simulations. The results for the integrated splitter shows that 4.2 db insertion loss is achieved at 5.2 GHz with all ports matched to the desired impedances (S11, S22, S33 < -20 db) and more than 10 db isolation is obtained between inputs of the two amplifier stages. Note that due to low quality factors of integrated passives (especially inductors) and low source impedances needed by the amplifier stage degrade the performance of the splitter (additional 1.2 db insertion loss). For the combiner case, the desired optimum load impedance level is better than that of the source impedance so that an enhanced performance is achieved. An insertion loss of 3.49 db is achieved with all ports matched to the desired impedances (S11, S22, S33< -20dB) and more than 10 db isolation is obtained between the outputs of the two amplifiers. The complete layout of combined power amplifier which consists of on-chip splitter/combiner and two amplifier blocks is given in the figure. The combined power amplifier simulated using Cadence platform and achieves a gain of 8.48 db, 21,94 dbm output power at 1 db compression point and %18.5 PAE at 5.2 GHz frequency with post layout simulations. The input return loss is less than -20 db, output return loss achieves -15 db and output to input isolation of 15 db is obtained for the combined PA in post layout simulations. This combined PA is very much suitable for IEEE a transceiver applications with its superior performance. Europractice is chosen for this project because it offers extensive availability, affordable prices for universities, fast delivery time and very helpful technical support. europractice examples 19

22 Monolithic CMOS- MEMS for Attogram Mass Sensing Department of Electronic Engineering, Universitat Autònoma de Barcelona, Bellaterra, Spain Contact: Jaume Verd Technology: AMS 0.35um CMOS C35B4C3 Die Size: 730 x 425 µm 2 (pad limited) Description This work presents the development of an ultra-sensitive mass sensor fabricated with the AMS-C35 CMOS technology. The mass transducer is a MEMS resonator constituted by a clamped-free beam or cantilever and two additional electrodes used for electrostatic excitation and capacitive readout purposes. The mass sensing principle is based on measuring the resonance frequency shift of the resonator due to the accreted mass. This kind of transducers has been used as physical, chemical and biological sensors. In our approach, the MEMS transducer is monolithically integrated with the readout CMOS electronics taking advantage in terms of fabrication cost, size, complexity, and portability. The monolithic integration is easily performed by defining the mechanical structures using the top metal layer of the AMS-C35 technology. A simple mask-less wet etching is performed after the standard CMOS process (post-cmos approach) in order to release the resonant structure [1]. The cantilever structure is defined to be 10 μm long (l), 600 nm wide (w), and 750 nm thick (t) presenting a resonance frequency of ~6 MHz, a mass sensitivity as low as ~1 ag/ Hz and a quality factor of 100 in air conditions. In [2] is reported the results corresponding with calibration and real time mass measurements of this device (see Figure). System-on-chip applications demand the integration of the electronics for the cantilever resonance frequency self-tracking. In this sense, the MEMS resonator can be configured as the frequencydetermining element of an oscillator circuit. A modified Pierce oscillator circuit has been implemented to overcome the high motional resistance of the resonator (~25 M ). For a typical averaging time of = 1 s, the oscillator presents a short-term frequency fluctuation of 1.6 Hz that leads to an unprecedented mass resolution for a monolithic MEMS oscillator of 1.4 ag [3]. Why Europractice? The use in our projects of the AMS 0.35μm CMOS fabrication process through Europractice allows us to obtain a fast feedback between the design of small ASICs and the obtaining of experimental results since the frequent MPW runs at a reasonable price. References: [1] J. Verd, A. Uranga, J. Teva, J. L. Lopez, F. Torres, J. Esteve, G. Abadal, F. P erez-murano, and N. Barniol, Integrated CMOS- MEMS with on-chip readout electronics for high-frequency applications, IEEE Electron Device Lett., vol. 27, no. 6, pp , Jun [2] J. Verd, A. Uranga, G. Abadal, J. Teva, F. Torres, F. Peerez- Murano, J. Fraxedas, J. Esteve, and N. Barniol, Monolithic mass sensor fabricated using a conventional technology with attogram resolution in air conditions, Appl. Phys. Lett., vol. 91, pp , [3] J. Verd, A. Uranga, G. Abadal, J. Teva, F. Torres, J.L. Lopez, F. Perez-Murano, J. Esteve, and N. Barniol, Monolithic CMOS MEMS Oscillator Circuit for Sensing in the Attogram Range IEEE Electron Device Lett., vol. 29, no. 2, Feb europractice examples

23 Fig. 2 ASIC floorplanning. A 192-channel Front-End ASIC for a PET mammography scanner INESC-ID, Rua Alves Redol 9, Lisboa, Portugal Contact: Edgar Albuquerque [email protected] Technology: austriamicrosystems CMOS 0.35µm, C35B4C3 Die size: 72 mm 2 Introduction The 192-channel front-end ASIC described here was designed within the framework of a large scale project with the goal of designing and evaluating the prototype of a PET mammography system with a resolution of less than 1 mm. INESC-ID is one of the seven partners of the project and was in charge of the development of the front-end ASIC and also of the data acquisition boards. Description The PET mammography scanner has two detector heads under the patient bed (Fig. 1), each with an array of 3072 scintillating crystals; each crystal is associated with two APDs (avalanche photodiodes), leading to a total of APDs (pixels). The front-end ASIC is a data driven system that receives handle the signals from 192 APDs, which are then am- Fig. 1 Pet mammography scanner. plified, shaped and sampled. The sampled pulses are then multiplexed and routed to the two analogue outputs; if more than two channels are active, a error warning is issued and the additional pulses is ignored. Each ASIC handles the signals from 6 arrays of 32 APDs, thus the whole system will have 64 ASICs (total of channels). The ASIC floorplanning is described in Fig. 2. The input low noise amplifiers have two stages, and perform a charge amplification and a shaping to obtain a 40 ns peaking time. The amplifiers are followed by a wrap-around analogue memory with eleven stages, running at 100 MHz sampling frequency. The channels are arranged in sets of 32, each set corresponding to a full APD array. Each set of 32-channels has its own local digital controller that controls the sampling and readout process. There is a top-level global controller that manages Fig. 3 Die microphotograph. the interface with the outside world. All the analogue outputs are fully-differential, and the digital outputs use LVDS signalling. Relevant statistics (Fig. 3): Total silicon area 71mm2, (approximately 0.37mm2/ channel); 192 channels; Amplifier noise lower than 1300 electrons; Seven digital controllers with a total of gates; 320 I/O pads with staggered arrangement: 192 input pads, 48 I/O pads and 80 power supply pads; 2200 control signals are routed between the analogue and digital blocks; Power dissipation is 700mW (approximately 3.5mW/ channel). Why Europractice? Due to the complexity and large size of this ASIC, fabrication through Europractice was very convenient, since, several iterations have been necessary. Of utmost importance have been the availability of monthly runs and the straightforward design submission via the Internet. europractice examples 21

24 Mixed-signal DfT demonstrator ASIC at the University of Limerick Department of Electronic and Computer Engineering University of Limerick, Limerick, Ireland Contact: Ian Grout Technology: AMS 0.35 µm C35B4 CMOS Die size: 3.58 mm x 3.68 mm Description This mixed-signal ASIC design contains six demonstrator designs for implementing different built-in self-test (BIST) and built-out self-test (BOST) actions for digital to analogue converter (DAC) and analogue to digital converter (ADC) designs. Each core was developed to demonstrate a range of actions to be undertaken for a range of 14 to 18-bit data converters. In addition, an on-chip programmable voltage reference generator circuit based on a switched resistor string arrangement was included. Each circuit can be accessed via an RS-232C interface. The design was created using the Cadence DFWII design suite and the AMS Hit-Kit with the AMS 0.35 µm C35B4 CMOS fabrication process. The ASIC designers were Jeffrey Ryan, Thomas O Shea and Ian Grout. Silicon die layout view The data converter BIST/BOST designs implement various schemes for the digital side of on-chip signal generation, control, results capture, analysis and communications that would be required within a typical BIST/ BOST scheme. Each of the digital cores was developed as RTL VHDL code and synthesised for the AMS 0.35 µm C35B4 CMOS fabrication process. The purpose of this ASIC was to investigate and identify implementation issues relating to the digital circuitry required for such DfT schemes and the integration of test circuitry within mixed-signal IC designs. Why Europractice? The access to the key tool sets for IC design, along with access to a high quality mixed-signal CMOS fabrication process that is provided through the Europractice organisation provided us with invaluable experience for our microelectronic circuit design/test activities. With the high level of support available from Europractice at all stages of the design project, from the front-end design tools through to the fabrication services for realising our designs in silicon, means that we have a well supported methodology to developing evaluation ASICs for our proof of concept work. In addition, the invaluable support provided during the design submission for fabrication provides the necessary means to ensure the best possible design was submitted for fabrication. Silicon die mounted in a 120 PGA package The designers would like to acknowledge the support through the Enterprise Ireland Commercialisation Fund Technology Development project MethoDAC (Mixed-Signal Built-In Self-Test for Next Generation Digital to Analogue Converters) contract no. CFTD/04/ europractice examples

25 A transimpedance amplifier for fast and high resolution measurements on nano-biosamples Dipartimento di Elettronica e Informazione, Politecnico di Milano Contact: Marco Sampietro [email protected] Technology: AMS 0.35µm CMOS C35B4C3 Die size: 460 x 660 µm 2 A transimpedance amplifier was implemented in the 0.35µm CMOS technology, featuring very high sensitivity and wide bandwidth. The foreseen scientific application is in the field of impedance measurement of molecule addressed by the tip of an atomic force microscope (AFM). The designed chip will be placed next to the cantilever to track the current flowing in the sample throw the tip taking all the advantages related to a short connection (see fig. 1). Both high impedance and small allowed electric field onto bio-samples impose current signals very small. Therefore standard transimpedance amplifiers, made by an opamp with a simple feedback resistor, would have not fulfilled our expectations, because of the high noise related to the resistor and the narrow bandwidth achievable with an high value (low current noise) feedback resistor. Not to mention the difficulty and the area consumption related to the integration on the chip of such a high value resistor. An original circuit has therefore been conceived. Such amplifier is composed of an integrator followed by a differentiator stage (see fig. 2): the overall transfer function is the same as a classical transimpedance amplifier but thanks to the absence of a noisy resistor and to the capacitive amplification the resulting sensitivity is enhanced. To avoid the saturation of the integrator, a time continuous feedback network has been designed to drive the DC input current through an active device, which is equivalent, in term of noise, to a very large resistor ( G ). Similar active resistor has been used to design the loop with a very low cut off frequency (100Hz) without affecting the DC gain or the loop stability. Thanks to these adopted solutions, the dimension of the die resulted to be very small (460 x 660 µm 2 ). The achieved high sensitivity, 3fA/ Hz, together with the wide bandwidth (some MHz) and the unlimited measuring time opportunity given by the continuous DC feedback provide it the capability to measure a capacitance with 1aF resolution in only 1 Fig. 1 second even in the case of a small voltage signal (10mV) applied to the sample. The work has been presented at the ISSCC at San Francisco in February Why Europractice? For a project where the transistors are used in a non-conventional way to control fa currents, it is essential to access silicon foundry easily and frequently. The design kit services, the numerous MPW runs together with the availability of a high-quality analog CMOS process, led us to Europractice as natural choice. Fig. 2 europractice examples 23

26 Self-Powered Wireless System-on-a-Chip Sensor Nodes for Hostile Environments Surrey Space Centre, Department of Electronic Engineering, University of Surrey, UK Contacts: Tanya Vladimirova and David J. Barnhart or Technology: austriamicrosystems 0.35µm S35 SiGe BiCMOS Die size: 2 and 7 mm 2 Description A new dimension of wireless sensor network architecture design is emerging where hundreds to thousands of ultra-light low-cost sensor nodes are required to collectively perform a spectrum of distributed remote sensing missions in hostile conditions. The Surrey Space Centre is particularly interested in space applications, with a focus on developing the satellite-on-a-chip concept 1. Wireless sensor networks have enjoyed widespread popularity since their inception in The original SmartDust sensor nodes developed at the University of Berkeley, USA, were based on multichip module (MCM) integration. However, more practical and cost-effective sensor nodes were developed soon after using printed circuit board (PCB) integration, which are now commercially available for numerous applications. At present, there is a renewed community interest in a system-on-a-chip (SoC) sensor nodes. Our SpaceChip programme is currently focused on developing two essential building blocks for a monolithic SoCbased sensor node: a photovoltaic power supply and a survivable processor design. Integrated solar cells on CMOS have remained elusive until the fabrication of our 2 mm 2 test chip in AMS S35, which demonstrated 8% conversion efficiency in simulated space solar conditions. Ongoing research into the integration of a charge pump will make this power usable by 3.3V circuits. Results from a second 2 mm2 test chip should clearly demonstrate the feasibility of this approach in early The purpose of our survivable design architecture is to dramatically improve a CMOS circuit s tolerance to process, voltage, and temperature (PVT) variations and radiation. We believe the solution lies in the novel combination of two well understood techniques: radiation hardening by design (RHBD) and asynchronous logic. Three test chips, two measuring 3.5 mm2 and one 7 mm2, each with different implementations of a microprocessor, are currently in fabrication and will soon undergo functional and environmental testing, which promise to demonstrate the advantages of this approach. The application of asynchronous logic alone has already shown a 30% power savings in simulation 2, soon to be verified in silicon. Figure 1. View of Asynchronous RHBD Test Chip We gratefully acknowledge funding for this project from the U.S. Air Force Research Laboratory (AFRL), European Office of Aerospace Research and Development (EOARD), grant number FA Why Europractice? The University of Surrey is an active member of EUROPRACTICE, utilising the spectrum of software licensing services and MPW services. The availability of taped-lid ceramic packaging is the key to supporting environmental testing. We are particularly grateful to the Microelectronics Support Centre staff at Rutherford Appleton Laboratory and the IMEC staff in Belgium for their expert support and advice, which has ensured the success of our research. Endnotes 1 D. Barnhart, T. Vladimirova, and M.N. Sweeting. Heterogeneous System-on-a-Chip Design for Self-Powered Wireless Sensor Networks in Non-Benign Environments, Proceedings of 2007 IEEE Aerospace Conference, ref. # 1362, 3-10 March 2007, Big Sky, MT, US. 2 D. J. Barnhart, T. Vladimirova, M. N. Sweeting. Design of Self- Powered Wireless System-on-a-Chip Sensor Nodes for Hostile Environments, to appear in Proceedings of 2008 IEEE International Symposium on Circuits and Systems, ISCAS 08, May 2008, Seattle, Washington, US. Figure 2. View of satellite-on-a-chip concept figure 24 europractice examples

27 3D time of flight Camera Lab for Micro- & Photonelectronics (LAMI), Vrije Universiteit Brussel, Belgium Contact: Prof. Maarten Kuijk, Technology: AMS 0.35 µm CMOS Die Size: 1.5 x 1.5mm 2 Description Time of flight (TOF) ranging is a method whereby a lightpulse is sent to the scene, and it is measured how long it takes for the reflection to return on a detector for determining the travelled distance of the light. This TOF principle can also be performed in parallel by illuminating a larger area of the scene with the light pulse. At the receive end one will then use a lens to image the illuminated part of the scene on a sensor chip containing an array of pixels. This chip will then measure the distance on a pixel per pixel basis. In this way the camera calculates a 3D image, which shows where objects are in the scene, and what the shape of these objects are. This can be achieved in real time making it useful for many applications in the fields of automotive, robotics, surveillance etc... Since pixels need to be small, there is only limited room for electronics circuits. With these limited resources it becomes difficult to distinguish the returned current pulse from the noise. One way of solving this signal to noise issue is to permanently oscillate the light (e.g. at 20 MHz) and then to mix the incoming light with the signal that was used to modulate the light. This delivers decomposition into I and Q, which is then used to derive phase information, from which the distance to the camera can easily be calculated by using the speed of light. The mixing and integration of the received (very weak) signal is a method that is also used in cell-phone front ends, and has shown to deliver very sensitive receivers. To achieve noiseless mixing, we worked at the VUB on a novel approach on device level that further delivers a mixing efficiency that is close to 100% for infrared light (860nm). To achieve this mixing of photo generated electrons, we apply a small majority current through the substrate, in that way letting them drift to the collector of our choice. By oscillating this majority current we obtain high speed, high quality mixing, at the expense of a little current. 1 The scene is illuminated by cheap near infrared LEDs that permanently oscillate at 20 MHz, giving real time depth images at a 50 frames per second. Figure 1 shows a camera that is based on this mixing substrate detector and has 32 x 32 pixels of 30 m square pixels. A resolution is achieved in the LAB of about 2-cm, in a range of 50-cm up to 6-m using 16 standard LEDs. An infrared filter is positioned between the lens and the CMOS sensor chip to lower the adverse effect of visible background light. Why Europractice? The Europractice route to chip development was of great use to this project. The TOF research is of a type that requires more iterations than the design of an analog, digital or mixed-signal circuit. Since the pixels have a very different functionality with respect to a typical CMOS image sensor pixel, knowhow had to be built up. There were so many questions to be answered on the new detector principle, on the subsequent detector circuits and on their interaction, that several years of research based on several chip-submissions a year were necessary. This wouldn t have been possible without Europractice allowing quick turn-around and the affordable mini@sic program. [1] Photonic Demodulator With Sensitivity Control Van Nieuwenhove, D.; van der Tempel, W.; Grootjans, R.; Stiens, J.; Kuijk, M.; Sensors Journal, IEEE Volume 7, Issue 3, March 2007 Page(s): europractice examples 25

28 Retina chip University of Ulm, Department of Microelectronics Contact: Prof. Albrecht Rothermel Technology: Austriamicrosystems 0.35µ C35 OPTO Retinal implants are developed to restore visual perception in blind patients. The retina can be stimulated from either side (epiretinal [1] or subretinal [2,3] ). With a subretinal light sensitive chip, the natural optical system of the eye is still used, allowing the patient to intuitively locate objects. 7 patients have been implanted in a clinical study in 2006 in Tuebingen, Germany [4] with predecessor of this design. The experiments [4] used a device including a light sensitive CMOS chip and separate direct stimulation electrodes. The device was connected to external power supply by a polyimideribbon (comparable to [2], however much longer), forming a flexible connection into the eyeball. Feasibility of the wired supply approach for humans was proven; no perception of the ribbon was reported by the patients. After 5 weeks, all implants were removed, and no damage of the patient s retina was observed. Here we have done the design of a next generation subretinal chip. Main concerns are power and stimulation efficiency, and lifetime. Stimulation voltage swing is nearly doubled from +2V to app. 2V, whereas the power supply is changed from +3V DC to 2V AC. A digital controller is added to address the pixels sequentially, which reduces the peak supply current. The chip will be connected to a separate supply box using the well proven polyimideribbon. The box will be implanted behind the ear and wirelessly supplied from outside like a cochlear implant. To minimize chemical reactions on the periphery, no DC-potential should appear at any terminal of the chip. Fig. 1 shows the concept. A rectifier generates internal V DDCONST and V SS from the external AC supply V H and V L. V H and V L are piecewise linear voltages which are constant during stimulation (several ms) and change polarity fast (within about 125ns, Fig. 1). AC supply directly supports the output drivers. 3 control signals (2 of them analog) are used (brightness reference level I GL, stimulation timing and amplitude limit I IMP, operating mode I SEL ). Low input impedance on-chip amplifiers clamp the control voltages to levels <200mV with respect to ground potential. Figure 2 shows responses of the logarithmic photo sensors of 17 out of 19 available samples. The core of the chip is an active pixel array, with every pixel including a photo sensor, an amplifier, some logic and the output drivers on a (70µm) 2 area. TiN electrode surface is (52µm) 2 leaving 15 x 48µm 2 for the photo diode. Glass opening for electrode contact is (15µm) 2. A 0.35µm CMOS opto technology with 5V I/O option is used. Total chip size is 3 x 3.5mm 2 (active pixel area (2.8mm) 2 ). The circuits for DC-free operation of a CMOS chip might be useful for other implantable devices in the future. Acknowledgements This work was funded by the company Retina Implant AG and the German Ministry of Research and Education. References Figure 2 Figure 1 [1] M. Ortmanns, et al., A 232-Channel Visual Prosthesis ASIC with Production-Compliant Safety and Testability, ISSCC Dig. Tech. Papers, pp , Feb [2] L. Theogarajan et al., Minimally Invasive Retinal Prosthesis, ISSCC Dig. Tech. Papers, pp , Feb [3] E. Zrenner, Will Retinal Implants Restore Vision?, Science, vol 295, no. 5557, pp , 8. Feb [4] E. Zrenner, et al., Psychometric Analysis of Visual Sensations Mediated by Subretinal Microelectrode Arrays Implanted Into Blind Retinitis Pigmentosa Patients, 2007 ARVO Annual Meeting 659/B283, Fort Lauterdale, Florida, May 6-10th, europractice examples

29 During End of 2006 and 2007 we have done three test-chips, to verify the functionality step by step. Chip 1 was to test the rectifier, chip 2 a pixel cell and I/O buffers, chip 3 the array with the addressing scheme. The design (based on chip 3) will be published at the ISSCC Feb in San Francisco, paper no Testchip No. 1 Testchip No. 2 Testchip No. 3 europractice examples 27

30 Fast Multichannel ASIC for Digital X-ray Imaging Systems Department of Measurement and Instrumentation, AGH UST Cracow, Poland Rigaku Corporation, Tokyo, Japan Contact: Pawel Grybos, Taguchi Takeyoshi Technology: AMS 0.35µm CMOS C35B4C3 Die size: 5 x 3.9 mm 2 Description Digital position sensitive X-ray imaging systems working in single photon counting mode require multichannel ASICs for effective readout of an array of the detectors. The critical parameters in such ASICs are low noise performance, good uniformity of analog parameters and proper operation with high rate of input signals. We have designed the 64-channel readout ASIC called RG64 for low energy X-ray imaging systems, which fulfils Fig. 2.: examples of measured diffractograms. the requirements mentioned above. The chip contains four basic blocks: 64 analog front-end channels (charge sensitive amplifiers and shapers), array of discriminators, digital section (counters, RAM and control block) and DACs with testing circuit. Two RG64 chips are combined with a silicon strip detector (SSD) and make up an X-ray detector, namely D/teX Ultra. Replacing a conventional scintillation counter with D/teX Ultra on an in-house X-ray diffraction (XRD) system, one can reduce data acquisition time by 1/100, or improve sensitivity 100 times when the same data acquisition time is applied. In practice, using D/teX Ultra, one can measure a specimen within a minute, or is able to measure a very weak diffraction peak easily. A short data acquisition time is quite useful for quality control purpose and an ability of finding very weak peak may help an environmental study. In addition to this, the RG64 connected to SSD has a capability of photon counting in a narrow, precisely set energy window. This feature is significantly useful to measure a specimen which produces fluorescence X-ray, such as Fe2O3, MnO2, etc. Section of discriminators in each channel allows suppressing fluorescence background considerably without any additional cost. Suppressing fluorescence background improves the data quality and enables accurate data analysis. As described here, D/teX Ultra, a silicon strip detector with RG64 chip, can significantly improve a performance of in-house XRD system. Why Europractice? For the ASIC project on small volume the EUROPRACTICE offers design kit services, frequent MPW runs and provides valuable help at the last stage of project. Acknowledgements The project was realized in several months thanks to using Cadence software. We really appreciate the help from Cadence engineers. Fig. 1.: ASIC layout Fig. 3.: diffractometer equipped with RG64 ASICs and SSD 28 europractice examples

31 EQCO 400T device die image EQCO 400T Equalizer EqcoLogic NV, Brussels Contact: Peter Helfet, CEO Maarten Kuijk, CTO Website: Technology: UMC 0.18µ CMOS mixed mode Die Size: 1.0 x 0.9mm Introduction EqcoLogic is a two year old company, a spin-out of the VUB (University of Brussels). It specializes in analogue high speed communications circuits, with a particular specialism in equalization. Equalizers are sophisticated circuits that recover attenuated signals that have reduced over the reach of a transmission line. This degradation is frequency dependent and is a function of the characteristics of both the signal and the conductor. EqcoLogic s business model includes selective licensing and fab-less product sales. Description The EQCO 400T equalizer is EqcoLogic s first product to be sold under the company s name and was launched in mid The device allows IEEE1394b (FireWire) signals to be transmitted over long lengths of Cat 5 low-cost network cable, at a speed of 500mbit/s (S400). The specification offers up to 80m range, compared to standard, expensive, cables that restrict range to 4.5m without equalization. The equalizer works by analyzing the signal characteristics, by frequency, at the receiver end, using a number of detectors and filters and then compensating for attenuation by selectively amplifying each frequency range. Unlike some competitive systems, EqcoLogic s device is 100% analogue and produced in CMOS, resulting in exceptional performance and low power consumption. The EQCO 400T is designed for production on the UMC 180nm mixed mode CMOS process, an economical and well-proven route. Other EqcoLogic products are also designed for this process or for the more up-to-date 130nm lines. Why Europractice? The EqcoLogic team had long experience of collaborating with Europractice while operating within the VUB. It seemed natural to explore their competence for prototyping and production services after the company was formed. We continue to use MPW runs for prototyping new product designs while running our EQCO 400T production and packaging through Europractice. In fact the Europractice group has proved an excellent partner, giving us access to world-class resources. They have also proved responsive, doing their best to give us fast turnaround and, where possible, meeting special requests. europractice examples 29

32 Dual-Band Receiver Chip Set for GALILEO/ GPS applications Advanced Communications Research & DEvelopment - ACORDE, Santander, Spain Contact: Marco Detratti [email protected] Technology: UMC 018µm CMOS 1P6M Mixed-Moder RF Die Size: Full 5x5 mm 2 slots were used in both runs, but since several configurations were included (test structure and redundant and fallback circuits), the exact area is not clearly identified. Description The GREAT project is one of the active projects co-funded by the European GNSS Supervisory Authority (GSA) with funding from the 6 th Framework Programme of the European Community for research and technological development, devoted to the study and implementation of the technologies for the next generation navigation devices. As part of the project, research and development activities focused on GNSS receivers for handset terminals have been carried out. In this context, ACORDE is developing an RF subsystem, able to operate with Galileo and GPS satellite signals in the presence of the major 2G/3G cellular signals, or other assistance technology, and investigating the multiband approach. The key focus is on a highly integrated Radio Front-End suitable for use within the mobile phone environment, for location based services, satisfying the basic requirements for a mass market receiver such as low cost, low footprint, good accuracy, low power consumption and high sensitivity. The target is a Galileo E1/ E5A and GPS L1/L5 Dual-System Dual Band switching GNSS receiver. Firstly, main individual building blocks of the receiver (two LNAs, Synthesizer with VCO, downconverter, VGA and filters) have been sent for fabrication and tested [1]. At present the second integration step is being carried out with the fabrication of a set of multifunction chips including a dual band LNA, a downconverter with integer synthesizer and a broadband IF section comprising a digitally controlled VGA and a tunable filter. The complete multi-chip assembly could be housed in a low cost 4x4mm 2 package. Expected performances are an overall NF of 2.5dB with 115dB gain, 9MHz Bandwidth; consuming results could be considered a big step in the performance of broadband GNSS receivers for handset applications. Why Europractice? In this type of R&D project, it is of utmost importance to have access to as much information and characterization results as possible. In this sense, the UMC MM/RF 018um CMOS technology has very good libraries and design kits for different type of simulators. Moreover, this technology could offer the trade-off between process maturity and device performance required by the targeted application. Also the cost and number of available MPW runs, together with the possibility of cutting the MPW slot into multiple subcircuits trough Europractice, made this solution the most cost effective. [1] M. Detratti, E. López, E. Pérez, and R. Palacio, Dual-Band RF Front-End Solution for Hybrid Galileo/GPS Mass Market Receivers, Proceeding of the Fifth IEEE CCNC, January 2008, Las Vegas (USA) 30 europractice examples

33 Image Sensor design for space applications ISAE-SUPAERO Integrated Image Sensor Lab Toulouse France Contact: Pierre Magnan Technology: UMC CIS 0.35μm Die size: 21.2mm x 12.2mm (58 I/Os) The DEMOS chip has been developed in the frame of a collaborative R&D program with EADS-Astrium, one of the wordwide leader of satellites and space instruments, as demonstrator chip dedicated to multi-spectral pushbroom imaging from a satellite plateform. In this application, the image sensor is placed at the focal plane of an optical instrument observing the Earth, carried by a satellite. In order to get data from various natural environnements (water area, coastal zones, soils, vegetations, agricultures, geology), the observation is performed in several spectral bands in the visible and Near Infrared domains thanks to dedicated pixel lines being covered by spectral filters. The line width, in conjunction with optics, determines the swath width on the Earth and the natural motion of the satellite around it provides a free scanning of the surface along the track (pushbroom imaging - figure 1). The DEMOS sensor is a special 2D (figure 2) device Figure 1. featuring multiple pixel lines including one PANchromantic (black Figure 3. DEMOS chip layout and white) channel and nine coloured channel (XS), each being specialized in a narrow spectral band thank to a special line filter added post chip fabrication. It is based on Active Pixel Sensor (APS) pixel structure using a photodiode as photodetector. The PAN channel has twice the resolution (pixel pitch 7.5µm) of the XS channels and it has its own pseudo-differential output port. The XS channels (pixel pitch 15µm) are multiplexed to a common output port. The readout circuits of each line has been designed to perform a Correlated Double Sampling readout eliminating the reset noise and providing a low noise figure. Thanks to the use of optimized image sensor CMOS process from UMC, the photodiode do feature low dark current and very good charge collection efficiency providing high detection efficiency and low crosstalk. This DEMOS chip is part of an internal multiproject wafers using the Figure 2. DEMOS sensor organization whole reticle area, including also 12 small 2D (128x128 pixels) arrays for R&D purpose. The DEMOS architecture is candidate, after further customization, for the VNIR detector of the ESA Sentinel 2 mission from the European GMES program. Why Europractice? We have been using CMOS process for research (PhDs) and R&D programs since 1996 either through MPW runs or dedicted batch. The very high electro-optic performance level required for space applications have lead us to move since 2003 to CMOS process optimized for imaging applications. With the help of Europractice IMEC- UMC team, we have launched several UMC 0.35µ CIS process dedicated batches for R&D demonstrators, organized as internal multiproject wafers (as no shuttle run is available), but also in an operational program for 2D arrays for geostationary Earth observation in We do really appreciate being able to access so specialized process, normally devoted to high volume projects, in small batches and so limited cost. Its a key element for achieving high performances, low volume custom systems for space instruments. We do appreciate very much the support and reactivity from Europractice and UMC teams. With their help, we do now move to the 0.18µm CIS generation. Figure 4. DEMOS chip in its package europractice examples 31

34 A 128x128 CMOS Single-Photon Image Sensor Cristiano Niclass, Claudio Favi, Theo Kluter, Marek Gersbach, and Edoardo Charbon Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland Contact: Cristiano Niclass Technology: austriamicrosystems 0.35μ HV CMOS (H35 50V 4M) Die size: 42 mm 2 Time-resolved optical imaging has many uses in disciplines such as physics, molecular biology, medical sciences, and computer vision, just to name a few. Deep sub-nanosecond timing resolution, in combination with high sensitivity, is becoming increasingly important in a number of imaging methods. Non solid-state devices enabling picosecond time resolution, such as photomultiplier tubes and microchannel plates, have existed for decades. However, cost and size have limited their use to low-scale and scientific applications. In solid-state technology, single-photon avalanche diodes (SPADs) have become the alternative of choice. Recently, SPADs are even more compelling with the emergence of CMOS implementations and the appearance of multi-pixel designs. In this research work, we present an array of 128x128 highly miniaturized SPAD pixels with a bank of 32 time-to-digital-converters (TDCs) on-chip. The image sensor concept, architecture and first results have been published at the ISSCC 2008 [1]. Fig. 1. Block diagram of the proposed sensor. The sensor consists of a 128x128 pixel array, a bank of 32 TDCs, and a fast parallel readout circuitry. A row decoding logic selects 128 pixels that are activated for detection. The pixels are organized in groups of four that access the same TDC based on a first-in-take-all sharing scheme. The block diagram of the system is shown in Fig. 1. A decoder selects a 128-pixel row. Every group of 4 pixels in the row share a TDC based on an event-driven mechanism. As a result, row-wise parallel acquisition is obtained with a low number of TDCs. Thanks to the outstanding timing precision of SPADs and an optimized TDC design, a typical resolution of 97ps was achieved within a range of 100ns (10-bits) at a maximum rate of 10MSample/s per TDC. The TDC bank exhibits a DNL of 0.08LSB and a INL of 1.89LSB. The 128x128 chip micrograph is shown SPAD array in Fig. 2, along with a detail of the pixel. The pixel measures 25x25 µm 2. The sensor was tested in three steps. First, the TDCs were characterized separately. A 32 TDC Array signal with known timing was injected in the array by means of the calibration multiplexer and the calibration loop functionality I/O was verified. Second, the TDC array was operated in Fig. 2. Photomicrograph of the sensor chip with a measurement mode and pixel detail in the inset. The circuit, fabricated in connected with the SPAD 0.35µm CMOS technology, has a surface of 8x5mm 2. The pixel pitch is 25µm. 32 europractice examples

35 Fig. 3. Measurements of differential non-linearity (DNL) and integral non-linearity (INL) for the worst case TDC at room temperature. array when exposed to ambient light. Measurements in this mode of operation allowed us to explore the entire timing range. The performance of the TDC bank is summarized in Fig. 3. The figure shows the worst-case DNL and INL measured over the entire bank over several days, to verify the effectiveness of calibration over temperature and technological variations. Finally, the chip was exposed to direct pulsed laser illumination, generated by a 637nm solid-state laser source. The pulses were 80ps wide with a repetition rate of 40MHz. The power of the laser was adjusted so as to minimize pile-up distorsion and a TOA histogram was built for each pixel. The chip s overall performance was tested in a breadboard system based on a dual Xilinx Virtex II Pro FPGA. The breadboard was designed to provide all the interface digital signals and a memory support for imager output. The sensor was used to image a 3D scene illuminated by the pulsed laser. Both the 2D and 3D Fig. 4. Experimental 3D image with model picture in inset. The 1 error computed from two subsequent images is 1.4mm. versions of the scene were captured. Fig. 4 shows the resulting 3D image obtained, whereby the total integration time for one frame was 1s, with a worst-case distance error of 1.4mm. Fig. 5 is a performance summary of the sensor chip and its various components. References [1] C. Niclass, C. Favi, T. Kluter, M. Gersbach, E. Charbon, A 128x128 Single-Photon Imager with on-chip Column-Level 10b Time-to-Digital Converter Array Capable of 97ps Resolution, IEEE International Solid-State Circuits Conference (ISSCC), February Parameter Symbol Min. Typ. Max. Unit Pixel Photon detection Ve=3.3V 3 460nm % Photon detection Ve=4.0V 3 460nm % Sensitivity spectrum nm Median DCR 284 Hz Dead time DT 100 ns TDC Tuning of measurement range (10 bits) ns Resolution (LSB) F ps Measurement rate 10 MS/s DNL 0.08 LSB INL 1.89 LSB System Clock frequency MHz Total IO bandwidth 7.68 Gbps JTAG bandwidth 8 Mbps Static power dissipation 33 mw Dynamic power dissipation 150 mw 3D Image Sample Integration time 1 s Illumination average power 1 mw Illumination peak power 250 mw Illumination duty cycle 0.4 % Target area 1 m2 Target m Fig. 5. Performance summary for the image sensor. europractice examples 33

36 List of Customers per country and number of designs they have sent in for MPW fabrication CUSTOMER TOWN Number of ASICs Australia Edith Cowan University Joondalup 11 Motorola Australian Ressearch Centre Botany 1 University of South Wales Sydney 1 Austria A3Pics Vienna 1 ARC Seibersdorf Research Vienna 4 austriamicrosystems Unterpremstaetten 60 Austrian Aerospace Wien 2 Carinthia Tech Institute Villach-St.Magdalen 1 IEG Stockerau 1 Johannes Keppler University Linz 3 MED-el 2 Securiton Wien 1 TU Graz Graz 2 TU Wien Vienna 11 Belarus NTLab Minsk 4 Belgium Alcatel Space Hoboken 4 AnSem Heverlee 3 Browning International SA Herstal 1 Cochlear Technology Centre Europe Mechelen 9 ED&A Kapellen 3 EqcoLogic Brussels 23 Faculte Polytechnique de Mons Mons 8 FillFactory Mechelen 2 ICI - Security Systems Everberg 6 ICSense Leuven 1 IMEC Leuven 139 K.U. Leuven Heverlee 94 Katholieke Hogeschool Brugge-Oostende Oostende 23 KHLim Diepenbeek 6 KHK Geel 10 KIHA Hoboken 2 Macq Electronique Brussel 1 Neurotech Louvain-la-Neuve 1 Q-Star Test nv Brugge 2 SDT International Bruxelles 1 SEBA Service N.V. Grimbergen 1 SIEMENS ATEA Herentals 2 SIPEX Zaventem 4 Societe de Microelectronique Charleroi 1 Universite catholique de Louvain Louvain-la-Neuve 14 Universiteit Gent Gent 58 University of Antwerp Wilrijk 3 Vrije Universiteit Brussel Brussels 72 Xenics Leuven 1 Brazil State University of Campinas - CenPRA Campinas 18 CPqD - Telebras Campinas 7 Genius Instituto de Tecnologia Manaus - Amazonas 3 UFPE Recife-PE 4 UNESP/FE-G Guaratingueta - SP 3 UNICAMP- University of Campinas Campinas, SP 17 Universidade de Sao Paulo Sao Paulo-SP 31 CUSTOMER TOWN Number of ASICs Bulgaria Technical University of Sofia Sofia 2 Canada Canadian Microelectronics Corporation Kingston, Ontario 9 Epic Biosonics Victoria 4 University of Alberta Edmonton 1 University of Toronto Toronto 1 University of Waterloo Waterloo 2 China Dept.Computer Science and Technology BeiJing 1 Fudan University Shanghai 2 Microelectronics Center Harbin 1 The Chinese University of Hong Kong Shatin-Hong Kong 10 Hong Kong Univ. of Science and Technology Hong Kong 4 Zhejiang University Yuquan 1 Croatia University of Zagreb Zagreb 2 Cyprus University of Cyprus Nicosia 1 Czech Republic ASICentrum s.r.o. Praha 4 6 Brno University of Technology Brno 7 Czech Technical University-FEE Prague 5 Denmark Aalborg University Aalborg 38 Algo Nordic A/S Cph 1 Bang & Olufsen Struer 4 DELTA Hoersholm 11 GN-Danavox A/S Taastrup 4 Microtronic A/S Roskilde 1 Oticon A/S Hellerup 10 PGS Electronic Systems Frb. 1 Techtronic A/S Roskilde 1 Tecnical University of Denmark Lyngby 4 Thrane&Thrane Lyngby 1 Egypt Bahgat Group - IEP Cairo 4 Estonia Tallinn Technical University Tallinn 1 Finland Detection Technology Inc. Li 1 Fincitec Oy Oulu 4 Helsinki University of Technology Espoo 5 Nokia Networks Espoo 2 Tampere University of Technology Tampere 8 University of Oulu Oulu 12 VTI Technologies Vantaa 2 VTT Electronics Espoo 95 France Atmel Nantes, Cedex europractice list of customers

37 CUSTOMER TOWN Number of ASICs C4i Archamps 13 CCESMAA -IXL Talence 2 CEA Grenoble 26 CMP-TIMA Grenoble 7 CNES Toulouse Cedex 01 4 CPPM Marseille 2 Dibcom Palaiseau 1 Dolphin Integration Meylan 4 EADS Defense & security 1 ELA Recherche Meylan 4 ENSEA Cergy Pontoise 2 ENST Paris Paris 2 ESIEE Noisy Le Grand 3 IN2P3 - LPNHE - Universites 6 et 7 Paris Cedex 5 8 Institut des Sciences Nucleaires Grenoble 5 Institut de Physique Nucleaire Villeurbanne 7 Institut Sup. d Electronique de Bretagne Brest 2 ISEN Recherche Lille cedex 3 LAAS/CNRS Toulouse 6 Labo PCC CNRS/IN2P3 Paris cedex05 2 Laboratoire de l Accelerateur Lineaire Orsay 6 LAPP Annecy-le-Vieux 7 LEA Cesson Sevigne 1 LEPSI Strasbourg 15 LETI-CEA Grenoble 4 LIRMM Montpellier 2 Midi Ingenierie Labege 1 MXM Laboratories Vallauris 3 NeoVision France Bagneux 3 NXP Semiconductor Caen 2 PMIPS - IEF Orsay 2 SODERN Limeil-Brevannes 2 SUPAERO Toulouse Cedex 6 Supelec Gif-sur-Yvette 3 TTPCOM Sophia Antipolis 1 Universite Pierre et Marie Curie Paris 4 Vision Integree Nogent sur Marne 3 Germany AEG infrarot-module 1 ALV-Laser Vertriebsgesellschaft mbh Langen 1 austriamicrosystems Dresden 2 Balluff 1 Bergische Universitaet Wuppertal Wuppertal 1 Biotronik GmbH & Co Erlangen 9 Bruker AXS 1 Bruker Biospin 3 Cairos Technologies Karlsbad 8 Comtech GmbH St. Georgen 3 Daimler-Benz AG Ulm 3 Darmstadt University of Technology Darmstadt 3 Dr. Johannes Haidenhain 1 ESM Eberline Erlangen 1 ETA Erlangen 1 Fachhochschule Aalen Aalen 3 Fachhochschule Augsburg Augsburg 1 Fachhochschule Bremen Bremen 3 Fachhochschule Darmstadt Darmstadt 9 Fachhochschule Dortmund Dortmund 3 Fachhochschule Esslingen Goeppingen 2 CUSTOMER TOWN Number of ASICs Fachhochschule Furtwangen Furtwangen 6 Fachhochschule Giessen-Friedberg Giessen 13 Fachhochschule Koeln Gummersbach 3 Fachhochschule Mannheim Mannheim 1 Fachhochschule Nuernberg Nuernberg 1 Fachhochschule Offenburg Offenburg 20 Fachhochschule Osnabrueck Osnabrueck 4 Fachhochschule Pforzheim Pforzheim 1 Fachhochschule Ulm Ulm 13 Fachhochschule Wilhelmshaven Wilhelmshaven 1 Fachhochschule Wuerzburg Wuerzburg 1 FAG-Kugelfischer Schweinfurt 3 FH Hannover Hannover 5 FH Karlsruhe Karlsruhe 1 FH Niederrhein Krefeld 5 FhG-IIS Erlangen 168 FH-Münster Steinfurt 1 FORMIKROSYS Erlangen 2 Forschungszentrum Juelich GmbH Juelich 1 Fraunhofer Heinrich - Hertz Berlin 1 Fraunhofer institute silicontechnology Itzehoe 17 Fraunhofer IPMS Dresden 3 Fraunhofer ISC 1 Friedrich-Schiller-University Jena 3 GEMAC Chemnitz 7 Gesellschaft für Schwerionenforschung Darmstadt 23 Geyer Nuernberg 6 GMD St. Augustin 1 Hella 1 Hyperstone AG Konstanz 1 iad GmbH Grosshabersdorf 1 IHP Frankfurt(Oder) 1 IIP-Technologies GmbH Bonn 5 IMKO Micromodultechnik GmbH Ettlingen 3 IMST GmbH Kamp-Lintfort 4 INOVA Semiconductor Munich 1 Institute for Integrated Systemes Aachen 1 Institute of Microsystem Techology Freiburg 2 Jakob Maul GmbH Bad Koenig 1 Johannes Gutenberg-Universitaet Mainz 9 KVG Quatrz Crystal Neckarbisch 1 Lenze GmbH Aerzen 2 LHR Comtech St. Georgen 1 MAN Nüremberg 1 Marquardt GmbH Rietheim-Weilheim 1 Max Planck Institute Munchen 2 MAZ Brandenburg Brandenburg 2 Med-El GmbH 1 MEODAT Ilmenau 2 Metzeler Automotive 3 MPI-Halbleiterlabor Munich 2 NeuroConnex Meckenheim 2 Optek Systems Innovations 1 OPTRONICS 1 Phisikalisches Institut Bonn 2 Preh Werke NA 2 Rechner Industrieelektronik GmbH 1 Rohde & Schwarz München 2 Ruhr-University Bochum Bochum 5 RWTH Aachen Aachen 12 europractice list of customers 35

38 CUSTOMER TOWN Number of ASICs Scanditronix Wellhöfer NA 3 Schleicher GmbH & Co Relais-Werke KG 1 Schleifring und Apparatebau GmbH 2 Seuffer Calw-Hirsau 5 Sican Braunschweig GmbH Braunschweig 1 Siemens 4 Technical University Ilmenau Ilmenau 24 Technical University of Berlin Berlin 11 TESAT-Spacecom Backnang 1 Trias Krefeld 1 Trinamic Hamburg 1 TU Berlin Berlin 5 TU Braunschweig Braunschweig 3 TU Chemnitz Chemnitz 11 TU Darmstadt Darmstadt 11 TU Dresden Dresden 20 TU Hamburg-Harburg Hamburg 28 Universitaet Dortmund Dortmund 2 Universitaet Hannover Hannover 12 Universitaet Kaiserslautern Kaiserslautern 18 Universitaet Paderborn Paderborn 13 Universität Rostock Rostock 7 University of Bonn Bonn 6 University of Bremen Bremen 26 University of Erlangen-Nuernberg Erlangen 5 University of Freiburg Freiburg 9 University of Heidelberg Heidelberg 40 University of Kassel Kassel 5 University of Magdeburg Magdeburg 12 University of Mannheim Mannheim 23 University of Munich Munich 1 University of Oldenburg Oldenburg 1 University of Saarland Saarbruecken 4 University of Siegen Siegen 13 University of Stuttgart Stuttgart 1 University of Ulm Ulm 7 Vishay semiconductor Heilbronn 2 Wellhoeffer Schwarzenbruck 2 Work Microwave GmbH Holzkirchen 1 Greece ACE Power Electronics LTD AG Dimitrios 1 Aristotle Univ. of Thessaloniki Thessaloniki 5 Athena Semiconductors SA Alimos - Athens 2 Crypto SA Marousi 1 Datalabs Athens 1 Democritus University of Thrace Xanthi 3 Found. for Research and Techn.-Hellas Heraklion 1 InAccess Athens 1 HELIC SA Athens 1 Hellenic Semiconductor Applications Athens 2 Intracom Paiania 1 National Tech. Univ. of Athens Athens 16 NCSR Athens 23 NTNU n/a 2 RETECO LTD. Athens 1 Technological Educational Institute of Chalkis Chalkis 1 Unibrain SA Athens 1 University of IONNINA Ioannina 2 University of Patras - VLSI Laboratory Rio - Patras 18 CUSTOMER TOWN Number of ASICs Hungary Hungarian Academy and Science Budapest 1 Peter Pazmany Catholic University Budapest 1 Computer and Automation Inst. Budapest 6 JATE University Szeged 1 India College of Eng. Guindy Anna Univesity Chennai 1 Electronics Corporation of India Hyderabad 8 Indian Institute of Science Bangalore 6 Indian Institute of Technology - Madras Chennai 4 Indian Institute of Science New Dehli 3 VECC Kolkata 6 Ireland Cork Institute of Technology Cork 3 Duolog LtD Dublin 2 National University of Ireland Kildare 1 Farran Technology Ballincollig 1 National Microelectronics Research Cent. Cork 17 Parthus Technologies (SSL) Cork 7 TELTEC Cork 1 University College Cork Cork 9 University of Limerick Limerick 14 Waterford Institute of Technology Waterford 8 Israel CoreQuest Petach Tikva 2 DSP Semiconductors Givat Shmuel 1 Technion - Israel Institute of Techn. Haifa 4 Italy Alcatel Alenia L Aquila 1 Alimare SRL Favria Canavese (Torino) 1 Aurelia Microelettronica S.p.A. Navacchio PISA 18 BIOTRONIC SRL San Benedetto 1 Cesvit Microelettronica s.r.l. Prato 2 DEEI - University of Trieste Trieste 2 INFN Bologna 1 INFN Cagliari 1 INFN Catania 7 INFN Ferrara 1 INFN Milano 3 INFN Genova 2 INFN Padova 2 INFN Roma 2 INFN S.Piero a Grado (PISA) 2 INFN Torino 7 INFN Trieste 8 Instituto di Sanita Roma 2 Fondazione Bruno Kessler Trento 29 ISE Vecchiano 1 LABEN S.p.A. Vimodrone (MI) 3 Neuricam Trento 3 Optoelettronica Italia Terlago 1 Politecnico di Bari Bari 4 Politecnico di Milano Milano 71 Politecnico di Torino Torino 6 Silis s.r.l Parma 1 36 europractice list of customers

39 CUSTOMER TOWN Number of ASICs Sincrotrone Trieste SCpA Trieste 3 SITE Technology s.r.l. Oricola 1 SYEL S.r.l. Pontadera 1 Universita degli Studi Dell Aquila L Aquila 3 Universita di Torino Torino 7 Università degli Studi di Ancona Ancona 4 Universita degli Studi di Firenze Firenze 3 Universita di Cagliari Cagliari 16 Universita di Catania Catania 38 University of Bologna Bologna 23 University of Brescia Brescia 9 University of Genova Genova 13 University of Lecce Lecce 1 University of Modena Modena 3 University of Naples Napoli 4 University of Padova Padova 26 University of Parma Parma 10 University of Pavia Pavia 10 University of Perugia Perugia 7 University of Pisa Pisa 17 University of Rome Tor Vergata Roma 7 University of Siena Siena 2 Japan Marubeni Solutions Osaka 9 Hokkaido University Sapporo 10 Rigaku Corporation Tokyo 1 Yamatake Kanagawa 1 Korea 3SoC Inc. Seoul 1 JOSUYA TECHNOLOGY Taejon 1 KAIST Daejeon 1 Korean Elektrotechnology Research Institute Changwon 1 Macam Co., Ltd Seoul 2 Nurobiosys Seoul 8 Radtek Yusung-Ku, Daejeon 1 Samsung Electro-Mechanics Suwon 1 Seoul National University Seoul 1 Seloco Seoul 15 SML Seoul 4 Lebanon American university of Beirut Beirut 1 Malaysia MIMOS Kuala Lumpur 1 SunSem Sdn. Bhd. Kuala Lumpur 1 University of Technology Skudai 1 Malta University Of Malta Msida 14 Mexico INAOE Puebla 24 Netherlands Aemics Hengolo 8 ASTRON Dwingeloo 1 Catena Microelectronics BV Delft 1 CUSTOMER TOWN Number of ASICs Cavendish Kinetics s Hertogenbosch 1 Delft University of Technology Delft 90 ESA AG Noordwijk ZH 3 Hogeschool Heerlen Heerlen 1 IMEC-NL Eindhoven 9 Lucent Technologies Nederland BV Huizen 1 Mesa Research Institute Twente 1 NFRA Dwingeloo 1 Sonion Amsterdam 3 Smart Telecom Solutions 1 SRON Utrecht 7 Technische Universiteit Eindhoven Eindhoven 44 TNO Industrie Eindhoven 1 TNO -FEL The Hague 13 University of Amsterdam Amsterdam 1 University of Twente Enschede 5 GreenPeak Technology Utrecht 8 Xensor Integration Delfgauw 3 New Zealand Industrial Research Ltd Lower Hutt 4 Norway AME As Horten 1 Nygon Asker 1 IDE AS Oslo 2 Interon Asker 3 Nordic VLSI Trondheim 38 Norwegian Institute of Technology Trondheim 18 SINTEF Trondheim 10 University of Bergen Bergen 6 University of Oslo Oslo 64 Poland AGH University of Science and Technology Krakow 13 Institute of Electron Technology Warsaw 35 Technical University of Gdansk Gdansk 3 Technical University of Lodz Lodz 4 University of Mining and Metallurgy Krakow 24 University of Technology & Agriculture Bydgoszcz 1 University of Technology - Poznan Poznan 1 Warsaw University of Technology Warsaw 15 Portugal Acacia Semiconductor Lisboa 6 Chipidea Oeiras 22 INESC Lisboa 22 INETI Lisboa 1 Instituto de Telecomunicacoes Lisboa 8 Instituto Superior Tecnico Lisboa 6 Universidade de Aveiro Aveiro 18 University of Minho Guimaraes 5 University of Porto Porto 3 ISEL-IPL LIsboa 1 University of Tras-os-Montes e Alto Vila Real 2 Universidade Nova de Lisboa - Uninova Caparica 6 Romania Polytechnic inst. Bucharest Bucharest 1 europractice list of customers 37

40 CUSTOMER TOWN Number of ASICs Russia MIET-TU Moscow 2 Moscow Engineering Physics Institute Moscow 4 University St Petersburg St Petersburg 3 Vladimir State university Vladimir 1 Serbia and Montenegro University of Nis Nis 1 Singapore Agilent Singapore 2 DSO National Laboratories Singapore 6 Slovakia Inst. of Computer Systems Bratislava 1 Slovak University of Technology Bratislava 3 Slovenia Iskraemeco d.d. Kranj 19 NOVOPAS Maribor 1 University of Ljubljana Ljubljana 8 University of Maribor Maribor 1 South Africa Solid State Technology Pretoria 4 University of Pretoria Pretoria 18 South America CNM/Iberchip 74 Spain Acorde S.A. Santander 10 Anafocus Sevilla 2 CNM Bellaterra 41 Design of Systems on Silicon Paterna 7 EUSS Barcelona 1 Facultad de Informática UPV/EHU San Sebastián 2 Technical University of Madrid Madrid 3 Univ. Las Palmas Gran Canaria Las Palmas de G.C. 11 Universidad Cartagena 2 Universidad de Cantabria Santander 20 Universidad de Extremadura Badajoz 18 Universidad de Navarra San Sebastian 32 Universidad del Pais Vasco Bilbao 3 Universidad Politecnica de Madrid Madrid 1 Universidad Publica de Navarra Pamplona 14 Universitat autonoma de Barcelona Barcelona 2 Universitat de Barcelona Barcelona 24 Universitat Illes Balears Palma Mallorca 3 Universitat Politecnica de Catalunya Barcelona 28 Universitat Rovira i Virgili Tarragona 2 University of Malaga Malaga 3 University of Sevilla - CNM - Sevilla 6 University of Seville Sevilla 31 University of Vigo Vigo 3 University of Zaragoza Zaragoza 19 Sweden Bofors Defence AB 2 Chalmers University Goteborg 6 CUSTOMER TOWN Number of ASICs Chalmers University of Technology Gothenburg 66 Defence Researh Establishment Linkoping 5 Ericsson Molndal 2 Ericsson Microelectronics Kista 2 Halmstad University Halmstad 1 Institutet for Rymdfysik Kiruna 1 Imego AB Goteborg 1 Lulea University of Technology Lulea 9 Lund University Lund 168 Malardalens University Vasteras 2 Mid Sweden University Sundsvall 12 Royal Institute of Technology Kista 23 Saab Ericsson Space AB Goteborg 1 SiCon AB Linkoping 4 Svenska Grindmatriser AB Linkoping 3 University of Trollhattan Trollhattan 3 University of Linköping Linköping 151 Uppsala University Uppsala 11 Switzerland Agilent Technologies Plan-les-Ouates 1 Asulab SA Marin 22 austriamicrosystems 2 Bernafon Bern 1 Biel School of Engineering Biel 8 CERN Geneva 5 CSEM Zurich 8 CT-Concept 9 HMT Microelectronics Ltd Biel/Bienne 1 EPFL Lausanne 173 ETH Zurich Zurich 96 Hochschule Rapperswill Rapperswill 1 HTA Luzern Horw 2 HTL Brugg-Windisch Windisch 2 id Quantique Carouge 14 Innovative Silicon S.A. Lausanne 1 Landis + Gyr AG 1 Leica Geosystems Heerbrugg 1 LEM Plan-les-Ouates 3 MEAD Microelectronics S.A. St-Sulpice 2 MICROSWISS Rapperswil 2 Paul-Scherrer-Institute Villigen 15 Photonfocus Lachen 3 Senis Zurich 1 Sensirion Staefa 2 Sentron AG Lausanne 7 siemens Zug 2 Smart Silicon Systems SA Lausanne 2 Suter IC-Design AG Waldenburg 3 University of Neuchatel Neuchatel 12 University of Zurich Zurich 40 Uster Technolgies Uster 1 Xemics SA - CSEM Neuchatel 33 Taiwan Feng Chia University Taichung 1 National Cheng Kung University 1 National Tsing Hua University Hsinchu 4 38 europractice list of customers

41 CUSTOMER TOWN Number of ASICs Thailand Microelectronic Technologies Bangkok 2 NECTEC Bangkok 31 Turkey ASELSAN Ankara 1 Bilkent University Ankara 5 Bogazici University Istanbul 5 Istanbul Technical University Istanbul 15 Kardiosis Ankara 1 Middle East Technical Univ. Ankara 8 Sabanci University Istanbul 6 Tubitak Bilten Ankara 4 United Kingdom Aberdeen University Aberdeen 1 Barnard Microsystems Limited London 2 Bournemouth University Poole 3 Bradford University Bradford 7 Brunel university Uxbridge 1 Cadence Design Systems Ltd Bracknell 1 Cambridge Consultants Ltd. Cambridge 3 Cardiff University Cardiff 5 CML Microcircuits Ltd. Maldon 15 Control Technique Newtown 4 Data Design & Developmentsq Stone 1 Dukosi Edinburgh 1 Edinburgh University Edinburgh 46 Epson Cambridge research lab Cambridge 2 ELBIT Systems Ltd. 1 Heriot-Watt University Edinburgh 2 Imperial College London 22 Jennic Ltd Sheffield 1 K.J. Analogue Consulting Malmesbury 1 King s College London London 1 Lancaster University Lancaster 7 Leicester University Leicester 1 Middlesex University London 6 Napier University Edinburgh 4 Nortel Harlow 1 Plextek Ltd Essex 4 Positek Limited Glos 1 CCLRC - RAL Oxon 44 Roke Manor Research Ltd. Southampton 1 Saul Research Towcester 22 Sheffield Hallam University Sheffield 1 Swindon Silicon Systems Ltd Swindon 3 Tality Livingston 1 The Queens University of Belfast Belfast 3 The University of Hull Hull 1 The University of Liverpool Liverpool 9 UMIST Manchester 48 University College London-UCL London 2 University of Bath Bath 15 University of Birmingham Birmingham 6 University of Brighton Brighton 1 University of Bristol Bristol 1 University of Cambridge Cambridge 26 University of Dundee Dundee 1 University of East London London 1 CUSTOMER TOWN Number of ASICs University of Glasgow Glasgow 30 University of Hertfordshire Hatfield 1 University of Kent Canterbury 13 University of London London 38 University of Newcastle upon Tyne Newcastle upon Tyne 6 University of Nottingham Nottingham 24 University Of Oxford Oxford 19 University of Plymouth Plymouth 2 University of Reading Reading 1 University of Sheffield Sheffield 6 University of Southampton Southampton 20 University of Stirling Stirling 1 University of Surrey Guildford 5 University of the West of England Bristol 2 University of Wales, Aberystwyth Aberystwyth 4 University of Warwick Coventry 4 University of Westminster London 5 University of York Heslington 1 Walmsley (microelectronics) Ltd Edinburgh 1 USA Analog Phoenix 1 austriamicrosystems USA 1 Boston university Boston 6 Brookhaven National Laboratory Upton, NY 1 Columbia University Irvington, NY 17 Discera 1 Duke Universtity Durham 1 Exelys Ilc Los Angeles 2 Eutecus Inc Berkeley 2 Flextronics Sunnyvale 1 Forza Silicon Corporation Pasadena 1 Fox Electronics Fort Myers 5 Future Devices 1 General Electric Niskayuna 3 Glacier Microelectronics San Jose 1 Goddard Space Flight Center, NASA Greenbelt 1 Iwatsu Irving 4 Linear Dimensions, Inc. Chicago 1 Micrel Semiconductor San Jose 7 Microchip Technology 1 MIT - Lincoln Lab Cambridge 16 MOSIS Marina del Rey, CA 28 Nova R&D Riverside 3 Parallax Inc. Rocklin 2 Philips Medical Systems Andover 1 Princeton University Princeton, NJ 4 Rockwell Scientific Thousand Oaks, CA 13 Signal Processing Group Chandler 1 Stanford Linear Accelerator Meno Park 11 Symphonix San Jose 5 Tachyon Semiconductor Naperville, IL 2 Tekwiss USA, Inc Costa Mesa 2 Triad Semiconductor 1 University of California Santa Cruz 1 University of Chicago Illinois 3 University of Colorado Boulder 2 University of Delaware Newark 3 University of Florida Gainesville 3 University of Pennsylvania Philadelphia, Pa. 2 europractice list of customers 39

42 CUSTOMER TOWN Number of ASICs University of Texas at Austin Austin 12 USRA Washington 1 Vectron International Inc. Hudson NH 5 Xerox El Segundo 1 Yanntek San Jose, CA 5 40 europractice a list total of customers solution

43

44 All information for MPW runs schedule, prices, etc. is available on-line on our WEB site design & layout: IC SERVICE ALLIANCE PARTNER For more information, please contact one of the EUROPRACTICE service centers. IMEC General EUROPRACTICE IC office & IC Manufacturing Center C. Das Kapeldreef 75 B-3001 Leuven, Belgium Tel : Fax : [email protected] Fraunhofer Institute for Integrated Circuits (Fraunhofer IIS) Integrierte Schaltungen IC Manufacturing Center W. McKinley, J. Sauerer Am Wolfsmantel 33 D Erlangen, Germany Tel : Fax : [email protected]