Super high-speed, and high density gate array Dual power supply operation Raw gates from 18K to 216K gates (Sea of gates) DESCRIPTION

Transcription

1 PF77- SLA3 Series High Speed Gate Array Wide Voltage Operation Products Super high-speed, and high density gate array Dual power supply operation Raw gates from K to K gates (Sea of gates) DESCRIPTION The SLA3 Series is an SOG-type CMOS gate array featuring the very high-speed operations, high density, and high output drive capability. This series has a full lineup of gate arrays to cover, to, gates for the large-scale, and high-speed systems. They can drive with both +V and +3V supply voltages. This series also has a built-in level shifter to provide dual-power interfacing in various low-voltage applications. The I/O cells supporting the Revision. are available for PCs and peripheral equipments. Also, the micro-ampere order, low-noise output cells are available for portable equipments and instruments of various applications. FEATURES Super-high density (adopting.µm silicon gate CMOS with and 3-metal layers) High-speed operation (operation delay of internal gate =.ns at.v, -input power NAND standard) Selectable supply voltage:.v, 3.3V, 3.V and built-in dual-power supplies level shift circuit Output drivability (IOL = µ,,,, ma when =.V, IOL = µ, µ,,, ma when = 3.3V) On-chip RAM available I/O cells supporting the Revision. and low noise output cells available PRODUCT LINEUP Master -layer Metal SLA3 SLA33 SLA3 SLA3 SLA37 SLA39 SLA3 SLA3 Features 3-layer Metal SLA3T SLA33T SLA3T SLA3T SLA37T SLA3T SLA3T SLA3T Total BCs Dual Power Supply, 3,,,3 7, 9,,3, (Raw Gates) Single Power Supply 3,7 37,3 9, 3,7,, 3, 3, Usable BCs -layer Metal -layer Metal 9,7,3 9,3, 33,9 9,,9, (Dual Power Supply) 3-layer Metal,3,9 3,77,7,, 9,377,3 Usable BCs -layer Metal -layer Meta,7, 3,39 9,97 3,3,3 9, 93,3 (Single Power Supply) 3-layer Metal,73 3,7,3,7,9 9, 3,,7 Number of PADs 3 37 Propagation Delay I/O Level Input Mode Output Mode Internal Gates Input Buffers Output Buffers tpd =.ns (standard at.v), tpd =.33ns (standard at 3.3V) tpd =.ns (standard at.v), tpd =.3ns (standard at 3.3V) tpd =.ns (standard at.v), tpd =.ns (standard at 3.3V) CL = pf CMOS, TTL, TTL, CMOS, Pull-up/Pull-down, schmitt, 3./3.3/.V Level interface (Level shifter) Normal, open drain, 3-state, Bi-directional, 3./3.3/.V Level interface (Level shifter)

2 SLA3 Series ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Power voltage VDD.3 ~. V Input voltage VI.3 to VDD+. V Output voltage VO.3 to VDD+. V Output current/pin IOUT ±(± * ) ma Storage temperature Tstg ~ C *: For cell of ma output current (VSS=V) RECOMMENDED OPERATING CONDITIONS Single power supply Item Symbol Min. Typ. Max. Unit Power voltage V DD.7.. V... Input voltage VI VSS VDD V Operating temperature Topr 7 C C Normal input during input rise time tri ns Normal input during input fall time tfi ns Schmitt input during input rise time tri ms Schmitt input during input fall time tfi ms Dual power supply Item Symbol Min. Typ. Max. Unit Power voltage HVDD.7.. V (High voltage) HVDD... V Power voltage LVDD V (Low voltage) LVDD V Input voltage HVI VSS HVDD V LVI VSS LVDD V Operating temperature Topr 7 C C Normal input during input rise time tri ns Normal input during input fall time tfi ns Schmitt input during input rise time tri ms Schmitt input during input fall time tfi ms

3 SLA3 Series ELECTRICAL CHARACTERISTICS (VDD=V) (VDD = V, VSS = V, Ta = to C) Item Symbol Conditions Min. Typ. Max. Unit Stand-by current * IDDS Stop position µa Input leakage current ILI µa Off-state leakage current IOZ µa IOH =.ma (Type S), ma (Type M), High level output voltage VOH ma (Type ), VDD ma (Type ), V ma (Type 3, ) VDD = Min. IOL =.ma (Type S), ma (Type M), ma (Type ), Low level output voltage VOL ma (Type ),. V ma (Type 3), ma (Type ) VDD = Min. High level input voltage VIH CMOS level, VDD = Max. 3. V Low level input voltage VIL CMOS level, VDD = Min.. V High level input voltage VT+ CMOS Schmitt, VDD =.V. V Low level input voltage VT- CMOS Schmitt, VDD =.V. V Hysterisis voltage VH CMOS Schmitt, VDD =.V.3 V High level input voltage VIH TTL level, VDD = Max.. V Low level input voltage VIL TTL level, VDD = Min.. V High level input voltage VT+ TTL Schmitt, VDD =.V. V Low level input voltage VT- TTL Schmitt, VDD =.V. V Hysterisis voltage VH TTL Schmitt, VDD =.V. V High level input voltage VIH3 level, VDD = Max.. V Low level input voltage VIL3 level, VDD = Min.. V High level output current IOH3 Available for, VOH =.V, ma VDD = Min., VOH = 3.V, VDD = Max. ma Low level output currrent IOL3 Available for, VOL =.V, 9 ma VDD = Min., VOL =.7V, VDD = Max. ma Pull-up resistor RPU VI = V Type Type KΩ Pull-down resistor RPD VI = VDD Type Type KΩ High level hold current IBHH Available for bus holding, VIN = 3.V (CMOS system) VDD = Max. 9 µa Low level hold current IBHL Available for bus holding, VIN =.V (CMOS system) VDD = Max. µa High level hold current IBHH Available for bus holding, VIN =.V (TTL system) VDD = Max. µa Low level hold current IBHL Available for bus holding, VIN =.V (TTL system) VDD = Max. µa High level inversion current IBHHO Available for bus holding, VDD = Min. 9 ma Low level inversion current IBHLO Available for bus holding, VDD = Min. 3 ma Input pin capacitance CI f = MHz, VDD = V pf Output pin capacitance CO f = MHz, VDD = V pf I/O pin capacitance CIO f = MHz, VDD = V pf * Stand by current is a representative value of eresy series 3

4 SLA3 Series ELECTRICAL CHARACTERISTICS (VDD=3V) (VDD = 3V±.3V, VSS = V, Ta = to C) Item Symbol Conditions Min. Typ. Max. Unit Stand-by current* IDDS Stop position µa Input leakage current ILI µa Off-state leakage current IOZ µa IOH =.ma (Type S),.mA (Type M), High level output voltage VOH.mA (Type ), VDD 3.mA (Type ),.3 V ma (Type 3, ) VDD = Min. IOL =.ma (Type S),.mA (Type M),.mA (Type ), Low level output voltage VOL 3.mA (Type ),.3 V ma (Type 3), ma (Type ) VDD = Min. High level input voltage VIH CMOS level, VDD = Max.. V Low level input voltage VIL CMOS level, VDD = Min.. V High level input voltage VT+ CMOS Schmitt, VDD = 3.V.3 V Low level input voltage VT- CMOS Schmitt, VDD = 3.V. V Hysterisis voltage VH CMOS Schmitt, VDD = 3.V. V High level input voltage VIH3 level, VDD = Max.. V Low level input voltage VIL3 level, VDD = Min.. V High level output currrent IOH3 Available for, VOH =.V, 33 ma VDD = Min., VOH =.3V, VDD = Max. ma Low level output current IOL3 Available for, VOL =.V, ma VDD = Min., VOL =.V, VDD = Max. ma Pull-up resistor RPU VI = V Type Type KΩ Pull-down resistor RPD VO = VDD Type Type KΩ High level hold current IBHH Available for bus holding, VIN =.V VDD = Max. 3 µa Low level hold current IBHL Available for bus holding, VIN =.V VDD = Max. 7 µa High level inversion current IBHHO Available for bus holding, VDD = Min. 9 ma Low level inversion current IBHLO Available for bus holding, VDD = Min. 7 ma Input pin capacitance CI f = MHz, VDD = V pf Output pin capacitance CO f = MHz, VDD = V pf I/O pin capacitance CIO f = MHz, VDD = V pf * Stand by current is a representative value of eresy series

5 SLA3 Series ELECTRICAL CHARACTERISTICS (VDD=3.3V) (±.3V, VSS = V, Ta = to C) Item Symbol Condition Min. Typ. Max. Unit Stand-by current* IDDS Stop position 9 µa Input leakage current ILI µa Off-state leakage current IOZ µa IOH =.ma (Type S),.mA (Type M), High level output voltage VOH ma (Type ), VDD ma (Type ),.3 V ma (Type 3, ) VDD = Min. IOL =.ma (Type S),.mA (Type M), ma (Type ), Low level output voltage VOL ma (Type ),.3 V ma (Type 3), ma (Type ) VDD = Min. High level input voltage VIH CMOS level, VDD = Max.. V Low level input voltage VIL CMOS level, VDD = Min.. V High level input voltage VT+ CMOS Schmitt,. V Low level input voltage VT- CMOS Schmitt,. V Hysterisis voltage VH CMOS Schmitt,. V High level input voltage VIH3 level, VDD = Max..7 V Low level input voltage VIL3 level, VDD = Min..9 V High level output current IOH3 Available for, VOH =.9V, 3 ma VDD = Min., VOH =.V, VDD = Max. ma Low level input current IOL3 Available for, VOL =.V, ma VDD = Min., VOL =.V, VDD = Max. 37 ma Pull-up resistor RPU VI = V Type 9 Type 9 3 KΩ Pull-down resistor RPD VI = VDD Type 9 Type 3 KΩ High level hold current IBHH Available for bus holding, VIN =.V VDD = Max. µa Low level hold current IBHL Available for bus holding, VIN =.V VDD = Max. 3 µa High level inversion current IBHHO Available for bus holding, VDD = Min. 3 µa Low level inversion current IBHLO Available for bus holding, VDD = Min. µa Input pin capacitance CI f = MHz, VDD = V pf Output pin capacitance CO f = MHz, VDD = V pf I/O pin capacitance CIO f = MHz, VDD = V pf * Stand by current is a representative value of eresy series

6 SLA3 Series ELECTRICAL CHARACTERISTICS (Stand-by Current) Single power supply (Ta= to C) Dual power supply (Ta= to C) V±% 3.3V±.3V 3.V±.3V Master IDDS Max. IDDS Max. IDDS Max. Unit SLA3/3T SLA33/33T 3 µa SLA3/3T SLA3/3T SLA37/37T 9 µa SLA39/3T SLA3/3T SLA3/3T 3 µa V±% 3.3V±.3V V±% 3.V±.3V Master HIDDS Max. LIDDS Max. HIDDS Max. LIDDS Max. Unit SLA3/3T SLA33/33T µa SLA3/3T SLA3/3T SLA37/37T 9 µa SLA39/3T SLA3/3T SLA3/3T 3 µa HIDDS: Stand-by current between HVDD and VSS. LIDDS: Stand-by current between LVDD and VSS. In case of dual power supply, total stand-by current is the sum of HIDDS and LIDDS. CHARACTERISTICS CURVES (VDD=V) Output Current Characteristics (.V±%) Type number Output Current IOH(mA) IOL(mA) TypeS.. TypeM Type Type Type3 Type Conforms to standard. Letters S, M and to of "Type*" represent the numbers used for the output cell name (in format of "XX X"). Measurement Circuit V DD I OH I OL VI IBC A V, OH V OL V SS

7 I I I I I SLA3 Series Low level output current High level output current Type S Type S OL (µa) VDD =.V VDD =.V OH(µA) VDD =.V VDD =.V VDD =.V VDD =.V VOH VDD(V) Type M Type M OL (ma) IOH(mA) VDD =.V VDD =.V VDD =.V VDD =.V VDD =.V VDD =.V VOH VDD(V) OL (ma) VDD =.V VDD =.V VDD =.V IOH(mA) VDD =.V VDD =.V VDD =.V VOH VDD(V) Type to TYPE to VDD =.V TYPE TYPE TYPE OL (ma) IOH (ma) TYPE3, TYPE TYPE3 TYPE TYPE VDD =.V Output voltage VOH Supply voltage VDD(V) 7

8 t t t t t SLA3 Series tpd, tr, tf-cl tplh vs. CL tphl vs. CL VDD =.V Vth =.V VDD =.V Vth =.V PLH (ns) 3 PDVAT + UOS PHL(ns) 3 PDVAT+UOS PDVAT + UOM PDVAT+UOM Type to Type to PLH (ns) VDD =.V Vth =.V PDVAT+UO PDVAT+UO PDVAAT+UO3 PDVAAT+UO t PHL(ns) VDD =.V Vth =.V PDVAT+UO PDVAT+UO PDVAAT+UO3 PDVAAT+UO 9 7 VDD =.V Vth =.V 9 7 VDD =.V Vth =.V PLH (ns) 3 PDVAAT+UOPA PHL(ns) 3 PDVAAT+UOPA

9 r f r f t r t f SLA3 Series tpd, tr, tf-cl tr vs. CL tf vs. CL... VDD =.V. VDD =.V ( -9 )(ns) UOS ( -9 )(ns) UOS UOM.. UOM 3 Type to 3 Type to VDD =.V VDD =.V t ( -9 )(ns) UO UO UO3, UO t ( -9 )(ns) UO UO UO3 UO VDD =.V VDD =.V t ( -9 )(ns) UOPA t ( -9 )(ns) UOPA 9

10 t t SLA3 Series Delay Time Propagation delay(tpd) vs. supply voltage(vdd) Propagation delay(tpd) vs. ambient temperature(ta)..3.. VDD =.V T pd =... VDD =.V T pd =. pd (ratio). pd (ratio) VDD (V) Ta ( C) CHARACTERISTICS CURVES (VDD=3.3V) Output Current (3.3V±.3V) Type number Output Current IOH(mA) IOL(mA) TypeS.. TypeM.. Type Type Type3 Type Conforms to standard. Letters S, M and to of "Type*" represent the numbers used for the output cell name (in format of "XX X").

11 I I I I SLA3 Series Low level output current High level output current 3 Type S Type S OL (µa) VDD = 3.V IOH(µA) VDD = 3.V Output voltage VOH - Supply voltage VDD(V) Type M Type M OL (ma) VDD = 3.V IOH(mA) VDD = 3.V VOH VDD(V) OL (ma) VDD = 3.V IOH(mA) VDD = 3.V VOH VDD(V) Type to Type to TYPE TYPE OL (ma) IOH(mA) TYPE TYPE3 TYPE TYPE3, TYPE TYPE VOH VDD(V)

12 SLA3 Series tpd, tr, tf-cl tplh vs. CL tphl vs. CL 9 9 t PLH (ns) 7 3 Vth =.V PDVAT+UOS t PHL (ns) 7 3 Vth =.V PDVAT+UOS PDVAT+UOM PDVAT+UOM 3 Type to 3 Type to (ns) t PLH Vth =.V PDVAT+UO PDVAT+UO PDVAAT+UO3 PDVAAT+UO (ns) t PHL Vth =.V PDVAT+UO PDVAT+UO PDVAAT+UO3 PDVAAT+UO 9 7 Vth =.V 9 7 Vth =.V (ns) t PLH PDVAAT+UOPB (ns) t PHL PDVAAT+UOPB 3 3

13 r f r f r f SLA3 Series tpd, tr, tf-cl tr vs. CL tf vs. CL t ( -9 )(ns)... UOS t ( -9 )(ns)... UOS... UOM. UOM Type to Type to 3 3 t ( -9 )(ns) UO UO t ( -9 )(ns) UO UO UO3 UO3, UO UO t ( -9 )(ns) UOPB t ( -9 )(ns) UOPB 3

14 SLA3 Series NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All product names mentioned herein are trademarks and/or registered trademarks of their respective companies. Seiko Epson Corporation 99 All rights reserved. ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group -, Hino, Hino-shi, Tokyo 9-, JAPAN Phone: +-()-7- Fax: +-()-7- ED International Marketing Department I (Europe & U.S.A.) -, Hino, Hino-shi, Tokyo 9-, JAPAN Phone: +-()-7- Fax: +-()-7- ED International Marketing Department II (Asia) -, Hino, Hino-shi, Tokyo 9-, JAPAN Phone: +-()-7- Fax: +-()-7- Electric Device Information of EPSON WWW server