11 EMBEDDED MEMORY OVERVIEW

Transcription

1 11 EMBEDDED MEMORY OVERVIEW Embedded memy is any nonstandalone memy. It is an integrated onchip memy that suppts the logic ce to accomplish intended functions. Highperfmance embedded memy is a key component in VLSI because of its highspeed and wide buswidth capability, which eliminates interchip communication. During the past several years, a lot of development has taken place in the embedded memy market. Most recently, many new products were introduced with embedded memy, with a particularly high interest in embedded DRAM. Figure 111 shows the increasing perfmance gap between microprocesss and DRAMs. As this gap has widened, chip designers placed greater emphasis on the development of embedded memy devices. Their task was made easier by at least two facts. First, the complexity of process technology made it possible to incpate logic and memy on the same chip. Secondly, larger die size allows the incpation of both logic and memy on the same chip. Several advantages of using embedded memies are provided below. They include reduced number of chips, reduced pin count, multipt memies, less board space requirements, faster response with memy embedded onchip, dedicated architecture, memy capacity specific f an application, reduced power consumption, and greater cost effectiveness at the system level. The main disadvantages of embedded memies are that they are generally larger in size and are me complex to design and manufacture. Additionally, a tradeoff must often be found between design and technology since the optimized technology f a memy cell is not the same as that f embedded logic devices. Furtherme, processing becomes even me complex when the designer integrates different types of memy on the same chip. Figure 112 presents a DSP from Texas Instruments that includes embedded memies. Note that the memy ption consumes about half the total area of the chip. RAM, ROM, and logic on one chip makes f a challenging design and f challenging manufacturing. INTEGRATED CIRCUIT ENGINEERING CORPORATION 111

2 1,000 Frequency (MHz) MPU DRAM Growing Perfmance Gap Between MPU and DRAM Year Source: Kyushu University/ICE, "Memy 1997" Figure 111. MPU Versus DRAM Perfmances Figure 113 shows the key differences between embedded and standalone flash memies. On a standard memy device, cell size is the most critical issue. However, if the memy area is not a significant part of the full chip area, cell size is not a critical fact f a chip with embedded memy. F this reason, chip designers will often use a conservative cell design f embedded memies. EPROM, flash, DRAM may have me than one transist per cell. will often use the CMOS sixtransist (6T) cell design instead of the fourtransist (4T) memy design, along with some additional transists. EMBEDDED DRAM Embedded DRAMs are in the introduction phase of the product lifecycle. Due to the complexity of DRAM process technology, suppliers did not quickly develop embedded DRAMs. Embedded DRAM capacits that ste data require several processing steps not needed when making logic devices. The threshold voltage of DRAM transists must be high enough to ensure that they will not create memy cell capacit leakage. This constraint on low subthreshold current may cause some speed penalty on the logic ption of the device. DRAM processes are a central issue in an embedded DRAM device using a process developed f logic chips. 112 INTEGRATED CIRCUIT ENGINEERING CORPORATION

3 Source: TI/ICE, Memy Figure 112. TI s 1V DSP f Wireless Communications Typical Array Size (Bits) Typical Percent of Chip Area Cell Size Very Critical Cell Type Dual GateOxide Multiple Modules Redundancy Repairing Embedded 2K 2M 5% 40% No NOR Likely Rare StandAlone 1M 16M 100% NOR/NAND/AND Not Likely No Source: Motola/ICE, "Memy 1997" Figure 113. Key Differences Between Embedded and StandAlone Flash Memies In 1996 and 1997, numerous announcements were made regarding embedded DRAMs, revealing the great interest in this type of device. Until recently, DRAMs were the leastused embedded memy cell due to process complexity. INTEGRATED CIRCUIT ENGINEERING CORPORATION 113

4 Embedded DRAMs will become a me widespread solution to designer needs as onchip memy increases and the use of systemonachip rises. One reason f the interest in embedded DRAM is speed. As illustrated in Figure 114, embedded DRAM offers a large increase in memy bandwidth perfmance compared to several other currently used alternatives. Most of the current embedded DRAM developments are f graphics and multimedia applications. Memy Type Bandwidth Standard (256K x 16) HighSpeed (256K x 16) 2MB x 8 RDRAM (Rambus DRAM) SDRAM (Synchronous DRAM) Embedded DRAM (32K x 256) 240MB/sec. 400MB/sec. 500MB/sec. 640MB/sec. 2,560MB/sec. Source: Silicon Magic Cp/ICE, "Memy 1997" 20811A Figure 114. Memy Bandwidth Comparisons Several companies are developing embedded DRAMs. Figure 115 shows a sampling of DRAM/Logic devices that have recently been introduced. Silicon Magic is a 1994 fabless startup that develops embedded DRAMs f systems requiring very high memy bandwidth. They offer a chip that combines graphics, audio, and video functions with DRAM. At the 1996 ISSCC conference, Mitsubishi presented a 32bit Multimedia RISC microprocess with 16Mbits of embedded DRAM. This device was manufactured using a 0.45µm, doublemetal technology process. It also included 16Kbits of cache. Figure 116 shows a description of this product. Toshiba announced two ASIC families with embedded DRAM. One is based on the company s onetransist DRAM trench capacit cell process technology while the second family is based on its threetransist cell logic process. DRAM Memy Cell The memy cell of standard DRAM memy chips consists of one transist and one capacit. In the new DRAM generations, the capacit is either a trench stack capacit design. 114 INTEGRATED CIRCUIT ENGINEERING CORPORATION

5 Company Product Comments NeoMagic Silicon Magic Mitsubishi NEC Hitachi SGSThomson MagicGraph MaxH M32R/D PIPRAM "Media Chip" Omega Graphics controller chip f notebook computers that has 1M of embedded DRAM. Available now. IC that couples 1.25M of DRAM with VGA graphics acceleration, audio, and MPEG1 decompression fuctions. Available now. 32bit RISC process (54MIPS at 66MHz) and 16M DRAM. Device is built using 0.45µm, twolayer metal technology. Die size: 153.7mm2. Available now. Parallelimage processing (PIP) RAM f realtime image processing applications. PIPRAM integrates 16M DRAM and 128 8bit processs. In development stage. Prototype optimized f 3D graphics. The device integrates four 2M DRAM macros and four pixel processs. The chip integrates DRAM, ST20 microprocess ce, an MPEG Audio and video recder, and cache memy. Source: ICE, "Memy 1997" 21211A Figure 115. Companies Exple DRAM/Logic on Same Chip CPU ce VAX MIPS Memy Peripheral logic External bus Clock Supply voltage Power Die size CPU size Process technology Package 32b RISC architecture 52.4 MIPS at 66.6 MHz (Dhrystone V2.1) 16Mbit DRAM with 16KBit cache () 32b x 16b DSPlike multiply accumulat memy controller, etc. 24b address, 16b data 66.6MHz (internal) / 16.67MHz (external) 3.3V 700mW(typ.) / 2mW (standby) 153.7mm 2 5.7mm µm CMOS, 2metal layers 80pin plastic QFP Source: ISSCC 1996/ICE, "Memy 1997" Figure 116. Mitsubishi Multimedia 32bit RISC Chip Overview The memy cell of embedded DRAMs using a standard logic process will often be a threetransist design with separate read and write access. An additional capacit is sometimes added to ensure a minimum value of 30pF. The larger the capacit, the less sensitive to noise alpha particle induced soft err the memy cell will be. Figure 117 shows the different types of DRAM cells. The advantages of a threetransist cell over a onetransist cell are compatibility with standard digital CMOS technology, higher access speed, dualpt (separate read and write access pts) and nondestructive readout. INTEGRATED CIRCUIT ENGINEERING CORPORATION 115

6 1T 3T 3T with added capacit Source: ICE, "Memy 1997" Figure 117. DRAM Memy Cells An illustration of this embedded DRAM design diversity was made by Toshiba. The company proposed both a onetransist cell and a threetransist cell f ASIC applications. The onetransist cell is based on a 0.25µm DRAM trench capacit process and is proposed f applications needing 1Mbit to 32Mbit DRAM density. The threetransist cell is based on a 0.3µm logic process and is proposed f applications needing no me than 1Mbit DRAM density. EMBEDDED Embedded is widely used. The embedded market is even larger than the standalone market! Whether faster speed, greater density, lower power consumption, several vends have emerged to supply improved embedded devices. as Cache Memy Most CPUs, DSPs, and MCUs have a small quantity of cache memy on chip. This onchip memy is called primary cache levelone (L1) cache. L1 cache is backed up by a larger offchip secondary leveltwo (L2) cache. Figure 118 shows the quantity of L1 cache used in AMD and Intel MPUs. in ASIC cells are also implemented in ASICs. They may be used f the programmability implemented as a block. Figure 119 shows a block diagram of Actel s 3200DX FPGA that incpates blocks of high speed (5ns) dualpt. 116 INTEGRATED CIRCUIT ENGINEERING CORPORATION

7 AMDK5 AMDK6 Intel P55C Pentium Pro L1 Cache 16Kbytes instr 8Kbytes data 32Kbytes instr 32Kbytes data 16Kbytes instr 16Kbytes data 8Kbytes instr 8Kbytes data MMX? No No* Outof Order Execution? No Max Clock 100MHz 180MHz 200MHz 200MHz Voltage 3.3V ~2.9V 2.5V 3.3V Transists 4.3 million 8.8 million 4.5 million 5.5 million IC Process 0.35µm 0.35µm 0.28µm 0.35µm Metal Layers 3M 5M 4M 4M Die Size 181mm 2 180mm 2 140mm 2 196mm 2 Production Now 1H97 1H97 Now *Klamath, a singlechip version of the Pentium Pro, will feature MMX technology. Source: MDR/Vends/ICE, "Memy 1997" 21738A Figure 118. L1 Cache in AMD and Intel MPUs 6T Cell A sixtransist CMOS architecture will be often used to make the memy cell. This architecture provides better electrical characteristics (speed, power consumption, noise immunity) and is compatible with a logic process as only one polysilicon level is required. The cell size, however, is larger than a fourtransist cell. Figure 1110 shows cell dimensions of CPU products analyzed by ICE s labaty. All the cells presented on the list are sixtransist cells. Embedded s can also utilize me transists than the classical 6T cell. This helps improve the electrical perfmance of the embedded circuit. Also, multipt memy cells are also often used as embedded. Figures 1111 and 1112 show two embedded s using me than the classical 6T structure. Figure 1111 presents a cell implemented in an ASIC from IBM that uses nine transists f a cell size of 120 square microns (0.6µm channel length). Figure 1112 presents a cell implemented in a CPLD from Philips that also utilizes a ninetransist cell. INTEGRATED CIRCUIT ENGINEERING CORPORATION 117

8 JTAG JTAG Logic Modules Logic Modules Logic Modules JTAG Fast Decode Module JTAG Source: Actel/ICE, "Memy 1997" Figure 119. Actel s 3200DX FPGA Architecture Product Gate Length (µm) Cell Type Cell Size (µm 2 ) Sun UltraSparc 143MHz T 63.7 Intel Pentium Pro 200MHz 0.3 6T 49.0 Cyrix/IBM 6x T 44.0 DEC Alpha 0.4 6T 43.0 Motola PowerPC 604e T 36.0 Source: ICE, "Memy 1997" Figure L1 Cache Cell Dimensions 118 INTEGRATED CIRCUIT ENGINEERING CORPORATION

9 WORD 4P 2P 5N 6N 3N 1N 9N 7N 8N Source: ICE, Memy Figure Transist Cell (IBM) WORD φ 8 1 OUT 2 4 φ 7 6 Source: ICE, Memy Figure Transist Design Cell (Philips) 4T Cell There are at least two reasons that a company would consider using 4T cells f embedded memy. First, if the size of embedded memy is imptant, the use of a smaller memy cell is necessary. Secondly, if a company has experience in standalone 4T cell architecture, it may prefer to implement that architecture in its embedded application. This is the case of IDT. As illustrated in Figures 1113 and 1114, the same used f its 256Kbit is used in as embedded (L1 cache) on its 79R4600 RISC process. Product Cell Type Week Code Technology Cell Dimensions (µm) Cell Area (µm 2 ) 256K 4T µm 8.5 x RISC Process 4T µm 7 x Source: ICE, "Memy 1997" Figure Comparison of IDT s StandAlone and Embedded Cells INTEGRATED CIRCUIT ENGINEERING CORPORATION 119

10 GND 1 3 R1 2 R2 4 EMBEDDED WORD LINE Q4 Q1 R1 R2 Q2 Q3 256K Source: ICE, Memy Figure Top Views of IDTÕs Cells EMBEDDED ROM Like embedded s, there are probably me embedded ROM developments than standalone ROM memy shipments. ROM cells do not need a specific technology. Various programming methods may be used such as metal contact, channel implant, and field oxide. The selection of programming method involves a tradeoff between cost, cell size, and cycle time. If random high speed is required, the ROM will use a NOR architecture. If this speed requirement is not needed, the NAND architecture may be used to save space INTEGRATED CIRCUIT ENGINEERING CORPORATION

11 EMBEDDED EPROM Figure 1115 shows a twotransist EPROM cell developed by Cypress and Altera f programmable logic device (PLD) implementation. The choice of using two transists was done to separately optimize read and write floating gate transists. This approach allows a better read current/area ratio compared to standard onetransist EPROM twotransist EEPROM cells. Control Gate Read Source Read Drain Program Drain Source: Cypress/Altera/ICE, "Memy 1997" Figure Schematic of High Speed 2T EPROM Cell With Separate Read and Write Transists OneTime Programmable (OTP) Memy As product design cycles get shter, it is me imptant f MCU suppliers to offer onetime programmable (OTP) memy as an option on their MCU chips. Manufacturers must be flexible enough to rapidly adapt to changing market opptunities. One problem with ROM is that programming, setup, and engineering changes are economical only when system manufacturers purchase large quantities of identically programmed MCUs. Furtherme, if system manufacturers make a software change, the lead time f receiving MCUs with the new program in ROM may be many months. OTP devices can come programmed unprogrammed from the semiconduct manufacturer. A single MCU model can be used in a variety of products by varying the program, the system can be customized to a customer s specific needs. This flexibility reduces the variety of MCUs that the systems manufacturer must stock, which in turn reduces inventy. INTEGRATED CIRCUIT ENGINEERING CORPORATION 1111

12 EMBEDDED EEPROM The me common embedded EEPROM devices are made of one polysilicon layer as illustrated by Figures 1116 and Both cells are implemented on programmable logic devices. Bit Wd A 1 B 3 2 Source: ICE, Memy Figure PZ5032 CPLD EEPROM From Philips The main interest of these designs is to use only one level of polysilicon and thus be compatible with a standard CMOS process. They will, however, have an additional step to create the thin oxide of the floating gate needed f programming the cell. EMBEDDED FLASH MEMORY Another nonvolatile memy option to use is embedded flash memy. As standard flash memies take EPROMs and EEPROMs market shares, flash memies will also replace these types of cells in the embedded applications. Figure 1118 shows a comparison between the different types of nonvolatile memies f embedded applications INTEGRATED CIRCUIT ENGINEERING CORPORATION

13 TUNNEL OXIDE DEVICE ENABLE 2 C WORD 1 GND WORD 1 2 Source: ICE, Memy Figure LatticeÕs Embedded EEPROM ROM EPROM Single Gate Flash Split Gate Flash EEPROM Density Electrically Prog. Electrically Erase. Byte Erasable Program Disturb Over Erase/Program Process Complexity Manufacturability Cost Wst Best Source: Motola/ICE, "Memy 1997" Figure Embedded NonVolatile Memy Comparison INTEGRATED CIRCUIT ENGINEERING CORPORATION 1113

14 Reprogrammability and incircuit programming capability provide a highly flexible solution to rapidly changing market demands. To meet these needs, several vends have embedded flash memy onto their microcontroller other logic devices. Siemens expects flash to be widely used in microcontroller applications, with as much as 80 percent of all embedded controllers using it in five years. Embedded flash memies may be used in a wide range of applications. Figure 1119 shows which applications may need flash devices. By Function By Device By EndProduct By Usage Program Data Firmware Boot Code Boot Vect MCU DSP PLD/FPGA Automotive Consumer Communications Office Automation Industrial System Development Prototyping Pilot Production Full Production Parameters LookUp Table Shadow Bits/ Array Configuration Register Manufacturing Code Source: Motola/ICE, "Memy 1997" Figure Embedded Flash Memy Applications Like other embedded memy cells, flash memy design will be a tradeoff between size, perfmance, and process compatibility. Figure 1120 shows the advantages and disadvantages of different types of flash memy cell designs. Smartcard Products Smartcards are a new and fast growing market using embedded memy. Smartcards may incpate MCU, different types of memy, advanced security features, and cryptographic processing. Figure 1121 shows the chip ganization of an advanced smartcard INTEGRATED CIRCUIT ENGINEERING CORPORATION

15 ,,,,, N N Single Gate (1T Cell) N N Split Gate (1.5T Cell), N,, N N Double Gate (2T Cell) Advantages High Density No OverErase Full Isolation Disadvantages Over Erase/Program Program Disturb Larger Cell Area Program Disturb Very Large Cell Area Source: Motola/ICE, "Memy 1997" Figure Advantages and Disadvantages of Flash Memy Cell Gate Structures 8bit MCU RAM System ROM User ROM A MAP Memy Access Matrix User ROM B Security Random Number Gen. EEPROM A Serial I/O EEPROM B Source: SGSThomson/ICE, "Memy 1997" Figure Smartcard Chip Organization INTEGRATED CIRCUIT ENGINEERING CORPORATION 1115