1 System-on-Chip EE141 Test Architectures Ch FPGA Testing - P. 1

Transcription

1 Chapter 2 Field Programmable Gate Array Testing System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P.

2 What is this chapter about? Field Programmable Gate Arrays (FPGAs) Have become a dominant digital implementation media Reconfigurable to implement any digital logic function Focus on Testing challenges due to programmability and complexity Overview of testing approaches Test and diagnosis of various resources New frontiers in FPGA testing 2 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 2

3 FPGA Testing Overview of FPGAs Architecture, Configuration, & Testing Problem Testing Approaches BIST of Programmable Resources Logic Resources Logic Blocks, I/O Cells, & Specialized Cores Diagnosis Routing Resources Embedded Processor Based Testing Concluding Remarks 3 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 3

4 Field Programmable Gate Arrays Configuration Memory Programmable Logic Blocks (PLBs) Programmable Input/Output Cells Programmable Interconnect Typical Complexity = 5 million billion transistors 4 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 4

5 Basic FPGA Operation Writing configuration memory (configuration) defines system function Input/Output Cells Logic in PLBs Connections between PLBs & I/O cells Changing configuration memory data (reconfiguration) changes system function Can change at anytime Even while system function is in operation Dynamic partial reconfiguration 5 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 5

6 FPGA Architectures Early FPGAs NxN array of unit cells Unit cell = CLB + routing Special routing along center axes I/O cells around perimeter Next Generation FPGAs MxN array of unit cells Added small block RAMs at edges More Recent FPGAs Added larger block RAMs in array Added multipliers Added Processor Cores (PC) Latest FPGAs Added DSP cores w/multipliers I/O cells along columns for BGA System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 6 PC PC PC PC 6

7 Combinational Logic Functions Gates are combined to create complex circuits A S Z Multiplexer example If S =, Z = A If S =, Z = B Common digital circuit Heavily used in FPGAs Select input (S) controlled by configuration memory bit B Truth table S A B Z Logic symbol A B S Z 7 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 7

8 Look-up Tables Using multiplexer example Configuration memory holds truth table Input signals connect to select inputs of multiplexers to select output value of truth table for any given input value B A S Z Multiplexer A B S Truth table S A B Z 8 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 8 Z

9 Basic PLB Structure Look-up table (LUT) for combinational logic Store truth table in LUT (typically 3 to 6 inputs) Some LUTs can also act as RAM/shift register Flip-flops for sequential logic Programmable clock enable, set/reset Special logic Large logic functions with Shannon expansion Fast carry for adders and counters Input[:4] Control 4 LUT/ RAM clock, enable, set/reset 3 carry in Carry & Control Logic carry out Flip-flop/ Latch Output Q output System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 9 9

10 Look-up Table Based RAMs Normal LUT mode performs read operations Data In en en2 In en3 with write enable In In2 en4 Address decoder Write Address generates load signals to latches for write operations Small RAMs but can be combined for larger RAMs Write Enable System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. Address s Decoder en en5 en6 en7 In In In2 Read Address Z

11 Input/Output Cells Bi-directional buffers Programmable for input or output signals Tri-state control for bi-directional operation Flip-flops/latches for improved timing Set-up and hold times Clock-to-output delay Pull-up/down resistors Routing resources to/from internal routing resources Connections to core of array Tri-state Control Output Data Input Data Bidirectional Buffer Programmable I/O voltage & current levels System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. Pad

12 Interconnect Network Wire segments of varying length xn = N PLBs in length Typical values of N =, 2, 4, 6, 8 Long lines xh = half the array in length xl = full array in length config bit Programmable Interconnect Points (PIPs) Wire A Wire B Transmission gate connects to 2 wire segments Controlled by configuration memory bit Four basic types of PIPs 2 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 2

13 Programmable Interconnect Points Break-point PIP Connect or isolate 2 wire segments Cross-point PIP 2 nets straight through net turns corner and/or fans out Compound cross-point PIP Collection of 6 break-point PIPs Can route 2 isolated signal nets Multiplexer PIP Directional and buffered Main routing resource in recent FPGAs Select -of-n inputs for output Decoded MUX PIP N configuration bits select from 2 N inputs Non-decoded MUX PIP configuration bit per input System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 3 3

14 Recent Architectural Trends Addition of specialized cores: Memories Single and dual-port RAMs FIFO (first-in first-out) ECC (error correcting codes) Digital signal processors (DSPs) Multipliers Accumulators Arithmetic/logic units (ALUs) Embedded processors Hard core (dedicated processors) With dedicated program/data memories Otherwise, programmable RAMs in FPGA used for program/data memories Soft core (synthesized from a HDL) = PLBs = routing resources = special cores = I/O cells System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 4 4

15 FPGA Resources Types and sizes of resources vary with FPGA family Example: LUTs vary from 3-input to 6-input 4-input LUTs are most common Typical ranges for some commercially available FPGAs Logic Routing Specialized Cores Other FPGA Resource Small FPGA Large FPGA PLBs per FPGA ,92 LUTs and flip-flops per PLB 8 Wire segments per PLB PIPs per PLB 39 3,462 Bits per memory core 28 36,864 Memory cores per FPGA DSP cores 52 Input/output cells 62,2 Configuration memory bits 42,4 79,74,832 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 5 5

16 Configuration Interfaces Master mode (Serial or Parallel options) FPGA retrieves configuration from ROM at power-up Slave (Serial or Parallel options) FPGA configured by external source (i.e., a µp) Used for dynamic partial reconfiguration Boundary Scan Interface 4-wire IEEE standard serial interface for testing Write and read access to configuration memory Interfaces to FPGA core internal routing network Not available in all FPGAs clock PROM with Config Data data out CCLK FPGA in Master Mode Din Dout System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 6 CCLK FPGA in Slave Mode Din Dout CCLK FPGA in Slave Mode Din Dout 6

17 FPGA Configuration Memory PLB addressable Good for partial reconfiguration X-Y coordinates of PLB location to be written Z coordinate identifies which resources will be configured Frame addressable Vertical or horizontal frame Vertical frames most common Access to all PLBs in frame Only portion of logic and routing resources accessible in a given frame Many frames required to configure PLBs & routing System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 7 7

18 Configuration Techniques Full configuration & readback Simple configuration interface Automatic internal calculation of frame address Long download time for large FPGAs Partial reconfiguration & readback Only change portions of configuration memory with respect to reference design Reduces download time for reconfiguration Requires a more complicated configuration interface Command Register (CMR) Frame Length Register (FLR) Frame Address Register (FAR) Frame Data Register (FDR) System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 8 8

19 Configuration Techniques Compressed configuration Requires multiple frame write capability Write identical frames of config data to multiple frame addresses Extension of partial reconfiguration interface capabilities Frame address is much smaller than frame of configuration data Reduces download time for initial configuration depending on Regularity of system function design % utilization of array Unused portions written with default configuration data System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 9 9

20 FPGA Testing Taxonomy Test Approach Attribute Test pattern application and output response analysis Classification Internal (BIST) External System-level testing Off-line On-line System application Independent Dependent Target programmable resources Logic Routing PLBs I/O cells Cores Local Global On-line test while system is operational Off-line test while system is out-of-service Application-dependent testing tests only those FPGA resources used by intended system function Application-independent testing tests all FPGA resources 2 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 2

21 FPGA Test Configurations More test configurations required for routing resources than for logic resources Data below from publications on actual test configuration implementations in commercial FPGAs FPGA Number of Test Configurations Vendor Series PLBs Routing Cores Reference Lattice ORCA2C 9 27 [Abramovici 2] ORCA2CA 4 4 [Stroud 22b] Atmel AT4K/AT94K [Sunwoo 25] Cypress Delta39K 2 49 [Stroud 2] Xilinx 4E/Spartan XL/XLA 2 26 [Stroud 23] Virtex/Spartan-II [Dhingra 25] Virtex-4 5? 5 [Milton 26] 2 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 2

22 A Simple PLB Architecture Two 3-input LUTs Can implement any 4-input combinational logic function Can implement full adder flip-flop Carry in LUT C Sum in LUT S Programmable: Active levels Clock edge Set/reset 22 configuration memory bits 8 per LUT D2- D3 C7-C and S7-S 6 control bits CB5-CB 3 CB 5 Clock Enable Set/Reset Clock LUT C 8x LUT S 8x CB D2- LUT C 7 Smux C 6 C 5 C 4 C 3 C 2 C C out Cout SOmux Sout System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 22 CB CB 2 CEmux CB 3 SRmux CB FF 22 CB 4 = Configuration Memory Bit

23 Test Configurations for Simple PLB All configuration memory bits must be tested for both logic values ( and ) assuming exhaustive input patterns Output effects for each logic value must be observed Exclusive-OR (XOR) and exclusive-nor (XNOR) functions are good for testing LUTs Put opposite functions in adjacent LUTs to produce opposite logic values at inputs to subsequent logic functions Fault coverage results below are based on collapsed single stuck-at gate-level fault model (74 faults total) Configuration Bits Configuration # Configuration #2 Configuration #3 LUT C (C7 - C) XNOR () XOR () XOR () LUT S (S7 - S) XOR () XNOR () XNOR () CB - CB5 Individual FC 49/74 = 85.6% 49/74 = 85.6% 8/74 = 62.% Cumulative FC 85.6% 97.7% % System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

24 BIST for FPGAs Basic idea: Program some logic resources to act as Goal: Test pattern generators (TPGs) Output response analyzers (ORAs) Resources under test Logic resources as blocks under test (BUTs) Routing resources as wires under test (WUTs) Minimize number of test configurations to minimize download time Download time dominates total test time 24 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 24

25 TPG and ORA Implementations TPG implementation depends on test algorithm May be implemented in different resources (see table below) Multiple TPGs prevent faulty TPG from escaping detection Lower bound on number of PLBs per TPG, T PLB = B IN N FF B IN = number of inputs to BUT N FF = number of FFs/PLB ORAs most efficiently implemented in PLBs Number of PLBs needed for ORAs, O PLB = (N BUT B OUT ) N FF B OUT = number of outputs from BUT N BUT = number of BUTs Resource Under Test TPGs ORAs PLBs PLBs or DSP cores PLBs LUT RAMs PLBs or DSP and RAM cores PLBs I/O cells PLBs or DSP and RAM cores PLBs Cores (memories, DSPs, etc.) PLBs PLBs Interconnect PLBs PLBs System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

26 TPG Algorithms Small logic functions (PLBs, IOBs) can be tested with pseudo-random test patterns LFSRs or counting patterns Large logic functions (RAMs, DSPs) require specialized test algorithms for high fault coverage Below are examples of typical RAM test algorithms Algorithm March Y March LR w/o BDS March LR with BDS March Test Sequence (w); (r, w,r); (r, w, r); (r) (w); (r, w); (r, w, r, r, w); (r, w); (r, w, r, r, w); (r) (w); (r, w); (r, w, r, r, w); (r, w); (r, w, r, r, w); (r, w, w, r); (r, w, r); (r) Notation: w = write (or all s), r = read (or all s) = address up, = address down, = address either way System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

27 Output Response Analyzers Comparison-based XOR with OR feedback from flip-flop Latches mismatches observed due to faults Results retrieval ORA with shift register Requires additional logic Configuration memory readback Read contents of ORA flip-flops Good with partial configuration memory readback capabilities BUT j output BUT k output BUT j output BUT k output BUT j output BUT k output BUT j output n BUT k output n shift data shift mode Pass/ Fail System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P Pass/ Fail Pass/ Fail

28 Logic Resource BIST Architectures Basic comparison Multiple TPGs drive alternating columns (rows) of blocks under test (BUTs) BUTs in center of array observed by 2 sets of ORAs and compared with 2 other BUTs BUTs along edges of array observed by only set of ORAs Some loss of diagnostic resolution Originally used to test PLBs Later used to test specialized cores Basic Comparison =TPG =ORA =BUT System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

29 Logic Resource BIST Architectures Circular Comparison Multiple TPGs drive alternating columns (rows) of blocks under test (BUTs) All BUTs observed by 2 sets of ORAs and compared with 2 other BUTs Good diagnostic resolution Originally used to test specialized cores Later used to test PLBs and I/O cells Circular Comparison =TPG =ORA =BUT 29 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 29

30 Logic Resource BIST Architectures Expected Results comparison Multiple TPGs One set of TPGs drive BUTs Other set of TPGs produce expected results for comparison with outputs of BUTs BUTs observed by set of ORAs and compared with expected results from TPGs Simple diagnosis since failing ORA position indicates faulty BUT Good when expected results can be algorithmically generated easily Example: RAM test algorithms Originally used to test RAM cores expected results Expected Results test patterns =TPG =ORA =BUT System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 3 3

31 Logic Resource Diagnostic Procedure. Record ORA results; = failure indication. 2. For every set of 2 or more consecutive ORAs with s, enter s for all BUTs observed by these ORAs; the BUTs are faultfree. 3. For every adjacent and followed by an empty space, enter to indicate BUT is faulty; continue while such entries exist. 4. If an ORA indicates a failure but both BUTs monitored by the ORA are fault-free, one of the following conditions exist: A. A fault in routing resources between one of the BUTs and the ORA, B. ORA is faulty, or C. There are more than 2 consecutive BUTs with equivalent faults (for circular comparison only); reorder circular comparison and repeat test and diagnostic procedure. 5. Remaining BUTs marked as unknown may be faulty; reorder circular comparison or rotate basic comparison architecture by 9, repeat test and diagnostic procedure. System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 3 3

32 Diagnostic Procedure Examples Note that B4 and B5 have equivalent faults in Example A Circular comparison provides better diagnostic resolution Also indicates when more than 2 consecutive BUTs with equivalent faults (Example C) Example A Example B Example C BIST Architecture Basic Circular Basic Circular Basic Circular Diagnostic Step B O2 B2 O23 B3 O34 B4 O45 B5? O56 B6?? O6 32 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 32

33 Testing Routing Resources Comparison-based BIST approach Developed for on-line FPGA BIST Testing restricted to routing resources for 2 rows or 2 columns of PLBs Small Self-Test AReas (STARs) Comparison-based ORA Later applied to off-line BIST Fill FPGA with STARs Tests run concurrently Diagnostic resolution to STAR Easier BIST development But more BIST configurations TPG WUTs ORA STAR FPGA 33 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 33 T O T O T O T O T O

34 Testing Routing Resources Original parity-based BIST approach Parity bit routed over fault-free resources What is fault-free until you ve tested it? Modified parity-based approach N-bit up-counter with even parity, and N-bit down-counter with odd parity Gives opposite logic values for Stuck-on PIPs & bridging faults Parity used as test pattern N+ wires under test Good for small PLBs like our simple PLB example Make STARs as small as possible Better diagnostic resolution Easier BIST development WUTs TPG WUTs parity bit ORA parity-check based-ora TPG System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 34 Par O R A C + 34 C

35 Testing Routing Resources Testing typically separated by routing resources Global - interconnects non-adjacent logic resources Local - interconnects adjacent logic resources and connects logic resources to global routing Additional test configurations swap positions of TPGs and ORAs to reverse direction of signal flow to test directional, buffered routing resources Multiplexer PIPs are a good example global routing =TPG =ORA local routing PLB feed-through local routing adjacent PLBs 35 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P. 35

36 Reducing Test Time Orient BIST architecture to configuration memory Align along rows/columns depending on FPGA structure Downloading BIST configurations Compressed configuration for initial download Partial reconfiguration for subsequent downloads Reduce number of frames written between configurations Keep routing constant between BIST configurations Optimize order of BIST configuration application Retrieving BIST results Partial configuration memory readback Eliminates ORA logic for scan chain Allows concurrent testing of more resources Minimize number of frames to be read Dynamic partial reconfiguration Read BIST results after a series of BIST configurations Slight loss in diagnostic resolution System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

37 Embedded Processor Based BIST New area of R&D in FPGA testing Basic idea: Embedded processor core Hard or soft core Configures FPGA for BIST Via internal configuration access port (ICAP) Alternative: download initial BIST configuration Executes BIST sequence May provide TPG functionality Retrieves BIST results May perform diagnostic procedure Reconfigures FPGA for subsequent BIST configurations Soft core requires two test sessions to test area occupied by processor core during first test session Processor core, TPGs and interface to ICAP circuitry Test session # = BUT = ORA Processor core, TPGs and interface to ICAP circuitry Test session #2 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

38 Embedded Processor BIST Overall reduction in total test time Algorithmic reconfiguration faster than external download to 25 times faster Results below from actual implementation in commercial FPGA Can be loaded into processor program memory for on-demand BIST and diagnosis of FPGA Good for fault-tolerant applications where system function is reconfigured around diagnosed fault(s) Resource Function External Processor Speed-up PLB BIST Routing BIST Download 7.68 sec. sec 76. Execution.6 sec.85 sec.2 Total time sec.86 sec 4.4 Download 2.64 sec. sec 82.4 Execution.26 sec.343 sec.75 Total time 2.9 sec.453 sec 44.3 Total Test Time sec.639 sec 43.5 System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P

39 Concluding Remarks Growing use of FPGAs in systems and SOCs FPGA testing is necessary but difficult due to Programmability Complex programmable interconnect network Constantly growing size and changing architectures Incorporation of new and different specialized cores Test & diagnosis allows fault-tolerant applications New FPGA capabilities assist in testing solutions Dynamic partial reconfiguration and readback Configuration/reconfiguration by embedded processor cores System-on-Chip EE4 Test Architectures Ch. 2 - FPGA Testing - P