The Interconnect Challenge

Transcription

1 The Interconnect Challenge Bob Havemann Novellus Systems, Inc. 16th Biennial University Government Industry Microelectronics Symposium June 26, 2006

2 Outline Interconnect Scaling Fabrication options Benefits of Cu/Low k Engineering C Reducing k effective Optimizing mechanical properties Engineering R Thinner barriers Optimizing Cu resistivity Summary P. 2

3 Interconnect Fabrication Options Positive Pattern Negative Pattern Metal Etch Dielectric Etch Dielectric Deposition Metal Deposition Metal Dielectric Planarization by CMP Metal CMP Dielectric Deposition Dielectric Photoresist Etch Stop (Dielectric) Subtractive Etch (Al) Damascene (W, Cu) Logic devices have fully transitioned from Al to Cu interconnect; transition from Al to Cu for Memory devices is in progress P. 3

4 Microprocessor Clock Frequency vs. Scaling Influence of Interconnect System on Performance Reference: P. Fisher & R. Nesbitt Clock Freq. (MHz) Cu-Low k Al-Low k Al-SiO 2 Cu-SiO Technology Min. Feature (nm) Logic Depth = 12 Gates P. 4

5 Interconnect Hierarchy 90 nm DSP Example Courtesy ot Texas Instruments Global/Semi-Global Interconnect Intermediate Interconnect Local Interconnect P. 5

6 A Typical Chip Scaling Scenario Global Wires Do Not Scale In Length A Chip A More Advanced Chip Macro Circuit Scaled Macro Circuit Local wire in a macro Global wire between macros P. 6

7 Interconnect Delay vs. Technology Node For ITRS Design Rules/Material Parameters 100 Reference: R. Ho & M. Horowitz Gate Delay (Fan out 4) Local (Scaled) Global wire signal delay increases with scaling Relative Delay 10 Global with Repeaters (Scaled Die Edge) Global w/o Repeaters (Scaled Die Edge) Repeater insertion reduces global delay 1 Local wire signal delay improves with scaling Process Technology Node (nm) P. 7

8 Benefits of Cu and Low k Interconnects Decreased RC Delay RC ~ ε o ερl 2 (h -2 + w -2 ) Crosstalk ~ C L-L / (C L-L + C L-G ) C L-L Lower Power Consumption P ~ CV 2 f C L-G Reduced Crosstalk Noise N ~ C L-L /C Total Line-to-line Capacitance = C L-L Line-to-ground Capacitance = C L-G P. 8

9 Cu Interconnect Evolution vs. Technology Node rf HCM PVD Barrier HCM PVD Seed rf HCM PVD Barrier HCM PVD Seed rf HCM PVD Barrier rf HCM PVD Seed iald Barrier iald Seed Cu Cu Cu Cu FSG (k~3.6) Low k (k 3) Porous Low k (k~2.5) Porous Low k (k<2.5) SiN SiC Low k Cap/Etch SiC Stop Cu Passivation Cap/Etch Stop Refractory Cap 130nm 90/65nm 45nm 32nm Engineering RC requires new materials and processes P. 9

10 New materials have both benefits & concerns Performance RC delay Crosstalk (~C ll /C T ) Power dissipation (~CV 2 f) Reliability Time Dependent Dielectric Breakdown (TDDB) Bias Thermal Stress (BTS) Via Stress Migration (VSM) Electromigration (EM) Packaging Mechanical Integrity Heat Dissipation P. 10

11 Engineering C Goal is reduction in effective dielectric constant (k) by minimizing: k of bulk dielectric material k of dielectric barrier Damage to low k during processing Moisture absorption in low k material Requires hermetic barrier Must also optimize mechanical properties Hardness, modulus, stress, cohesive strength, cracking limit Adhesion Pore size and connectivity P. 11

12 k Effective for Dense and Porous Low k Dielectrics Barrier Node k Th Cap Node k Th Dense Low k Dense Dielectric Dielectric Barrier Cu Dense Dielectric Porous Low k Porous Dielectric Dielectric Barrier Cap Node (nm): k = k = NA k = k = k = liner Cu Intermediate Etch Stop Layer Porous Dielectric Dielectric liner (k=4, t=5nm) ESL Node k Th Must simplify porous low k integration to realize benefits P. 12

13 BEOL Integration Challenges Low k Dielectrics Low k dielectrics required for capacitance scaling, but: Weaker electrical and mechanical properties are a concern UV Thermal Processing (UVTP) improves film modulus High porosity of Ultra Low k (ULK) films presents integration issues Reduced pore interconnectivity enables standard process for lower cost 1.4 Epoxy 1.2 h 1.0 iald TaN ULK k vs. Hardness for Porous ULK Ta EDS Line Scan UV -Cure Closed Pore Behavior No Penetration of iald barrier Thermal Cure k (1/V)*(dV/dD) Fractional Volume Distribution at 5.1 kev (370 nm) 15% Lower RC K=2.85 dense film K=3.0 dense film HMS (k=3) K=2.7 dense film ULK (k=2.5) K=2.5 porogen based film Spherical Pore Diameter (nm) Integration of ultra low k dielectrics demonstrated at k = 2.5 P. 13

14 Making a Reliable SiC Diffusion Barrier Resistance to moisture and oxygen H 2 O absorption in damaged CDO O 2 /H 2 O reaction forms Cu x O Interfacial O (atoms/cm 2 ) 1E+16 1E+15 1E+14 Dielectric Constant SiC Cap on damaged Coral Permeable SiC Hermetic SiC Time (hours) % Adhesion Failures (< 5 J/m 2 ) 1E No Cu x O Reduction No Cu x O Reduction Permeable SiC Permeable SiC Hermetic SiC Hermetic SiC Hermeticity of the dielectric barrier is key to Cu/low k reliability P. 14

15 Engineering R Goal is to lower interconnect resistance by: Alleviating contact R increase through material changes Replace high resistivity Ti/TiN with WN Reducing barrier thickness to maximize Cu volume in trench While maintaining reliability Reducing via resistance by optimizing: Etch and post-etch clean Pre-sputter clean Barrier deposition Must also optimize resistivity for smaller feature sizes Optimization of Cu plating chemistry and anneal P. 15

16 Impact of Scaling on Contact Resistance Contact resistance increasing with scaling: Control of resistance with scaling DirectFill TM WN/Low ρ W Current carrying part of Contact 2600 CVD W Fill W Nucleation TiN/Ti Resistance of 2 Plugs ( Ω ) NMOS Resistance (ITRS : 4xW min ) Direct Fill Ti/TiN/W Technology Node (nm) Elimination of Ti/TiN liner improves R in scaled contacts P. 16

17 Scaling Cu Barrier/Seed Lower line resistance achieved by optimizing Cu volume: Requires thinner barrier while maintaining barrier integrity Effective Resistivity (µ Ω.cm) ITRS Specification 45 nm 25nm PVD (Conventional PVD) 10nm PVD (RF HCM PVD) 65 nm 90 nm 60nm Trench RF HCM TaN Line Width (nm) iald TaN Thinner barrier alleviates line resistance increase with scaling, but process optimization required to maintain interconnect reliability P. 17

18 RF HCM Barrier Step Coverage M = Ta M + M + M Ar + M + M + M + Ar + 1. Barrier Deposition (Ta/TaN) 2. RF Biased Ar + Etch / Ta Deposition As deposited After resputtering P. 18

19 Cu Fill of Scaled Interconnects Challenges for Cu fill of smaller feature size: Smaller features require faster bottom-up fill without overplating Must compensate for nonuniform current distribution from thin Cu seed Cu Seed Protrusion: Need Fast Bottom-up Fill to Prevent Voids FILL TIME Time to fill Thin Cu Seed: Optimize Entry Conditions GENERATION Thin barrier/seed with optimized plating process 80 nm filled trench Overplating New Chemistry Planar Fill New plating chemistry & tool enhancements enable Cu fill extendibility P. 19

20 Optmization of Cu Resistivity ρ (µohm-cm) Cu resistivity increases with smaller feature size: Electron scattering from grain boundaries and sidewalls Optimized chemistry/anneal gives large grain size & lower resistivity Copper Anneal/Plating Chemistry Optimized for Large Grain Size INTEL IITC 2004 Surface scattering only Steinhogl MRS 2002 IMEC AMC 2003 NVLS IITC 2005 Cu Grains Line Width (nm) Lower effective Cu resistivity with optimized plating chemistry & anneal P. 20

21 Summary Interconnect performance needs have led to the introduction of Cu and low k dielectrics Cu interconnects mainstream for Logic devices Transition to Cu interconnects underway for Memory devices The successful integration of Cu/low k has required the resolution of numerous technical challenges Cu/low k (k= ) in production at 90nm/65nm technology nodes Cu/low k (k=2.5) in development for 45nm production in 2008 Even greater challenges lie ahead Lower k dielectrics (k < 2.5), ultra thin (< 3nm) metal barriers, fill of sub-50nm features, scaling effects, etc. Collaboration between industry, universities and government is key to fostering innovative solutions and fueling the IC scaling engine P. 21