Very Large Scale Integration (VLSI)

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1 Very Large Scale Integration (VLSI) Lecture 9 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1

2 Content Packaging Input/Output pads Overall organization V DD and V SS pads Output Pads Input pads Tristate and Bidirectional Pads Dr. Ahmed H. Madian-VLSI 2

3 Packages Package functions Electrical connection of signals and power from chip to board with little delay and distortion. Mechanical connection of chip to board Removes heat produced on chip Protects chip from mechanical damage Compatible with thermal expansion Inexpensive to manufacture and test Dr. Ahmed H. Madian-VLSI 3

4 Package Types Through-hole vs. surface mount Dual Inline Packages (DIP), Pin Grid Array (PGA), Plastic Leadless Chip Carrier (PLCC) are convenient for components that might be removed for reprogramming, While Ball Grid Array (BGA) provides large number of highbandwidth signals in compact form Dr. Ahmed H. Madian-VLSI 4

5 Multichip Modules (MCM) Pentium Pro MCM Fast connection of CPU to cache, higher speed. Expensive. Dr. Ahmed H. Madian-VLSI 5

6 Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame Metal pads on μm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling Dr. Ahmed H. Madian-VLSI 6

7 Package Parasitics Use many V DD, GND in parallel Inductance, I DD Package Signal Pins Signal Pads Chip Chip V DD Chip GND Bond Wire Lead Frame Package Capacitor Board V DD Board GND Dr. Ahmed H. Madian-VLSI 7

8 Heat Dissipation 60 W light bulb has surface area of 120 cm 2 Itanium 2 die dissipates 130 W over 4 cm 2 Chips have enormous power densities Cooling is a serious challenge Package spreads heat to larger surface area Heat sinks may increase surface area further Fans increase airflow rate over surface area Liquid cooling used in extreme cases ($) Dr. Ahmed H. Madian-VLSI 8

9 Power Distribution Power Distribution Network functions Carry current from pads to transistors on chip Maintain stable voltage with low noise Provide average and peak power demands Provide current return paths for signals Avoid wear-out of electromigration & selfheating Consume little chip area and wire Easy to lay out Dr. Ahmed H. Madian-VLSI 9

10 content Input/Output pads Overall organization V DD and V SS pads Output Pads Input pads Tristate and Bidirectional Pads Dr. Ahmed H. Madian-VLSI 10

11 I/O pads The I/O system is responsible for communicating data between the chip and the external world. A good I/O system has the following properties Drives large capacitances typical of off-chip signals Operates at voltage levels compatible with other chips Limits slew rates to control high-frequency noise Protects chip against damage from electrostatic discharge (ESD) Protect against over-voltage damage Has a small number of pins (low-cost) Dr. Ahmed H. Madian-VLSI 11

I/O pad organization Pad consists of a square of toplevel metal of approximately 100µm on a side that is either soldered to bond wire connecting to a package or coated with lead solder ball.

12 I/O pad organization Pad consists of a square of toplevel metal of approximately 100µm on a side that is either soldered to bond wire connecting to a package or coated with lead solder ball. Pad refers to metal square only or to the complete I/O cell containing the metal, ESD protection circuit, and I/O transistors. Also sometimes it contains built in receiver and driver circuits to perform level conversion and amplification. Dr. Ahmed H. Madian-VLSI 12

13 I/O pad organization (cont.) Pad size is defined usually by the minimum size to which a bond wire can be attached. This is usually of the border of µ square. The spacing of the pads is defined by the minimum pitch at which bonding machines can operate. Extremely high pad counts may be achieved by interdigitating pads. Pad size pitch I/O circuitry Dr. Ahmed H. Madian-VLSI 13

14 I/O pad organization (cont.) Pads could be designed according to following criteria: Core-limited Pad-limited Dr. Ahmed H. Madian-VLSI 14

15 I/O pad organization (cont.) Core limited The internal core of the chip determines the size of the chip, so thin pads are required. The input/output circuitry is placed on either side of the pad PAD I/O circuitry Dr. Ahmed H. Madian-VLSI 15

16 I/O pad organization (cont.) PAD limited The input/output circuitry is placed toward the center of the chip PAD I/O circuitry Dr. Ahmed H. Madian-VLSI 16

17 I/O pads V DD and V SS Pads Power pads are simply squares of metal connected to the package and the on-chip power grid. High performance chips devote about half of their pins to power. This large number is required to carry the high current and to provide low supply inductance. Dr. Ahmed H. Madian-VLSI 17

18 I/O pads (cont.) V DD and V SS Pads One of the largest sources of noise in many chips is the ground bounce caused when output pads switch. The pads must rapidly charge the large external capacitive loads, causing a big current spike and high L di/dt noise. The problem is especially bad when many pins switch simultaneously, as could be the case of 64-bit off-chip data bus. Solution is to interdigitated such buses with power and ground pins to supply the output current through a low-inductance path. In many designs dirty supply lines are separated from the main power grid to reduce the noise. N driver Dirty V SS Dirty V DD PAD I/O circuitry P driver Clean V SS Clean V DD Dr. Ahmed H. Madian-VLSI 18

19 Output Pads Drive large off-chip loads (2 50 pf) With suitable rise/fall times Requires chain of successively larger buffers Guard rings to protect against latchup Large nmos output transistor p+ inner guard ring n+ outer guard ring In n-well Dr. Ahmed H. Madian-VLSI 19

20 I/O pads Output Pads must have sufficient drive capability to deliver adequate rise and fall times into given capacitive load. If the pad drives resistive load it must also deliver enough current to meet the required DC transfer characteristics. Also, output pads generally contains adequate buffering to reduce the load seen by the on-chip circuitry driving the pad. Dr. Ahmed H. Madian-VLSI 20

21 Input Pads Level conversion Higher or lower off-chip V A V DDH V DDL V Y A Y DDL Noise filtering weak Schmitt trigger A weak Y Y Hysteresis changes V IH, V IL A Protection against electrostatic discharge Dr. Ahmed H. Madian-VLSI 21

22 I/O pads Input pads ESD protection Input pads have transistor gates connected directly to the external world. These gates are subject to damage from electrostatic discharge that can puncture and break down the oxide. (V BD = 5V in modern processes) A protection circuit from diodes and resistors is used to clamp the input signal En Dout NAND Dout NOR Y Current limiting resistor Dr. Ahmed H. Madian-VLSI 22

23 I/O pads (cont.) Clock pads They usually have very high internal loading and have to provide extremely fast rise and fall times. So we have three strategies for the clock buffer CLK CLK CLK CLK CLK CLK Dr. Ahmed H. Madian-VLSI 23

24 Phase Locked Loop Clock Technique Phase locked loops (PLL) are used to generate internal clocks on chips for two main reasons: to synchronize the internal clock of a chip with an external clock to operate the internal clock at a higher rate than the external clock input CLK in FF FF ref CLK Feedback CLK PLL CLK distribution GLB CLK Dr. Ahmed H. Madian-VLSI 24

25 I/O pads (cont.) Bidirectional Pads The output driver could be tri-stated according to the Enable signal NAND Dout En Y Dout NOR Dr. Ahmed H. Madian-VLSI 25

26 Analog Pads Pass analog voltages directly in or out of chip No buffering Protection circuits must not distort voltages Dr. Ahmed H. Madian-VLSI 26

27 Quiz 2 Next week check the web site for exact date Dr. Ahmed H. Madian-VLSI 27

Module 7 : I/O PADs Lecture 33 : I/O PADs

Module 7 : I/O PADs Lecture 33 : I/O PADs Objectives In this lecture you will learn the following Introduction Electrostatic Discharge Output Buffer Tri-state Output Circuit Latch-Up Prevention of Latch-Up