CAD Algorithms. Physical Design Automation

Transcription

1 CAD Algorithms Physical Design Automation of VLSI Systems Mohammad Tehranipoor ECE Department 7 October Physical Design Automation Objectives: Obtain general understanding about IC design process Study design automation Study algorithms Used in designing the layout of a chip Prepare students for exposure to hard CAD problems 7 October

2 VLSI Design Cycle Large number of components: The physical design is not practical without the help of computers. Optimize requirements for higher performance Performance relates to speed, power and size. Time to market competition: Makes the use of computer necessary Cost: Using computer makes it cheaper by reducing time-to-market. Manual System Specifications Chip Automation 7 October VSLI Design Cycle (Cont.) VLSI design cycle can be divided into the following steps: System Specification: Goals and constraints of the system Functionality (what will a system do) Performance figures like speed and power Technology constraints like size and space (physical dimensions) Fabrication technology and design techniques Architectural/Functional Design: RISC, CISC, # of ALUs, floating point units, number and structure of pipelines, etc. Functional behavior and functional units to match specification Functional subunits and relationship among them 7 October

3 VSLI Design Cycle (Cont.) Logic Design: Implementation of functional subunits using logic representation Boolean expressions, finite state machines or schematics. Use of standard building blocks like RAM, ROM, PLA, etc. Logic design should match functional description. Register Transfer Level (RTL) description of subunits. RTL is expressed in VHDL or Verilog. Circuit Design Logic networks or descriptions are converted into electronic circuits. Circuit elements are designed to meet specifications. Transistors are sized for current capacity and delay requirements. Circuit simulation is used to verify the correctness and timing of each component. 7 October VSLI Design Cycle (Cont.) Physical Design: That s the focus of our course. The circuit representation is converted into a geometric representation. Geometric representation of a circuit is called layout. The exact details of the layout depends on design rules. Design rules are guidelines based on the limitations of the fabrication process. 7 October

4 VSLI Design Cycle (Cont.) CAD Tools: Layout synthesis tools are fast but do have area and performance penalties. Manual layout is very slow but does have better area and performance. Most of the layout of a high performance custom design may be done using manual design. Synopsys, Cadence, Mentor Graphics, Magma, and more Note that the objective of VLSI CAD tools are to minimize the time for each iteration and the total number of iterations, thus reducing time-to-market. 7 October VSLI Design Cycle (Cont.) Fabrication: After layout and verification, the design is ready for fabrication (called tapeout). Layout data is converted into photo-lithographic masks. Testing and Debugging: After fabrication, each die is tested. The wafer is diced into individual chips. Each chip is packaged and tested. 7 October

5 VLSI Design Cycle System Specifications Functional Design X=(AB*CD)+ Logic Design Circuit Design 7 October VLSI Design Cycle Physical Design Fabrication Packaging 7 October

6 New Trends in VLSI Design Cycles Increasing Interconnect Delay: Interconnect is not scaling at the same rate as the devices. Almost 60% of path delay may be due to interconnect. Increasing Interconnect Area: Almost 30-40% of the area is covered by interconnects in modern designs. Interconnect vs. Gate Delay Relative Delay Technology Node (nm) ITRS October New Trends in VLSI Design Cycles Increasing number of Metal Layers: To meet the increasing need of interconnect, number of metals is increasing. Up to 12 metal layer in the next few years In nanometer technology designs: More silicon area consumed by wires Miles of Cu wires Increasing wire lengths and interconnect defects, i.e. more bridging faults Increasing number of vias Metal layers Many Metal Layers 7 October

7 New Trends in VLSI Design Cycles Increasing Planning Requirements: Physical design considerations have to enter into design at much earlier phase. Synthesis: The design time can be reduced if layout can be directly generated from a higher level description. Behavioral Model Physical Layout New tools can support it. 7 October Physical Design Process Physical Design converts circuit description into a geometric description. This description is used to manufacture a chip. The input to a physical design cycle is a circuit diagram/netlist and the output is the layout of the circuit. Required Stages: Partitioning Floorplanning Placement Routing Compaction Extraction and Verification (post-layout verification) 7 October

8 New Trends in Physical Design Process Chip Level Signal Planning Routing of major signals and buses must be planned from early design stages, so that the interconnect distances can be minimized. Interconnects length directly impact circuit delay and layout area OTC Routing Over-the-cell (OTC) routing allows routing over blocks and active areas. Reduces the layout area 7 October Major Challenges Crosstalk C c C s C c C s 0.35 µm 90 nm 7 October

9 Cont. Power Supply Noise and Temperature 7 October Power Supply Noise Cont. 7 October

10 Cont. Temperature 7 October Steps of Iterative Design Process Synthesis: Synthesis derives or improves a representation at any step. Behavioral synthesis, logic synthesis and layout synthesis are all examples at various steps. Analysis: Analysis ensures that the design representation matches the requirements at various steps. Requirements like area, power dissipation and speed. Verification: Establishes the correctness of design at any given step. Simulation at any step should match specifications. 7 October

11 Design Process is Iterative Simulation-Based Verification Simulation-Based Verification Behavioral Structural Synthesis Simulation-Based Verification PNR Simulation/Emulation-Based Verification 7 October Design Styles JC Preferred style for mass production, Highly optimized layout, Time can be justified 7 October

12 Selection of Design Style Selection of design styles depends on many factors: Type of chip High performance, Area, Volume Mass production, Medium production volume, Cost Company s budget, Cost of the chip Time-to-market Last two are dominant. 7 October Full Custom Design Style Circuit partitioned into sub-blocks. Blocks can be of any size/shape Hierarchical design Placement on any location is allowed Allows very compact designs Difficult automation High performance The process of automating a fullcustom design style has a much higher complexity than other restricted styles. 7 October

13 Standard Cell Design Style Design process is somewhat simpler than full-custom design style Rectangular cells of same height Library based design Cells arranged in rows Easier automation Inherently nonhierarchical Lower performance Well suited for moderate size designs and medium production volume. Logic synthesis uses standard cell design style. 7 October Standard Cell Channel is the space between two rows. Feedthrough is the empty cells in a row. Feedthroughs are assigned for the interconnections of non-adjacent cells. Standard cell design style takes more area than full custom. Along with semiconductor manufacturing advances, standard cell methodology was responsible for allowing designers to scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complex multi-million gate devices (SoC). 7 October

14 Standard Cell 2-input NAND or NOR function is sufficient to form any arbitrary Boolean function set In modern ASIC design, standard cell methodology is practiced with a sizeable library of cells The library contains multiple implementations of the same logic function, differing in area and speed This variety enhances the efficiency of automated synthesis, place and route tools It gives the designer greater freedom to perform implementation tradeoffs Area vs Speed vs Power Consumption A complete group of standard cell descriptions is commonly called a technology library. The technology library is developed and distributed by the foundry operator. 7 October Gate Array Design Style A simplification of Standard Cell Design Style Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected A regular lattice shaped structure Pre-fabricated logic Both vertical and Horizontal channels Only wiring masks need to be defined Rapid fabrication Low performance Easy automation Non-hierarchical structure Logic synthesis can use gate array. 7 October

15 Gate Array Photo-lithographic masks are required only for the metal layers Production cycles are much shorter as metallization is a comparatively quick process Advantages/Disadvantages: The steps involved for creating any prefabricated wafer are the same Only the last few steps in the fabrication process will be used. Cheaper and easier to produce than full-custom and standard cell. It offers more area and less time. Difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the price Pure, logic-only gate array design is rarely implemented by circuit designers today FPGA is preferred. 7 October Gate Array Today gate arrays are evolving into Structured ASICs Structured ASICs consist of a large IP core like a CPU, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommited logic. This shift is largely because ASIC devices are capable of integrating large blocks of system functionality and "system on a chip" requires far more than just logic blocks. 7 October

16 FPGA Design Style Extremely rapid prototyping Re-programmable Lowest performance Easy automation Cells and interconnects are prefabricated. The user simply programs the interconnects. Contains programmable logic blocks and interconnects Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or mathematical functions. FPGAs contain FFs 7 October LUT Programming Source: Fundamentals of Digital Logic, McGraw Hill October

17 LUT Programming 3-input LUT 7 October LUT Programming Sequential 7 October

18 Comparison of Design Styles Production Volume: Mass Production Volume Medium Production Volume Medium Production Volume Low Production Volume Complexity: High Low 7 October Physical Design Automation Physical design implies physical realization of integrated circuit layout. Input to physical design cycle is a circuit design Circuit netlist (gate level representation) RTL description of the circuit Output from this stage is a layout of the circuit The task from input to output is accomplished in several design stages, each addressing specific goals. 7 October

19 Physical Design Cycle 7 October Physical Design Cycle 7 October

20 Physical Design Cycle 7 October VLSI Design Automation 7 October