Quality. Stages. Alun D. Jones
|
|
|
- Dina Daniel
- 8 years ago
- Views:
Transcription
1 Quality - by Design Quality Design Review Stages Alun D. Jones
2 Design Review Stages Design Review 0 (DR0) Pre-order & quotation stage Design Review 1 (DR1) Initial kick-off and preliminary specification review Design Review 2 (DR2) Pre-layout simulation review of final design Design Review 3 (DR3) Post-layout simulation review of final design Layout DRC, ERC & LVS review Design Review 4 (DR4) Prototype review Design Review 5 (DR5) Production review
3 Design Review 0 DR0 Design Target Specification, description & schematics etc., Planning Development plan, proposed sample & production timescales. Production quantities. Manufacturing Package type & general specification. Tester & tooling requirements. Commercial Unit cost estimates, volumes, ASP, & NRE costs. Special costs (Tooling, qualification). Safety & Reliability Design safety & reliability requirements. Product life-cycle requirements. Environmental conditions. Qualification requirements.
4 From DR0 to DR1 DR0 Customer Contact Draft Specification Feasability & Technology Studies Quotation DR1 Customer Review
5 Design Review 1 DR1 Design Target Specification, description & schematics etc., Wafer fab technologies, design rules, special issues Planning Task allocation & resources Development plan, sample & production timescales Production quantities & schedules Manufacturing Package type, package approval status & general specification Tester, tooling & assembly requirements Commercial Die size estimates, unit cost estimates, wafer costs & yields Capital & Tooling costs Quality, Safety, Reliability & Risk assessment. Quality plan Risks - Identification & Assessment Design safety & reliability requirements, with life-cycle definition.
6 From DR1 to DR2 DR1 Customer Review Schematic Capture VHDL Text Synthesis Netlist & Simulation DR2 Acceptance
7 Design Review 2 DR2 Design Specification, description, block diagrams & schematics etc., Simulation data. Performance against specification, any special issues. Planning Progess and outstanding actions. Development plan, with sample timescales. Production quantities & schedules. Manufacturing Package type, package approval status & general specification. Assembly requirements, piece parts & travellers. Commercial Die size estimates, unit cost estimates, wafer costs & yields, any changes? Quality, Safety, Reliability & Risk assessment. Quality plan review & update Risks - review, any new risks identified?.
8 From DR2 to DR3 DR2 Acceptance Manual Layout Auto Place & Route DRC / ERC / LVS & Extraction Post-Layout Simulation & Chip Finish DR3 Acceptance
9 Design Review 3 DR3 Design Specification, description, block diagrams & schematics etc., Layout and post-layout Simulation data, performance issues. LVS, DRC, ERC, Customer checks, die fiducials, Bonding data. Planning Progess and outstanding actions. Update of development plan, with sample timescales. Update of Production quantities & schedules. Manufacturing Bonding diagram, branding data, BOM defined, wafer testing. Sample & production travellers for Assembly, Test and Qualification. Commercial Die size estimates, unit cost re-estimate, fab timescales, any changes? Quality, Reliability & Risk assessment. Quality plan review & update Risks - review, any new risks identified?.
10 From DR3 to DR4 DR3 Acceptance GDSII Tape Out Test Vectors Mask Making & Processing Test Specification Cut- n-go Prototype Test Program Customer Evaluation Compliance Testing DR4 Acceptance
11 Design Review 4 DR4 Design Specification, description, block diagrams & schematics etc., Samples meet specification, problems identified? Planning Progess and outstanding actions. Update of development plan, with production timescales. Update of Production quantities & schedules. Manufacturing Any problems/changes from Assembly, Test and Qualification? Characterization data from samples. Commercial Yield issues? Quality, Reliability. Quality plan review & update Done It!
12 From DR4 to DR5 DR4 Prototype Acceptance Wafer Probe Test It Works Packaging Final Delivery Test Additional Process Tests & Yield Analysis DR5 Production Review
13 Design Review 5 DR5 Design Yield issues, customer returns? Planning / Project Outstanding actions. Update of Production quantities & schedules. Characterization / Qualification complete. Manufacturing Any problems from Assembly, Test and Qualification? Commercial Yield issues? Quality, Reliability. Quality plan issued. What Problems? No Problems Boss!
14 Some relevant considerations to getting it right! Reliability Risk Assessment Packaging Proving the design (verification) Manufacturing Commercial considerations
15 Reliability Application requirement Operational life & Infant Mortality Hazardous environment (to device) Mission criticality? Environment When device active? Long term storage? Operational and shelf storage Choice of Foundry Appropriate technology? Suitable design rules for application? Characterised silicon for intended use?
16 Risk Assessment Chances of Success Avant-Garde design Unusual techniques Poor information Design criticality Failure Mode Analysis Life-Cycle requirements Application Environment Use of device outside of design rules Testability & Manufacturability
17 Packaging Ceramic / Plastic / Metal etc., Package and lid match number of pins Electrical characteristics & performance Attach method Eutectic Ag-Glass general Adhesives Bonding rules... Au or Al? Bond wire length and angles? Pad sizes and spacing Current carrying capacity Lead finish
18 Design verification Digital Verilog or VHDL netlists... Verilog often preferred by foundries VHDL often preferred by Designers Pre- and Post-Layout checking... SDF file creation Min-Typ-Max simulation Test benches Fault coverage (stuck-at faults) Automatic & Application Test Vector Generation ATE Tester Vector Generation ATE Tester semantics Critical Path Timing data Test specification Guardbanding
19 Design verification Analog SPICE netlists Many SPICE flavours, netlist conversion? Pre- and Post-Layout checking... Parasitic back extraction Sweep & Monte Carlo simulation Test benches Multiple SPICE test benches ATE Tester semantics Test specification Test set-up and parametric measurements critical. Tester noise floor Tester measurement resolution & accuracy
20 Design verification Mixed Signal As both Analog & Digital, plus Signal / data-path partitioning A/D & D/A interfacing techniques Separate power/ground supplies? Test bench set-up now very critical... Mixed-mode simulation Analog/Digital test synchronisation Testability Intermediate test and capture points / nodes Test equipment capability Special test bench set-ups Test Specification!!! Guardbanding
21 Manufacturing Test Testability of design adequate test coverage Test socketing Suitable for temperature extremes Test throughput --- realistic tests Test time vs. test coverage Manufacture Acceptable yield profile Special processing Project control Project maintenance Cost reduction Test time reduction Flow control Volume purchasing
22 Commercial Projected yield Gross Die / Wafer Die yield at test Yield after packaging Packaging costs Post processing Device testing Environmental screening Life testing
23 Finally, the most important ingredients... Customer Involvement Pragmatism Honesty
24 ASE s Design Capability Software (CAD) Hardware Silicon vendor specific
25 ASE Design Tools Software Cadence Tools (on Sun Sparc w/s) Analog Artist Capture (Virtuoso Composer) Analog Artist Layout (Virtuoso) with DLE Spectre & cdsspice Verilog-XL Verilog-Spectre Integration DIVA Extraction DIVA LVS, DRC and ERC Other Tanner tools (LEDIT etc.,), pspice ECS capture system, Protel capture system ModelSim (Mentor), with CodeRight Actel Designer Software
26 ASE Design Tools Hardware Design Hardware Five Sun workstations (SunOS & Solaris) Numerous PC s (Win 9x, Win-XP, Win-7) HP 36 colour plotter (Design Jet 1055CM) Interfaces for DAT CDROM QIC ZIP Floppy Hardware Archive Rotating archive on DAT tape (incl. annual storage) Nightly backup (every night)
27 ASE Design Tools Vendor Kits Vendor kits installed include... Austria Micro Systems X-Fab Zetex (ASE Proprietary Cadence Kit) Alcatel Mietec Zarlink/MHS/Plessey Semiconductors Chip Express (ASE Proprietary Cadence Kit) MITEL ACTEL Others in various stages, such as Micrel, VersArray, ES2, ABB-HAFO, SAMES, Atmel, Chartered Semi, Dynex, Prema, UTMC, Raytheon, Semefab, Links to Europractice
28 In summary Design reviews are for... Customer partnership Project & QA control ultimate accuracy These stringent controls have given us AND our customers 100% first time success in all ASIC projects!
Virtuoso Analog Design Environment Family Advanced design simulation for fast and accurate verification
Advanced design simulation for fast and accurate verification The Cadence Virtuoso Analog Design Environment family of products provides a comprehensive array of capabilities for the electrical analysis
Design-Kits, Libraries & IPs
Design-Kits, Libraries & IPs Supported CAD tools Design-kits overview Digital, Analog, and RF Libraries IPs Supported CAD tools Design-kits overview ST 65nm Tanner PDK Standard cell Libraries IPs austriamicrosystems
State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop
Photos placed in horizontal position with even amount of white space between photos and header State-of-Art (SoA) System-on-Chip (SoC) Design HPC SoC Workshop Michael Holmes Manager, Mixed Signal ASIC/SoC
EEC 119B Spring 2014 Final Project: System-On-Chip Module
EEC 119B Spring 2014 Final Project: System-On-Chip Module Dept. of Electrical and Computer Engineering University of California, Davis Issued: March 14, 2014 Subject to Revision Final Report Due: June
Space product assurance
ECSS-Q-ST-60-02C Space product assurance ASIC and FPGA development ECSS Secretariat ESA-ESTEC Requirements & Standards Division Noordwijk, The Netherlands Foreword This Standard is one of the series of
Interactive Interface USERS /CMP
Web site: http://cmp.imag.fr General informations Specific informations and forms Interface Users / CMP General informations Web site: Home page Quick References News Upcoming RUNS Customers login General
Agenda. Michele Taliercio, Il circuito Integrato, Novembre 2001
Agenda Introduzione Il mercato Dal circuito integrato al System on a Chip (SoC) La progettazione di un SoC La tecnologia Una fabbrica di circuiti integrati 28 How to handle complexity G The engineering
1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.
.Introduction If the automobile had followed the same development cycle as the computer, a Rolls- Royce would today cost $00, get one million miles to the gallon and explode once a year Most of slides
Technical Overview: WIP Tracking IC Manufacturing Workflow and Cycle-time Reduction. Dr. Klaus ten Hagen, Dr. Michael Orshansky
IC Manufacturing Workflow and Cycle-time Reduction Dr. Klaus ten Hagen, Dr. Michael Orshansky Prepared by esilicon Corporation, Copyright March 2001 Introduction It is well known that talented product
Creating Affordable Silicon
Creating Affordable Silicon John Tinson VP Sales Sondrel 2016 03/05/2016 Presentation Title 1 The IoT Challenge Existing OEM s and start ups would benefit from a custom ASIC to prove their application
System-on. on-chip Design Flow. Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems. jouni.tomberg@tut.
System-on on-chip Design Flow Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems jouni.tomberg@tut.fi 26.03.2003 Jouni Tomberg / TUT 1 SoC - How and with whom?
IL2225 Physical Design
IL2225 Physical Design Nasim Farahini farahini@kth.se Outline Physical Implementation Styles ASIC physical design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification
Interactive Interface USERS /CMP
Web site: http://cmp.imag.fr General informations Specific informations and forms Interface Users / CMP General informations Web site: Home page Quick References News Upcoming RUNS Customers login General
StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs
White Paper StarRC Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs May 2010 Krishnakumar Sundaresan Principal Engineer and CAE Manager, Synopsys Inc Executive Summary IC
Complete ASIC & COT Solutions 1986-2008
Complete ASIC & COT Solutions 1986-2008 www.avnet-asic.com Nadav Ben-Ezer Managing Director 1 March 5th, 2008 Core Business ASIC/SoC Design and Implementation RTL Design Sub-system IP Integration RTL to
Corporate presentation. CNES Décembre 2009 www.id-mos.com
Corporate presentation www.id-mos.com The SERMA group 2008 SERMA Group Turnover : 45 M SERMA Group 446 p 2008 ID MOS Turnover : 5.65 M NEW Subsidiary since 2009 august AXENEON Nuremberg 75 p ID MOS R &
Testing & Verification of Digital Circuits ECE/CS 5745/6745. Hardware Verification using Symbolic Computation
Testing & Verification of Digital Circuits ECE/CS 5745/6745 Hardware Verification using Symbolic Computation Instructor: Priyank Kalla (kalla@ece.utah.edu) 3 Credits Mon, Wed, 1:25-2:45pm, WEB L105 Office
PADS PCB Design Solutions
start smarter D A T A S H E E T PADS PCB Design Solutions The standard in desktop PCB design FEATURES AND BENEFITS: Easy to learn and use Proven technology for PCB design, analysis, and verification Accurately
Chapter 13: Verification
Chapter 13: Verification Prof. Ming-Bo Lin Department of Electronic Engineering National Taiwan University of Science and Technology Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010,
VHDL-Testbench as Executable Specification
VHDL- as Executable Specification Michael Pichler Zentrum für Mikroelektronik Aargau Fachhochschule Aargau, Steinackerstrasse 5, CH-5210 Windisch Web: www.zma.ch - E-mail: m.pichler@zma.ch Seite 1 Overview
Objective. Testing Principle. Types of Testing. Characterization Test. Verification Testing. VLSI Design Verification and Testing.
VLSI Design Verification and Testing Objective VLSI Testing Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut Need to understand Types of tests performed at different stages
Tanner EDA L-edit (Layout Editor)
Tanner EDA L-edit (Layout Editor) Tanner Tools Speeding Concept to Silicon EDA= Electronic Design and Automation NOTE: This tutorial was constructed in L-edit version 1.15 (c. October 2007) http://www.tanner.com/eda/
Eingebettete Systeme. 4: Entwurfsmethodik, HW/SW Co-Design. Technische Informatik T T T
Eingebettete Systeme 4: Entwurfsmethodik, HW/SW Co-Design echnische Informatik System Level Design: ools and Flow Refinement of HW/SW Systems ools for HW/SW Co-Design C-based design of HW/SW Systems echnische
MEMS Processes from CMP
MEMS Processes from CMP MUMPS from MEMSCAP Bulk Micromachining 1 / 19 MEMSCAP MUMPS processes PolyMUMPS SOIMUMPS MetalMUMPS 2 / 19 MEMSCAP Standard Processes PolyMUMPs 8 lithography levels, 7 physical
INF4420 Introduction
INF4420 Introduction Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline Practical information about the course. Context (placing what we will learn in a larger context) Outline of the
VARIATION-AWARE CUSTOM IC DESIGN REPORT 2011
VARIATION-AWARE CUSTOM IC DESIGN REPORT 2011 Amit Gupta President and CEO, Solido Design Automation Abstract This report covers the results of an independent worldwide custom IC design survey. The survey
First, in developing the perfect electrical center, there are essential tools required.
The Misunderstood Myth about Fixtureless Probers By Jim Axton of Test Connections, Inc. The 2001 printed circuit board industry slow down resulted in many PCB fabricators turning to flying probes as their
SR. SIGNAL INTEGRITY ENGINEER
SR. SIGNAL INTEGRITY ENGINEER Specialist in electrical simulation of advanced package devices. This job requires an individual with outstanding electrical simulation and performance characterization skills
SoC Curricula at Tallinn Technical University
SoC Curricula at Tallinn Technical University Margus Kruus, Kalle Tammemäe, Peeter Ellervee Tallinn Technical University Phone: +372-6202250, Fax: +372-6202246 kruus@cc.ttu.ee nalle@cc.ttu.ee lrv@cc.ttu.ee
Digital Systems. Role of the Digital Engineer
Digital Systems Role of the Digital Engineer Digital Design Engineers attempt to clearly define the problem(s) Possibly, break the problem into many smaller problems Engineers then develop a strategy for
Product Development Flow Including Model- Based Design and System-Level Functional Verification
Product Development Flow Including Model- Based Design and System-Level Functional Verification 2006 The MathWorks, Inc. Ascension Vizinho-Coutry, avizinho@mathworks.fr Agenda Introduction to Model-Based-Design
Prototyping Printed Circuit Boards
Prototyping Printed Circuit Boards From concept to prototype to production. (HBRC) PCB Design and Fabrication Agenda Introduction Why PCBs? Stage 1 Understanding the rules Stage 2 Planning the board. Stage
Streamlining the creation of high-speed interconnect on digital PCBs
Streamlining the creation of high-speed interconnect on digital PCBs The Cadence integrated high-speed design and analysis environment streamlines creation of high-speed interconnect on digital PCBs. A
VLSI Design Verification and Testing
VLSI Design Verification and Testing Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text Michael L. Bushnell and Vishwani D. Agrawal, Essentials of Electronic Testing, for Digital,
DIGITAL DESIGN FLOW OPTIONS
DIGITAL DESIGN FLOW OPTIONS A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in the Graduate School of The Ohio State University By Sagar Vidya Reddy, B.E.
Your End-to-End PCB products design and Manufacturing in the 21 st Century
Your End-to-End PCB products design and Manufacturing in the 21 st Century Who Are We? An engineering and manufacturing company dedicated to the advancement of technology that provides solutions related
ASCIA - A Multi-Vendor IC Design System. Thomas Harriehausen
ASCIA - A Multi-Vendor IC Design System Thomas Harriehausen Siemens AG, Semiconductor Division P.O. Box 80 17 09, D-81617 Munich, Germany Phone: +49 89 4144-4762 September 9, 1996 INTERNATIONAL CADENCE
ECE 410: VLSI Design Course Introduction
ECE 410: VLSI Design Course Introduction Professor Andrew Mason Michigan State University Spring 2008 ECE 410, Prof. A. Mason Lecture Notes Page i.1 Age of electronics microcontrollers, DSPs, and other
Cadence SiP Design Connectivity-driven implementation and optimization of singleor multi-chip SiPs
Connectivity-driven implementation and optimization of singleor multi-chip SiPs System-in-package (SiP) implementation presents new hurdles for system architects and designers. Conventional EDA solutions
Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX
White Paper Testing Low Power Designs with Power-Aware Test Manage Manufacturing Test Power Issues with DFTMAX and TetraMAX April 2010 Cy Hay Product Manager, Synopsys Introduction The most important trend
Introduction to Digital System Design
Introduction to Digital System Design Chapter 1 1 Outline 1. Why Digital? 2. Device Technologies 3. System Representation 4. Abstraction 5. Development Tasks 6. Development Flow Chapter 1 2 1. Why Digital
A Mixed-Signal System-on-Chip Audio Decoder Design for Education
A Mixed-Signal System-on-Chip Audio Decoder Design for Education R. Koenig, A. Thomas, M. Kuehnle, J. Becker, E.Crocoll, M. Siegel @itiv.uni-karlsruhe.de @ims.uni-karlsruhe.de
Unlimited Product Licensing Cost-Effectively Eliminate Design Bottlenecks. Dr Ivan Pesic
Unlimited Product Licensing Cost-Effectively Eliminate Design Bottlenecks Dr Ivan Pesic Traditional Licensing Problems Traditional point tool licensing is too expensive and inflexible, offering very low
Easy Step 1000 Stepper Driver Module
Easy Step 1000 Stepper Driver Module STEPPER MOTOR DRIVER MODULE Example Connection Diagram 2 The Easy Step 1000 (ES1000) is intended to be the link between a microprocessor and stepper motor. The ES1000
Document Contents Introduction Layout Extraction with Parasitic Capacitances Timing Analysis DC Analysis
Cadence Tutorial C: Simulating DC and Timing Characteristics Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group rev S06 (convert to spectre simulator) Document Contents Introduction
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course. Module-VII Lecture-I Introduction to Digital VLSI Testing
Design Verification and Test of Digital VLSI Circuits NPTEL Video Course Module-VII Lecture-I Introduction to Digital VLSI Testing VLSI Design, Verification and Test Flow Customer's Requirements Specifications
HOW PRODUCTS GET DESIGNED
HOW PRODUCTS GET DESIGNED Introduction: This is a description of DFAD s role as an electronics design center, in designing products or projects for you. It also explains the interactions between all parties
Custom design services
Custom design services Your partner for electronic design services and solutions Barco Silex, Barco s center of competence for micro-electronic design, has established a solid reputation in the development
At-Speed Test Considering Deep Submicron Effects. D. M. H. Walker Dept. of Computer Science Texas A&M University walker@cs.tamu.
At-Speed Test Considering Deep Submicron Effects D. M. H. Walker Dept. of Computer Science Teas A&M University walker@cs.tamu.edu Integrated Circuit Testing IC Test What s Going On Test Generation Test
University of Texas at Dallas. Department of Electrical Engineering. EEDG 6306 - Application Specific Integrated Circuit Design
University of Texas at Dallas Department of Electrical Engineering EEDG 6306 - Application Specific Integrated Circuit Design Synopsys Tools Tutorial By Zhaori Bi Minghua Li Fall 2014 Table of Contents
which is responsible for CAD tools, libraries, technology data; customer support is shared with local CAD groups
ASCIA - A Multi-Vendor IC Design System Dr. Thomas Harriehausen CAD SYS Tel.: (89) 4144-4762 Internet email: harrie@hl.siemens.de Dr. Harriehausen, Siemens Halbleiter Objectives of this Presentation Present
Digital IC Design Flow
Collège Militaire Royal du Canada (Cadence University Alliance Program Member) Department of Electrical and Computer Engineering Départment de Génie Electrique et Informatique RMC Microelectronics Lab
Royal Military College of Canada
Microelectronics Lab Cadence Tutorials Layout Design and Simulation (Using Virtuoso / Diva / Analog Artist) Department of Electrical & Computer Engineering Royal Military College of Canada Cadence University
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design
Curriculum for a Master s Degree in ECE with focus on Mixed Signal SOC Design Department of Electrical and Computer Engineering Overview The VLSI Design program is part of two tracks in the department:
9/14/2011 14.9.2011 8:38
Algorithms and Implementation Platforms for Wireless Communications TLT-9706/ TKT-9636 (Seminar Course) BASICS OF FIELD PROGRAMMABLE GATE ARRAYS Waqar Hussain firstname.lastname@tut.fi Department of Computer
An Advanced Behavioral Buffer Model With Over-Clocking Solution. Yingxin Sun, Joy Li, Joshua Luo IBIS Summit Santa Clara, CA Jan.
An Advanced Behavioral Buffer Model With Over-Clocking Solution Yingxin Sun, Joy Li, Joshua Luo IBIS Summit Santa Clara, CA Jan. 31, 2014 Agenda 1. SPICE Model and Behavioral Buffer Model 2. Over-Clocking
PADS PCB Design Solutions
PADS PCB Design Solutions The standard in desktop PCB design PCB Flow D A T A S H E E T Major product benefits Proven, reliable PCB design technology Powerful, yet easy-to-use Scalable to grow as your
Printed Circuit Boards. Bypassing, Decoupling, Power, Grounding Building Printed Circuit Boards CAD Tools
Printed Circuit Boards (PCB) Printed Circuit Boards Bypassing, Decoupling, Power, Grounding Building Printed Circuit Boards CAD Tools 1 Bypassing, Decoupling, Power, Grounding 2 Here is the circuit we
VON BRAUN LABS. Issue #1 WE PROVIDE COMPLETE SOLUTIONS ULTRA LOW POWER STATE MACHINE SOLUTIONS VON BRAUN LABS. State Machine Technology
VON BRAUN LABS WE PROVIDE COMPLETE SOLUTIONS WWW.VONBRAUNLABS.COM Issue #1 VON BRAUN LABS WE PROVIDE COMPLETE SOLUTIONS ULTRA LOW POWER STATE MACHINE SOLUTIONS State Machine Technology IoT Solutions Learn
PADS PCB Design Solutions The standard in desktop PCB design
PADS PCB Design Solutions The standard in desktop PCB design PCB Flow D A T A S H E E T Major product benefits = Proven, reliable PCB design technology = Powerful, yet easy-to-use = Scalable to grow as
PowerPlay Power Analysis & Optimization Technology
Quartus II Software Questions & Answers Following are the most frequently asked questions about the new features in Altera s Quartus II design software. PowerPlay Power Analysis & Optimization Technology
JTAG Applications. Product Life-Cycle Support. Software Debug. Integration & Test. Figure 1. Product Life Cycle Support
JTAG Applications While it is obvious that JTAG based testing can be used in the production phase of a product, new developments and applications of the IEEE-1149.1 standard have enabled the use of JTAG
Echtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur
Echtzeittesten mit MathWorks leicht gemacht Simulink Real-Time Tobias Kuschmider Applikationsingenieur 2015 The MathWorks, Inc. 1 Model-Based Design Continuous Verification and Validation Requirements
Allegro Design Authoring
Create design intent with ease for simple to complex designs Systems companies looking to create new products at the lowest possible cost need a way to author their designs with ease in a shorter, more
System-on-Chip Design with Virtual Components
FEATURE ARTICLE Thomas Anderson System-on-Chip Design with Virtual Components Here in the Recycling Age, designing for reuse may sound like a great idea. But with increasing requirements and chip sizes,
Flex Circuits for the ATLAS Pixel Detector
Flex Circuits for the ATLAS Pixel Detector P. Skubic University of Oklahoma Outline ATLAS pixel detector ATLAS prototype Flex hybrid designs Performance simulations Performance measurements Wire bonding
Combinational Controllability Controllability Formulas (Cont.)
Outline Digital Testing: Testability Measures The case for DFT Testability Measures Controllability and observability SCOA measures Combinational circuits Sequential circuits Adhoc techniques Easily testable
CADENCE LAYOUT TUTORIAL
CADENCE LAYOUT TUTORIAL Creating Layout of an inverter from a Schematic: Open the existing Schematic Page 1 From the schematic editor window Tools >Design Synthesis >Layout XL A window for startup Options
Adapters - Overview. Quick-Turn Solutions for IC Supply Issues
Adapters - Overview BGA to BGA Adapter BGA to PGA BGA to QFP BGA to BGA QFP to BGA SMT to DIP SMT to SMT PGA to PGA BGA to QFP Adapter with VR using FlexFrame Interconnect TSOP Adapter Packaged Die to
ESP-CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation
Datasheet -CV Custom Design Formal Equivalence Checking Based on Symbolic Simulation Overview -CV is an equivalence checker for full custom designs. It enables efficient comparison of a reference design
Route Power 10 Connect Powerpin 10.1 Route Special Route 10.2 Net(s): VSS VDD
SOCE Lab (2/2): Clock Tree Synthesis and Routing Lab materials are available at ~cvsd/cur/soce/powerplan.tar.gz Please untar the file in the folder SOCE_Lab before lab 1 Open SOC Encounter 1.1 % source
ECE 510 Lecture 15 Manufacturing Test Methods. Glenn Shirley Scott Johnson
ECE 510 Lecture 15 Manufacturing Test Methods Glenn Shirley Scott Johnson Manufacturing Test Flow Outline The Ramp. Initial Flow. High-Volume Manufacturing (HVM) Flow. Purpose of Various Test Modules.
Digital Systems Design! Lecture 1 - Introduction!!
ECE 3401! Digital Systems Design! Lecture 1 - Introduction!! Course Basics Classes: Tu/Th 11-12:15, ITE 127 Instructor Mohammad Tehranipoor Office hours: T 1-2pm, or upon appointments @ ITE 441 Email:
The Evolution of ICT: PCB Technologies, Test Philosophies, and Manufacturing Business Models Are Driving In-Circuit Test Evolution and Innovations
The Evolution of ICT: PCB Technologies, Test Philosophies, and Manufacturing Business Models Are Driving In-Circuit Test Evolution and Innovations Alan J. Albee Teradyne Inc. North Reading, Massachusetts
Implementation Details
LEON3-FT Processor System Scan-I/F FT FT Add-on Add-on 2 2 kbyte kbyte I- I- Cache Cache Scan Scan Test Test UART UART 0 0 UART UART 1 1 Serial 0 Serial 1 EJTAG LEON_3FT LEON_3FT Core Core 8 Reg. Windows
AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD)
AC 2007-2485: PRACTICAL DESIGN PROJECTS UTILIZING COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD) Samuel Lakeou, University of the District of Columbia Samuel Lakeou received a BSEE (1974) and a MSEE (1976)
How To Design A Chip Layout
Spezielle Anwendungen des VLSI Entwurfs Applied VLSI design (IEF170) Course and contest Intermediate meeting 3 Prof. Dirk Timmermann, Claas Cornelius, Hagen Sämrow, Andreas Tockhorn, Philipp Gorski, Martin
Orcad Layout. Autorouter User s Guide
Orcad Layout Autorouter User s Guide Copyright 1985-2000 Cadence Design Systems, Inc. All rights reserved. Trademarks Allegro, Ambit, BuildGates, Cadence, Cadence logo, Concept, Diva, Dracula, Gate Ensemble,
Table 1. The relationship between courses and EDA tools (P: PC, M: MAC, U:Unix Workstation, T: Engineering Technology only).
Table 1. The relationship between courses and EDA tools (P: PC, M: MAC, U:Unix Workstation, T: Engineering Technology only). Course Mentor Graphics U Viewlogic PowerView U / WorkView P,U Low Cost Tools
3. On the top menu bar, click on File > New > Project as shown in Fig. 2 below: Figure 2 Window for Orcad Capture CIS
Department of Electrical Engineering University of North Texas Denton, TX. 76207 EENG 2920 Quickstart PSpice Tutorial Tutorial Prepared by Oluwayomi Adamo 1. To run the PSpice program, click on Start >
M. Jämsä 6.4.2011 PCB COST REDUCTIONS
M. Jämsä 6.4.2011 PCB COST REDUCTIONS There is an old joke about Commodity Manager of PCB (Printed Circuit Board) having one brain cell only, either occupied by the idea of price reduction or by the idea
RF Module Design: Requirements and Issues
unlicensed technology RF Module Design: Requirements and Issues RF module design and prototype development are hot industry topics. This article discusses the issues and solutions related to RF module
E158 Intro to CMOS VLSI Design. Alarm Clock
E158 Intro to CMOS VLSI Design Alarm Clock Sarah Yi & Samuel (Tae) Lee 4/19/2010 Introduction The Alarm Clock chip includes the basic functions of an alarm clock such as a running clock time and alarm
The accelerometer designed and realized so far is intended for an. aerospace application. Detailed testing and analysis needs to be
86 Chapter 4 Accelerometer Testing 4.1 Introduction The accelerometer designed and realized so far is intended for an aerospace application. Detailed testing and analysis needs to be conducted to qualify
Programmable Frequency Synthesizer
Sample Proposal Programmable Frequency Synthesizer Note from BF: This was submitted by a student in EE413 in a previous semester. The proposal has some shortcomings, but it will give you a good idea of
7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
FACULTY OF POSTGRADUATESTUDIES Master of Science in Computer Engineering The Future University
FACULTY OF POSTGRADUATESTUDIES Master of Science in Computer Engineering The Future University 2 Table of Contents: Page I. Introduction 1 II. Philosophy of the Program 2 III. Aims of the Program 2 IV.
Design of High Temperature Electronics for Well Logging Applications
Design of High Temperature Electronics for Well Logging Applications Bernard Parmentier Schlumberger, France BParmentier@clamart.oilfield.slb.com Ovidiu Vermesan SINTEF, Norway Ovidiu.Vermesan@sintef.no
Laboratory VHDL introduction
Laboratory VHDL introduction Digital Design IE1204 (Note! not included for IE1205) Attention! To access the laboratory experiment you must have: booked a lab time in the reservation system (Daisy). completed
TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING
TIMING-DRIVEN PHYSICAL DESIGN FOR DIGITAL SYNCHRONOUS VLSI CIRCUITS USING RESONANT CLOCKING BARIS TASKIN, JOHN WOOD, IVAN S. KOURTEV February 28, 2005 Research Objective Objective: Electronic design automation
Engineering Change Order (ECO) Support in Programmable Logic Design
White Paper Engineering Change Order (ECO) Support in Programmable Logic Design A major benefit of programmable logic is that it accommodates changes to the system specification late in the design cycle.
Impact of Signal Integrity on System-On-Chip Design Methodologies
EDP 2004 Impact of Signal Integrity on System-On-Chip Methodologies Juan-Antonio Carballo jantonio@us.ibm.com VSIA IMP co-chair Raminderpal Singh IBM Systems and Technology raminder@us.ibm.com VSIA IMP
Testing of Digital System-on- Chip (SoC)
Testing of Digital System-on- Chip (SoC) 1 Outline of the Talk Introduction to system-on-chip (SoC) design Approaches to SoC design SoC test requirements and challenges Core test wrapper P1500 core test
Total Hot Spot Management from Design Rule Definition to Silicon Fabrication
Total Management from Rule Definition to Silicon Fabrication Soichi Inoue, Toshiya Kotani, Shigeki Nojima, Satoshi Tanaka, Kohji Hashimoto, and Ichiro Mori & Manufacturing Engineering Center, Toshiba Corporation,
SIMATIC IT Unicam Test Expert
NPI solutions for electronics Test engineering solutions for PCB Assembly: accelerated test and inspection SIMATIC IT Unicam Test Expert Answers for industry. Simatic IT for the electronics industry Simatic
AES1. Ultra-Compact Advanced Encryption Standard Core. General Description. Base Core Features. Symbol. Applications
General Description The AES core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. Basic core is very small (start at 800 Actel tiles). Enhanced versions
PROJECT MANAGEMENT PLAN TEMPLATE < PROJECT NAME >
PROJECT MANAGEMENT PLAN TEMPLATE < PROJECT NAME > Date of Issue: < date > Document Revision #: < version # > Project Manager: < name > Project Management Plan < Insert Project Name > Revision History Name
Sequential 4-bit Adder Design Report
UNIVERSITY OF WATERLOO Faculty of Engineering E&CE 438: Digital Integrated Circuits Sequential 4-bit Adder Design Report Prepared by: Ian Hung (ixxxxxx), 99XXXXXX Annette Lo (axxxxxx), 99XXXXXX Pamela
OrCAD Lite Products Reference
Product Version 16.6 October 2012 Updated on: February 19, 2014 1991 2014 Cadence Design Systems, Inc. All rights reserved. Portions Apache Software Foundation, Sun Microsystems, Free Software Foundation,
Teaching the Importance of Data Correlation in Engineering Technology
Session 3549 Teaching the Importance of Data Correlation in Engineering Technology Michael R. Warren, Dana M. Burnett, Jay R. Porter, and Rainer J. Fink Texas A&M University Abstract To meet the needs