SRAM design challenges in nano-scale CMOS

Transcription

1 SRAM design challenges in nano-scale CMOS Vivek De Circuits Research Lab Acknowledgment: M. Agostinelli, A. Farhang, F. Hamzaoglu, A. Keshavarzi, D. Khalil, M. Khellah, N-S. Kim, G. Pandya, S. Rusu, D. Somasekhar, Y. Wang, C. Webb, Y. Ye, K. Zhang 1

2 Outline SRAM scaling trends Emerging challenges Circuit & design techniques Research opportunities 2 Vivek De

3 SRAM cell area & Vmin scaling 0.5X cell area scaling at constant Vmin becoming difficult Density vs. Vmin trade-off impacts are significant 3 Vivek De

4 Array efficiency & cycle time scaling 180 Example projections assuming traditional scaling Technology Generation (nm) 100% 80% 60% 40% 20% 0% Array Efficiency 180 Example projections assuming traditional scaling Technology Generation (nm) Frequency (GHz) Array efficiency degrades with traditional scaling Array efficiency vs. cycle time trade-off impacts significant 4 Vivek De

5 Memory latency & LLC power density Memory Latency (Clocks) Assume: 50ns Memory latency Freq (MHz) Power Density (Watts/cm 2 ) Logic Memory 0.25μ 0.18μ 0.13μ 0.1μ Memory latency demands bigger last level cache (LLC) Cache is more energy-efficient efficient than logic 5 Vivek De

6 Cache % of Total Area 100% 75% 50% 25% 0% LLC integration trends Desktop & mobile processors Server processors Pentium M Pentium III 486 Pentium Pentium 4 1u 0.5u 0.25u 0.13u 65nm LLC area approaching 50% in desktop & mobile processors LLC area approaching 80% in server processors 6 Vivek De

7 SRAM cell design trends 0.46x1.24um IEDM 02 Cell on 90nm (1um2) Improve CD control by unidirectional poly Relax critical layer patterning requirements Optimizing design rules is key Cell on 65nm (0.57um2) Shorter bitline enables better cycle time and/or array efficiency cy Full metal wordline with wider pitch achieves better RC 7 Vivek De

8 Cell transistor scaling challenges Mean # Dopant Atoms Random dopant fluctuation PMOS NMOS Oxide charge fluctuation Line edge roughness Cell transistor ratioing width, length, Vt Width variations & defects due to diffusion notches Gate dielectric leakage cell failure & bitline leakage impacts Narrow width device performance & leakage Fin dimension variations in trigate/finfet Area impact of width-based transistor ratioing in trigate/finfet 8 Vivek De

9 Array Vmin scaling challenges Shrinking Voltage Range V MIN V MAX Cache fail rate 84.1% Total power 99.9% 97.7% 1X 2X 3X Performance 50% SER Reliability 15.9% 2.3% Increasing array size volts 0.14% Vmin (V) Active Vmin limits read failure, write failure, access failure Standby Vmin limits data retention, SER Redundancy & cell size density vs. Vmin knob Vmin degrades over time due to transistor aging Power-limited, multi-core processors with single Vcc 9 Vivek De

10 Erratic bit failures Increased sampling Need more complex error detection & correction schemes Dynamic Pellston engine for cache line disabling Additional density & performance impacts 10 Vivek De

11 Gate dielectric leakage impacts Rg Stress aggravates impact Shows 1/f behavior 11 Vivek De

12 Performance impact of bitline leakage Courtesy: K. Agawa et al., JSSC, May 2001 Reduced effective cell current Negative bitline swing development Need to use bitline leakage compensation & reduction techniques 12 Vivek De

13 Dual-Vcc + dynamic sleep Push active Vmin limit to Vmax Embedded level shifters for wordline & write drivers minimize area & power overhead Reduce idle power: NMOS sleep with passive clamp Reduce idle power: PMOS sleep with passive clamp 13 Vivek De

14 Sleep transistor with active clamp 14 Vivek De

15 PVT variation & aging tolerance Process (P) variation tolerance Voltage (V) variation tolerance Temperature (T) variation tolerance Aging tolerance 15 Vivek De

16 Multi-Vcc cell & array design Optimum voltage choices Improved static noise margin (SNM) for read Improved write noise margin (WNM) Vmax: Max Vcc, Va: Min Vcc Multi-Vcc generation, control, distribution & timing overhead Differential noises among multiple Vcc s s impact cell failure Partial write & pseudo-read support 16 Vivek De

17 Adaptive array biasing NMOS FBB + PMOS RBB: Access & write failures NMOS RBB + PMOS FBB: Read failures Courtesy: S. Mukhopadhyay et al., 2006 Symp. VLSI Circuits Bias generation & selection overheads Body effect scaling Extensions to trigate/finfet 17 Vivek De

18 Cell stability: static vs. dynamic Static read failure (conservative) Static write failure (optimistic) Dynamic read failure (realistic) Wordline Dynamic write failure (realistic) Wordline Need to comprehend realistic dynamic stability in statistical failure rate analysis & array Vmin measurements 18 Vivek De

19 PCH RYSEL0 RYSEL7 SAE Exploit dynamic nature of stability Wordline (WL) pulsing technique WL127 WL0 BL V CC Cell Cell SA V CC BL# PCH WL BL BL# V L V R SAE READ Reduce bitline & sense-amp cap loading BL WL Pulse (ps) Write Read Differential 1.0E E E E-06 Failure Rate (normalized) Optimum WL pulse width to balance read, write & access failures Optimize cell & array design for best dynamic failure rate Hierarchical bitline for improved dynamic failure rate 19 Vivek De

20 Read-assist circuits Courtesy: H. Pilo et al., 2006 Symp. VLSI Circuits Per-column sense-amp area overhead Power overhead of full bitline discharge & precharge 20 Vivek De

21 Performance & power improvement Optimize sense-amp (SA) for input offset, loading, speed & area AC offset improvement bitline segmentation & SA strobe control Bitline decoupled sense-amp reduce timing complexity SA offset compensation cycle time vs. latency Asynchronous array design latency vs. complexity Dynamic Intel smart cache sizing Predict cache usage requirement Dynamically adapt effective cache size Re-power on demand to deliver full performance 21 Vivek De

22 Research opportunities Dynamic multi-vcc & other circuit techniques Vmin tracking for PVT variations & aging Resilient techniques for access failures Adaptive cache size, cycle time & latency Application of cache compression techniques Cache hierarchy, size & performance needs 22 Vivek De