Dual Up-Counter High-Voltage Silicon-Gate CMOS

Transcription

1 TECNICAL DATA IW20B Dual Up-Counter igh-oltage Silicon-ate CMOS The IW20B Dual Binary Up-Counter coists two identical, internally synchronous -stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going traition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going traition of the CLOCK. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q to the enable input of the subsequent counter while the CLOCK input of the latter is held low. Operating oltage Range:.0 to 18 Maximum input current of 1 μa at 18 over full package-temperature range; 0 na at 18 and 2 C Noise margin (over full package temperature range): 1.0 supply 2.0 supply 2. supply ORDERIN INFORMATION IW20BN Plastic IW20BD SOIC T A = - to 12 C for all packages PIN ASSINMENT LOIC DIARAM FUNCTION TABLE PIN 16= CC PIN 8= ND Inputs Outputs CLOCK ENABLE RESET Mode L Increment Counter L L Increment Counter X L No Change X L No Change L L No Change L No Change X X Q1 thru Q=L X = don t care

2 IW20B MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ND) -0. to +20 IN DC Input oltage (Referenced to ND) -0. to CC +0. OUT DC Output oltage (Referenced to ND) -0. to CC +0. I IN DC Input Current, per Pin ± ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ P D Power Dissipation per Output Traistor 0 mw Tstg Storage Temperature -6 to +0 C T L Lead Temperature, 1 mm from Case for Seconds (Plastic DIP or SOIC Package) 260 C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - mw/ C from 6 to 12 C SOIC Package: : - 7 mw/ C from 6 to 12 C mw RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ND).0 18 IN, OUT DC Input oltage, Output oltage (Referenced to ND) 0 CC T A Operating Temperature, All Package Types C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.

3 IW20B DC ELECTRICAL CARACTERISTICS (oltages Referenced to ND) CC uaranteed Limit Symbol Parameter Test Conditio - C 2 C 12 C I Minimum igh-level Input oltage IL Maximum Low - Level Input oltage O OL I IN I CC I OL I O Minimum igh-level Output oltage Maximum Low-Level Output oltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Minimum Output igh (Source) Current OUT = 0. or CC - 0. OUT = 1.0 or CC OUT = 1. or CC - 1. OUT = 0. or CC - 0. OUT = 1.0 or CC OUT = 1. or CC - 1. IN =ND or CC IN =ND or CC Unit IN = ND or CC 18 ±0.1 ±0.1 ±1.0 μa IN = ND or CC 20 IN = ND or CC U OL =0. U OL =0. U OL =1. IN = ND or CC U O =2. U O =.6 U O =9. U O = μa ma ma

4 IW20B AC ELECTRICAL CARACTERISTICS (C L =0pF, R L =kω, Input t r =t f =20 ) CC uaranteed Limit Symbol Parameter Unit - C 2 C 12 C f max Maximum ClockFrequency, (Figure 1) t PL, t PL t PL t TL, t TL Maximum Propagation Delay, Clock or Enable to Output (Figures 1,) Maximum Propagation Delay, Reset to Output (Figure 2) Maximum Output Traition Time, Any Output (Figure 1) C IN Maximum Input Capacitance - 7. pf Mz TIMIN REQUIREMENTS (C L =0pF, R L = kω, Input t r =t f =20 ) CC uaranteed Limit Symbol Parameter - C 2 C 12 C Unit t w Minimum Pulse Width, Clock (Figure 1) t w Minimum Pulse Width, Reset (Figure 2) tw Minimum Pulse Width, Enable (Figure ) t r, tf Maximum Input Rise and Fall Times (Figure 1) μs Figure 1. Switching Waveforms Figure 2. Switching Waveforms

5 IW20B Figure. Switching Waveforms TIMIN DIARAM EXPANDED LOIC DIARAM (1/2 of the Device)

6 IW20B N SUFFIX PLASTIC DIP (MS - 001BB) 16 1 A F 0.2 (0.0) M T NOTES: 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.2 mm (0.0) per side. 9 8 D N B -T- C -T- K SEATIN PLANE M L J Dimeion, mm Symbol MIN MAX A B C. D F J 0 K L M N 0.8 D SUFFIX SOIC (MS - 012AC) 16 1 D A 0.2 (0.0) M T C M 9 8 B K P C SEATIN PLANE Symbol MIN MAX A 9.8 B.8 C D F J 0 8 NOTES: K Dimeio A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion 0. mm (0.006) per side P for A; for B 0.2 mm (0.0) per side. R J R x F M Dimeion, mm