The NPN Transistor Bias and Switching

Transcription

1 The NPN Transistor Bias and Switching Transistor Linear Amplifier Equipment Oscilloscope Function Generator (FG) Bread board 9V Battery and leads Resistors:, 10 kω, Capacitors: ( 2) NPN Transistor Potentiometer Goals of the Experiment To examine the process of finding an optimum D.C. operating point for a transistor amplifier and then to document its gain and its input and out put characteristics. Topics: Biasing, Gain, Operating point, measure output impedance, measure input impedance, measure input impedance, analyse capacitive coupling. Collector Collector 9V R 1 Base A R 2 e b c Emitter i base i collector B

2 Experimental Procedure 1. Effects of D.C. bias and D.C. operating point Construct the circuit seen in Figure 6.1; adjust the potentiometer until the output voltage is 4 volts. Document the bias voltages. Note that yellow/violet/orange/gold, and yellow/violet/red/gold. V base = V DC 9V V bias = V DC V bias V base Figure 6.1: A diagram of the circuit used to measure the effects of D.C. biasing. 2. Measure A.C. gain at this operating point Use a capacitor in order to introduce an input signal without disturbing the bias setting, as seen in Figure 6.2. Set V in to 100 mv peak to peak at 1000 Hz, record, the calculate the gain. = V p p 9V Gain = V in = V in = 100 mv p p 1000 Hz Figure 6.2: A diagram of the circuit used to determine the A.C. gain at this operating point. Note that the battery is always required but not always drawn. Its presence is indicated by the. 2

3 3. Sketch the waveforms V in and in Figure 6.3 CH1 Sensitivity (V/div) CH2 Sensitivity (V/div) Time Base Figure 6.3: Draw the V in and waveforms shown on the oscilloscope. 4. Output impedance estimation Add a 10 kω resistor across as a test load, as seen in Figure 6.4. Document the resulting, and use the change in to calculate the amplifiers equivalent resistance = V p p 10 kω "Test" V in = 100 mv p p 1000 Hz Figure 6.4: A diagram of the circuit used to determine the A.C. gain at this operating point. Note that the battery is always required but not always drawn. Its presence is indicated by the. 3

4 5. Input impedance estimation Remove the 10 kω test resistor from the output, and place it in series with the input signal from the function generator, as shown in Figure 6.5. Document the resulting to calculate the equivalent input resistance of the amplifier. = V p p V in = 100 mv p p 1000 Hz Figure 6.5: A diagram of the circuit used to determine the A.C. gain at this operating point. Note that the battery is always required but not always drawn. Its presence is indicated by the. 4

5 Transistor Logic Gates Equipment Resistors: ( 4), ( 4) 2N3904 NPN transistor ( 4) Green LED (Light Emitting Diode) Push button switches ( 2) Breadboard 9 V battery and leads Goals of the Experiment To examine the minimum circuits required to satisfy first order combinational logic. These are the inverter, and the OR. We verify that we can form the NOR function, which provides both requirements in a single circuit. Using this circuit as a standard module, we form the flip-flop memory cell. Theory Experimental Procedure 1. The inverter demonstrated with a single transistor, test input provided by manual switch Construct the circuit in Figure 6.6a. Document the truth table. Figure 6.6: Inverter circuit (a) Circuit diagram. (b) Truth table. Input Output 1 0 5

6 2. Extend the inverter to a two-input NOR Use a second transistor without disturbing the first, as shown in Figure 6.7a. Document the truth table. Figure 6.7: Two-input NOR gate. (a) Circuit diagram. (b) Above: Truth table. Below: NOR gate symbol. In In Out A B A B 3. By cross-connecting two NOR gates, we form the Set/Reset Flip-Flop. Document the truth table in Figure 6.8a. 6

7 Figure 6.8: Set/reset flip-flop circuit. (a) Circuit diagram. (c) Diagram using NOR gates. (b) Truth table. Reset Out Set Reset Out Set 7

8 8