Dual-Slot PCMCIA Analog Power Controller

Transcription

1 ; Rev. 1; 8/93 Dual-Slot PCMCI nalog Power Controller General Description The provides the power switching and status signals necessary to control two Personal Computer Memory Card International ssociation (PCMCI) Release 2.0 card slots. The, used in conjunction with a PC Card Interface Digital Controller, forms a complete, minimum component count PCMCI interface for palmtop and notebook computers. The incorporates two 0V/+5V/+12V/highimpedance power outputs for flash V PP programming, level shifters for power MOSFET control of two separate +3.3V/+5V supplies, and two V PP power-ready status signals. The may be directly connected to the control outputs from a PCMCI digital controller, or may be configured to use internal edgetriggered registers for connection to the CPU data bus. The has all the features of the but omits the reference and V PP valid indicators. The C has all the features of the but omits the registers for the digital inputs. The D omits the reference, the V PP valid indicators, and the digital input registers. Part Number Reference & V PP Status Indicators Registers for Direct Connection to CPU Data us Dual V PP Switches & Level Shifters for V CC Switching C D +12V +5V Features SSOP Circuit Fits in 0.09in 2 Smallest Complete nalog Controller for Two PCMCI (Release 2.0/JEID 4.1) PC Card Sockets Dual V CC Contols and V PP Outputs Logic-Compatible with Industry-Standard PCMCI Digital Controllers: Intel 82365SL_DF Fujitsu M86301 Chips and Technology F8680 Cirrus Logic CL-PD6720 0V/+5V/+12V/High-Impedance V PP Outputs Internal 1.6Ω V PP Power Switches Dual Voltage 3.3V/5V V CC Operation V PP Power-Ready Status Signals 130µ Quiescent Supply Current (3.5µ in Shutdown) reak-efore-make Switching Ordering Information PRT TEMP. RNGE PIN-PCKGE CNG 0 C to +70 C 24 Narrow Plastic DIP CG 0 C to +70 C 24 SSOP C/D 0 C to +70 C Dice* ENG -40 C to +85 C 24 Narrow Plastic DIP EG -40 C to +85 C 24 SSOP Ordering Information continued on last page. * Contact factory for dice specifications. Typical Operating Circuit +3.3V pplications Notebook and Palmtop Computers Personal Organizers Digital Cameras Handiterminals ar-code Readers VPPIN REF DRV5 VPP +5V +5V V CC PCMCI SLOT V PP #1 V CC PCMCI SLOT V PP #2 C2 DIGITL I/O PCMCI DIGITL CONTROLLER Maxim Integrated Products 1 Call toll free for free samples or literature.

2 SOLUTE MXIMUM RTINGS to... +7V, -0.3V VPPIN to V, -0.3V,, DRV5, to...(vppin + 0.3V), -0.3V, VPP to...(vppin + 0.3V), -0.3V ll Other Pins to...( + 0.3V), -0.3V Continuous Power Dissipation (T = +70 C) 20-Pin Plastic DIP (derate 11.11mW/ C above +70 C)...889mW 20-Pin SSOP (derate 8.00mW/ C above +70 C)...640mW 24-Pin Narrow Plastic DIP (derate mw/ C above +70 C).1067mW 24-Pin SSOP (derate 8.00mW/ C above +70 C)...640mW Operating Temperature Ranges: _C...0 C to +70 C _E C to +85 C Storage Temperature Range C to +160 C Lead Temperature (soldering, 10sec) C Stresses beyond those listed under bsolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICL CHRCTERISTICS ( = +5V, VPPIN = +12V, T = T MIN to T MX, unless otherwise noted.) PRMETER CONDITIONS MIN TYP MX UNITS POWER REQUIREMENTS Input Voltage Range V VPPIN Input Voltage Range V Supply Current 5V mode V or 0V mode 60 µ VPPIN Supply Current VPPIN = 12.6V 12V mode V mode 10 µ Standby Current = 0V, all logic inputs at or µ VPPIN Standby Current = 0V, VPPIN = 4.75V µ DC CHRCTERISTICS, VPP Switch Resistance,,, DRV5 Leakage Current,,, DRV5 Output Voltage Low VOLTGE REFERENCE ( and C only) REF Voltage I LOD = 0µ High-impedance mode 1 50 n I LOD = 1m V REF Temperature Coefficient 20 ppm/ C REF Line Regulation = 2.85V to 5.5V 0.5 mv/v REF Load Regulation I LOD = 0µ to 100µ 2 µv/µ GPI, GPI Power-Ready Threshold GPI, GPI Power-Ready Hysteresis VPPIN = 11.4V, 0m < I LOD < 60m, 12V mode = 4.5V, 0m < I LOD < 1m, 5V mode VPPIN = 11.4V, 0m < I LOD < 1m, 0V mode _C _E _C _E V mode VPPIN 130 VPPIN 0 2 Ω V V mv

3 ELECTRICL CHRCTERISTICS (continued) ( = +5V, VPPIN = +12V, T = T MIN to T MX, unless otherwise noted.) PRMETER CONDITIONS MIN TYP MX UNITS LOGIC SECTION Logic Input Leakage Current 1 µ Logic Input High 2.4 V Logic Input Low 0.8 V GPI, GPI Logic Output High I LOD = 1m V GPI, GPI Logic Output Low I LOD = 1m V TIMING CHRCTERISTICS - and only ( = +3.3V or +5.0V, VPPIN = +12.0V, see Figure 4, T = T MIN to T MX, unless otherwise noted.) PRMETER SYMOL CONDITIONS MIN TYP MX UNITS Pulse Width t L 125 ns _VPP_, _VCC_ Setup Time t S 100 ns _VPP_, _VCC_ Hold Time t H (Note 1) 0 ns _VCC_ to _DRV_ Propagation Delay Note 1: Guaranteed by design, not production tested. 50 ns Typical Operating Characteristics SWITCHING VCC SWITCHING 5V/div 5V/div GPI 5V/div +5V VCC 1V/div +3.3V +12.0V 200mV/div 0V 5µs/div = C2 = 0V, = +5V, CIN = 10µF, C = 0.1µF 2ms/div = +5V, C2 = 0V, = +5V, M1 = M2 = 3055EL, R LOD = 130Ω, C C = 1µF 3

4 Typical Operating Characteristics (continued) SWITCH RESISTNCE (Ω) SWITCH RESISTNCE (12V MODE) = +5.0V, = C2 = = 0V, = +5.0V +125 C +85 C +25 C -55 C SWITCH RESISTNCE (Ω) SWITCH RESISTNCE (5V MODE) -55 C +125 C VPPIN = +12.0V, = C2 = 0V, = = 0V +25 C VPPIN (V) (V) REFERENCE LOD REGULTION REFERENCE VOLTGE vs. TEMPERTURE REF VOLTGE (V) C +125 C +25 C = +5.0V, = +5.0V, VPPIN = +12.0V LOD CURRENT (µ) REFERENCE VOLTGE (V) = +5.0V, = +5.0V, VPPIN = +12.0V TEMPERTURE ( C) 4

5 Pin Description PIN //C D NME 1 C2 FUNCTION Pin-strap input that selects edge-triggered register or direct digital inputs. Tying C2 to makes the logic inputs edge triggered; inputs to pins 4-11 are clocked in on the rising edge of. Tying C2 to allows control signals to be directly applied to the logic inputs on pins Connect to for C Pin-strap input that selects one of two logic decode modes for the digital inputs. See Tables 1-3. Write pulse input. When C2 is tied to, a rising edge on clocks in the V CC and V PP enables. When C2 is tied to, inputs to have no effect. Connect to for C. 4, 5 2, 3, Logic inputs that control the voltage on. 6, 7 4, 5, Logic inputs that control the voltage on VPP. 8, 9 6, 7, Logic inputs that control the state of the MOSFET gate drivers and. 10, 11 8, 9 VC, Logic inputs that control the state of the MOSFET gate drivers and DRV5. 12, 13 10, 11 14, 15 12, 13 DRV5,, Open-drain gate driver outputs that control the MOSFETs that switch the V CC pin of slot to 0V, 3.0V/3.3V, or 5V. Open-drain gate driver outputs that control the MOSFETs that switch the V CC pin of slot to 0V, 3.0V/3.3V, or 5V. 16 GPI 17 GPI Logic-level power-ready output that stays low as long as VPP is greater than 11.05V ( and C only). Make no connection to this pin for. Logic-level power-ready output that stays low as long as is greater than 11.05V ( and C only). Make no connection to this pin for. Logic input that shuts the down to a low supply-current state when brought low. sserting forces,,, DRV5, REF, GPI, and GPI low. ll V PP inputs and outputs are functional for either state of. Program and VPP to 0V for lowest power consumption. 15 N.C. No connect. Not internally connected. 19 REF 1.25V reference voltage output ( and C only). Make no connection to this pin for.) VPP Switched output that provides 0V, 5V, or 12V to the V PP pins of slot Switched output that provides 0V, 5V, or 12V to the V PP pins of slot V power input VPPIN +12V power input. VPPIN can have 0V or 5V applied as long as = 5V Ground 5

6 Table 1. Control Logic V VPPIN High-Z V V VPPIN Table 2. VPP Control Logic VPP V VPPIN High-Z V V VPPIN Table 3. and Control Logic V 0V Hi-Z 0V V Hi-Z V 0V V 0V V 0V V Hi-Z Hi-Z 0V Table 4. and DRV5 Control Logic VC DRV V 0V Hi-Z 0V V Hi-Z V 0V V 0V V 0V V Hi-Z Hi-Z 0V Detailed Description V PP Switching ll four versions (,, C, and D) of the allow simple switching of PCMCI card V PP to 0V, 5V, and 12V. On-chip power MOSFETs connect and VPP to either,, or VPPIN. The and control logic inputs determine the state of. Likewise, and control VPP. To prevent V PP overshoot due to parasitic inductance in the +12V supply, the VPPIN bypass capacitor (C IN ) should be 10 times greater than the capacitance from (C ) or VPP (C ) to. Hence, when C and C are 0.1µF, C IN should be 1.0µF. The GPI and GPI status outputs signal when the V PP lines are valid. GPI goes low when exceeds 11.05V; GPI goes low when VPP exceeds 11.05V. The status outputs and the reference are only active when is high. Pulling low puts the into a low supplycurrent mode and disables the reference and the GPI and GPI status outputs. The V CC level shifters,, DRV5, are all forced low when is low. V PP switching is not affected by the state of. Program and VPP to 0V for lowest power consumption when is low. Wait at least 200µs after bringing the out of shutdown before checking GPI or GPI since the reference needs time to stabilize. V CC Switching The contains level shifters that simplify driving external power MOSFETs to switch PCMCI card V CC to 3.3V and 5V. While a PCMCI card is being inserted into the socket, the V CC pins on the card edge connector should be powered down to 0V so that hot insertion does not damage the PCMCI card. The simplest way to accomplish this is to pull out a mechanical switch before the PCMCI card is inserted. The mechanical switch can be pushed in only when the card has been fitted snugly into its socket. The Detailed Operating Circuit shows this method. In the Detailed Operating Circuit, (with the mechanical interlock switch closed) the PCMCI card V CC cannot be pulled more than a diode drop below 3.3V. The N- channel power MOSFET that connects V CC to 3.3V has its drain tied to V CC and its source tied to 3.3V, so that its body diode prevents the card s V CC from falling to 0V. If it were rotated so that the source connected to V CC, then applying 5V to V CC would short the 5V supply to the 3.3V supply via the MOSFET s body diode. 6

7 If a mechanical interlock switch cannot be used, an extra MOSFET must be added, as shown in Figure 1. Placing two N-channel MOSFETs in series with their body diodes facing in opposite directions allows V CC to be shut down to 0V without using a mechanical switch. Switching Speed The drive to the external MOSFETs ensures that the 3.3V supply is never connected to the 5V supply. This is done by turning these transistors off quickly (using active pull-down circuitry), and on more slowly (using external pull-up resistors). The turn-on delay depends on the value of the pull-up resistors, and on the gate capacitance of the switching transistors. To save power, use high-value resistors of up to 10MΩ. However, note that high-value resistors will increase the time it takes to turn on the switched supplies pplications Information The can be used with PCMCI controllers other than the Intel 82365SL DF. Figure 2 shows the logic connections to the Cirrus Logic CL-PD6720 PCMCI Host dapter. The does not need a PCMCI controller to function. Tie C2 to to allow direct V CC and V PP control from the system bus. Figure 3 shows the connection to the system bus. Figure 4 shows the timing requirements. Reading from a PCMCI Port without Using the V PP Supply In the Typical Operating Circuit, V CC is switched to the PCMCI ports using the 12V V PP supply, which provides the gate drive needed to turn on the external N-channel MOSFETs. In some cases, the high-power V PP supply is only available when information has to be written to the PCMCI port, not when data is being read. The V PP supply may have a quiescent current of several milliamps, so it consumes more power than is necessary simply to provide gate drive for some FETs. In these circumstances, a separate gate-drive supply is needed to turn on the external FETs. Ideally it should have a low quiescent current and be capable of being turned off when read access to the PCMCI port is not required. Doubling or tripling charge pumps can easily be built using a convenient clock signal from elsewhere in the system. uffering the clock signal with a suitable gate provides on/off control, as shown in Figure 5. When driven at Hz or more by a CMOS gate powered from 5V, the doubler circuit outputs 8.6V when loaded with 25kΩ (equivalent to four Ω pull-up resistors). Under similar conditions, but when running from 3.3V, the tripler circuit produces 7.9V. _ DRV5 +12V +12V +12V +12V * +5V * EXTR MOSFET +3.3V NOTE: ODY DIODES OF MOSFETS SHOWN FOR CLRITY. * VCC 1µF VCC 1µF Figure 1. Using an Extra MOSFET to Replace the Mechanical Interlock 7

8 C2 _ VC GPI GPI _VPP_PGM _VPP_VCC _-VCC_3 _-VCC_5 _VPP_PGM _VPP_VCC _-VCC_3 _-VCC_5 VPP_VLID CIRRUS LOGIC CL-PD6720 _VPP_, _VCC_ t L t S t H Figure 2. Logic Connections to CL-PD6720 Figure 4. C2 = Mode Timing +5V C2 _ VC DT US D0 D1 D2 D3 D4 D5 D6 D7 CLOCK ON/OFF CLOCK ON/OFF +5V 10nF 10nF 10nF 0.1µF GTE-DRIVE SUPPLY OUTPUT GTE-DRIVE SUPPLY OUTPUT 0.1µF DDRESS DECODE DDRESS US 3.3V LL DIODES 1N µF Figure 3. Direct Connection to System us Figure 5. lternative Gate-Drive Charge-Pump Supplies 8

9 Dual-Slot PCMCI nalog Power Controller VPPIN VPP N.C. N.C. N.C. C2 VC DRV5 DIP/SSOP VPPIN VPP REF GPI GPI VC DRV5 C DIP/SSOP VPPIN VPP N.C. VC DRV5 D DIP/SSOP TOP VIEW Pin Configurations (continued) VPPIN VPP REF GPI GPI C2 VC DRV5 DIP/SSOP

10 Detailed Operating Circuit +12V +5V +3.3V C IN VPPIN 0.1µF M1 M2 MECHNICL INTERLOCK REF C C V CC VPP1 VPP2 PCMCI CONNECTOR C2 DRV5 C C D V CC VPP1 VPP2 PCMCI CONNECTOR VPP C VC GPI :VCC_EN0 :VCC_EN1 :VPP_EN0 :VPP_EN1 INTEL 82365SL DF* :VCC_EN0 :VCC_EN1 :VPP_EN0 :VPP_EN1 :GPI GPI :GPI CS SHUTDOWN SIGNL FROM CPU *MODE = 0, INTERNL DDRESS DECODING 10

11 Ordering Information (continued) PRT TEMP. RNGE PIN-PCKGE CNG 0 C to +70 C 24 Narrow Plastic DIP CG 0 C to +70 C 24 SSOP C/D 0 C to +70 C Dice* ENG -40 C to +85 C 24 Narrow Plastic DIP EG -40 C to +85 C 24 SSOP CCNG 0 C to +70 C 24 Narrow Plastic DIP CCG 0 C to +70 C 24 SSOP CC/D 0 C to +70 C Dice* CENG -40 C to +85 C 24 Narrow Plastic DIP CEG -40 C to +85 C 24 SSOP DCPP 0 C to +70 C 20 Plastic DIP DCP 0 C to +70 C 20 SSOP DC/D 0 C to +70 C Dice* DEPP -40 C to +85 C 20 Plastic DIP DEP -40 C to +85 C 20 SSOP * Contact factory for dice specifications. Chip Topography C2 VPPIN VC DRV5 VPP 0.111" (2.819mm) REF GPI GPI 0.085" (2.159mm) Package Information L 2 1 D1 e D 1 3 α E E1 e e DIM C D D1 E E1 e e e L α C MIN INCHES MX SC SC MILLIMETERS MIN MX SC 7.62 SC PIN PLSTIC DUL-IN-LINE (NRROW) PCKGE 11

12 Package Information (continued) E H DIM 1 C D E e H L α MIN INCHES MX SC MILLIMETERS MIN MX SC e D mm 0.004in. C L α 24-PIN PLSTIC SHRINK SMLL-OUTLINE PCKGE L 2 1 D1 e D 1 3 α E E1 e e C DIM C D D1 E E1 e e e L α MIN INCHES MX SC SC MILLIMETERS MIN MX SC 7.62 SC PIN PLSTIC DUL-IN-LINE PCKGE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, C (408) Maxim Integrated Products Printed US is a registered trademark of Maxim Integrated Products.