Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator ADG3304

Transcription

1 Low Voltage,.5 V to 5.5 V, -Channel, Bidirectional Logic Level Translator FETURES Bidirectional level translation Operates from.5 V to 5.5 V Low quiescent current < 5 µ No direction pin Qualified for automotive applications PPLICTIONS SPI, MICROWIRE level translation Low voltage SIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SN/NS) Computing/server applications GPS Portable POS systems Low cost serial interfaces GERL DESCRIPTION The is a bidirectional logic level translator that contains four bidirectional channels. It can be used in multivoltage digital system applications, such as data transfer, between a low voltage digital signal processing controller and a higher voltage device using SPI and MICROWIRE interfaces. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to VCC sets the logic levels on the side of the device, while VCCY sets the levels on the Y side. For proper operation, VCC must always be less than VCCY. The VCC-compatible logic signals applied to the side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCcompatible logic levels on the side. 3 FUNCTIONL BLOCK DIGRM Figure. The enable pin () provides three-state operation on both the side and the Y side pins. When the pin is pulled low, the terminals on both sides of the device are in the high impedance state. The pin is referred to the VCC supply voltage and driven high for normal operation. The is available in compact -lead TSSOP, -ball WLCSP, and -lead LFCSP. It is guaranteed to operate over the.5 V to 5.5 V supply voltage range. PRODUCT HIGHLIGHTS. Bidirectional level translation.. Fully guaranteed over the.5 V to 5.5 V supply range. 3. No direction pin.. vailable in -lead TSSOP, -ball WLCSP, and -lead LFCSP. Y Y Y3 Y - Rev. D Document Feedback Information furnished by nalog Devices is believed to be accurate and reliable. However, no responsibility is assumed by nalog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of nalog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, M -9, U.S.. Tel: nalog Devices, Inc. ll rights reserved. Technical Support

2 TBLE OF CONTTS Features... pplications... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... 3 bsolute Maximum Ratings... ESD Caution... Pin Configurations and Function Descriptions... 7 Typical Performance Characteristics... Test Circuits... Theory of Operation... Level Translator rchitecture... Input Driving Requirements... Output Load Requirements... Enable Operation... Power Supplies... Data Rate... 7 pplications... Layout Guidelines... Outline Dimensions... 9 Ordering Guide... utomotive Products... Terminology... 5 REVISION HISTORY /3 Rev. C to Rev. D Changes to Figure 3 and Table... 7 / Rev. B to Rev. C Changes to Table... 3 Changes to Table... Changes to VCCY Description, Table 3 and Table... 7 Changes to Ordering Guide... dded utomotive Products Section... /5 Rev. to Rev. B Changes to Table... 3 Changes to Table... Changes to Figure 3 and Table... 7 Updated Outline Dimensions... 9 Changes to Ordering Guide... /5 Rev. to Rev. dded LFCSP Package... Universal /5 Revision : Initial Version Rev. D Page of

3 SPECIFICTIONS VCCY =.5 V to 5.5 V, VCC =.5 V to VCCY, = V, T = 5 C. ll specifications TMIN to TMX, unless otherwise noted. Table. B Version Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS/OUTPUTS Side Input High Voltage VIH VCC =. V +. V/.5 V VCC. V VCC =. V ±.5 V VCC.7 V VCC =.5 V ±. V.7 V VCC = 3.3 V ±.3 V. V VCC = 5 V ±.5 V VCC.7 V Input Low Voltage VIL VCC =. V +. V/.5 V VCC.35 V VCC =. V ±.5 V VCC.35 V VCC =.5 V ±. V.7 V VCC = 3.3 V ±.3 V. V VCC = 5 V ±.5 V VCC.3 V Output High Voltage VOH VY = VCCY, IOH = µ, see Figure 9 VCC. V Output Low Voltage VOL VY = V, IOL = µ, see Figure 9. V Capacitance C f = MHz, =, see Figure 3 9 pf Leakage Current IL, Hi-Z V = V/VCC, =, see Figure 3 ± µ Y Side Input High Voltage VIHY VCCY =. V ±.5 V VCCY.7 V VCCY =.5 V ±. V.7 V VCCY = 3.3 V ±.3 V V VCCY = 5 V ±.5 V VCCY.7 V Input Low Voltage VILY VCCY =. V ±.5 V VCCY.35 V VCCY =.5 V ±. V.7 V VCCY = 3.3 V ±.3 V. V VCCY = 5 V ±.5 V VCCY.5 V Output High Voltage VOHY V = VCC, IOH = µ, see Figure 3 VCCY. V Output Low Voltage VOLY V = V, IOL = µ, see Figure 3. V Capacitance CY f = MHz, =, see Figure 35 pf Leakage Current ILY, Hi-Z VY = V/VCCY, =, see Figure 3 ± µ Enable () Input High Voltage VIH VCC =. V +. V/.5 V VCC. V VCC =. V ±.5 V VCC.7 V VCC =.5 V ±. V.7 V VCC = 3.3 V ±.3 V. V VCC = 5 V ±.5 V VCC.7 V Input Low Voltage VIL VCC =. V +. V/.5 V VCC.35 V VCC =. V ±.5 V VCC.35 V VCC =.5 V ±. V.7 V VCC = 3.3 V ±.3 V. V VCC = 5 V ±.5 V VCC.3 V Leakage Current IL V = V/VCC, V = V, see Figure 33 ± µ Capacitance C 3 pf Enable Time t RS = RT = 5 Ω, V = V/VCC ( Y), VY = V/VCCY (Y ), see Figure 3. µs Rev. D Page 3 of

4 B Version Parameter Symbol Test Conditions/Comments Min Typ Max Unit SWITCHING CHRCTERISTICS 3.3 V ±.3 V VCC VCCY, VCCY = 5 V ±.5 V Y Level Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 37 Propagation Delay tp, Y ns Rise Time tr, Y 3.5 ns Fall Time tf, Y 3.5 ns Maximum Data Rate DMX, Y 5 Mbps Channel-to-Channel Skew tskew, Y ns Part-to-Part Skew tppskew, Y 3 ns Y Level Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, Y 7 ns Rise Time tr, Y 3 ns Fall Time tf, Y 3 7 ns Maximum Data Rate DMX, Y 5 Mbps Channel-to-Channel Skew tskew, Y 3.5 ns Part-to-Part Skew tppskew, Y ns. V ±.5 V VCC VCCY, VCCY = 3.3 V ±.3 V Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 37 Propagation Delay tp, Y ns Rise Time tr, Y 5 ns Fall Time tf, Y 5 ns Maximum Data Rate DMX, Y 5 Mbps Channel-to-Channel Skew tskew, Y ns Part-to-Part Skew tppskew, Y ns Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, Y 5 ns Rise Time tr, Y 3.5 ns Fall Time tf, Y 3.5 ns Maximum Data Rate DMX, Y 5 Mbps Channel-to-Channel Skew tskew, Y 3 ns Part-to-Part Skew tppskew, Y 3 ns.5 V to.3 V VCC VCCY, VCCY = 3.3 V ±.3 V Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 37 Propagation Delay tp, Y 9 ns Rise Time tr, Y 3 5 ns Fall Time tf, Y 5 ns Maximum Data Rate DMX, Y Mbps Channel-to-Channel Skew tskew, Y 5 ns Part-to-Part Skew tppskew, Y ns Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, Y 5 9 ns Rise Time tr, Y ns Fall Time tf, Y ns Maximum Data Rate DMX, Y Mbps Channel-to-Channel Skew tskew, Y ns Part-to-Part Skew tppskew, Y ns Rev. D Page of

5 B Version Parameter Symbol Test Conditions/Comments Min Typ Max Unit.5 V to.3 V VCC VCCY, VCCY =. V ±.3 V Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 37 Propagation Delay tp, Y 5 ns Rise Time tr, Y 7 ns Fall Time tf, Y 3 5 ns Maximum Data Rate DMX, Y 5 Mbps Channel-to-Channel Skew tskew, Y 5 ns Part-to-Part Skew tppskew, Y 5 ns Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, Y 35 ns Rise Time tr, Y 5 ns Fall Time tf, Y.5.5 ns Maximum Data Rate DMX, Y 5 Mbps Channel-to-Channel Skew tskew, Y 3.5 ns Part-to-Part Skew tppskew, Y 3.5 ns.5 V ±. V VCC VCCY, VCCY = 3.3 V ±.3 V Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 37 Propagation Delay tp, Y 7 ns Rise Time tr, Y.5 ns Fall Time tf, Y 5 ns Maximum Data Rate DMX, Y Mbps Channel-to-Channel Skew tskew, Y.5 ns Part-to-Part Skew tppskew, Y ns Y Translation RS = RT = 5 Ω, CL = 5 pf, see Figure 3 Propagation Delay tp, Y 5 ns Rise Time tr, Y ns Fall Time tf, Y 3 5 ns Maximum Data Rate DMX, Y Mbps Channel-to-Channel Skew tskew, Y 3 ns Part-to-Part Skew tppskew, Y 3 ns POWER REQUIREMTS Power Supply Voltages VCC VCC VCCY V VCCY V Quiescent Power Supply Current ICC V = V/VCC, VY = V/VCCY,.7 5 µ VCC = VCCY = 5.5 V, = ICCY V = V/VCC, VY = V/VCCY,.7 5 µ VCC = VCCY = 5.5 V, = Three-State Mode Power Supply Current IHi-Z, VCC = VCCY = 5.5 V, =. 5 µ IHi-Z, Y VCC = VCCY = 5.5 V, =. 5 µ T for typical specifications is 5 C. Guaranteed by design, not production tested. Rev. D Page 5 of

6 BSOLUTE MXIMUM RTINGS T = 5 C, unless otherwise noted. Table. Parameter Rating VCC to.3 V to +7 V VCCY to VCC to +7 V Digital Inputs ().3 V to (VCC +.3 V) Digital Inputs (Y).3 V to (VCCY +.3 V) to.3 V to +7 V Operating Temperature Range C to +5 C Storage Temperature Range 5 C to +5 C Junction Temperature 5 C θj Thermal Impedance (-Layer Board) -Lead TSSOP 9. C/W -Ball WLCSP C/W -Lead LFCSP 3. C/W Lead Temperature, Soldering s per JEDEC J-STD- Stresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CUTION Rev. D Page of

7 NC NC 9 NC Y PIN CONFIGURTIONS ND FUNCTION DESCRIPTIONS BLL INDICTOR NC 3 NC TOP VIEW (Not to Scale) NC = NO CONNECT 3 Figure. -Lead TSSOP Pin Configuration 9 Y Y Y3 Y NC - B C D 3 Y Y Y3 Y 3 TOP VIEW (BLLS T THE BOTTOM) Not to Scale Figure 3. -Ball WLCSP Pin Configuration -3 NC 3 3 NC 5 PIN INDICTOR TOP VIEW (Not to Scale) 5 NC Y 3 Y3 Y NC NC = NO CONNECT NOTES. THE EXPOSED PDDLE CN BE TIED TO OR LEFT FLOTING. DO NOT TIE IT TO or. Figure. -Lead LFCSP_VQ Pin Configuration -57 Table 3. -Lead TSSOP and -lead LFCSP Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 9 VCC Power Supply Voltage Input for the to I/O Pins (.5 V VCC VCCY). Input/Output. Referenced to VCC. 3 Input/Output. Referenced to VCC. 3 3 Input/Output 3. Referenced to VCC. 5 Input/Output. Referenced to VCC., 9, 5,, 7,,, 5, NC No Connect. 7 Ground. 9 ctive High Enable Input. Y Input/Output Y. Referenced to VCCY. 3 Y3 Input/Output Y3. Referenced to VCCY. Y Input/Output Y. Referenced to VCCY. 3 7 Y Input/Output Y. Referenced to VCCY. VCCY Power Supply Voltage Input for the Y to Y I/O Pins (.5 V VCCY 5.5 V). Table. -Ball WLCSP Pin Function Descriptions Bump No. Mnemonic Description Y Input/Output Y. Referenced to VCCY. B Y Input/Output Y. Referenced to VCCY. C Y3 Input/Output Y3. Referenced to VCCY. D Y Input/Output Y. Referenced to VCCY. VCCY Power Supply Voltage Input for the Y to Y I/O Pins (.5 V VCCY 5.5 V). B VCC Power Supply Voltage Input for the to I/O Pins (.5 V VCC VCCY). C ctive High Enable Input. D Ground. 3 Input/Output. Referenced to VCC. B3 Input/Output. Referenced to VCC. C3 3 Input/Output 3. Referenced to VCC. D3 Input/Output. Referenced to VCC. Rev. D Page 7 of

8 TYPICL PERFORMNCE CHRCTERISTICS I CC (m) C L = 5pF = 3.3V, = 5V =.V, = 3.3V I CCY (m) C L = 5pF = 3.3V, = 5V.. =.V, =.V DT RTE (Mbps) -.5 =.V, =.V DT RTE (Mbps) =.V, = 3.3V -7 Figure 5. ICC vs. Data Rate ( Y Level Translation) Figure. ICCY vs. Data Rate (Y Level Translation) I CCY (m) C L = 5pF = 3.3V, = 5V =.V, = 3.3V =.V, =.V DT RTE (Mbps) -5 I CCY (m) =.V =.V Mbps Mbps 5Mbps Mbps CPCITIVE LOD (pf) - Figure. ICCY vs. Data Rate ( Y Level Translation) Figure 9. ICCY vs. Capacitive Load at Pin Y for Y (. V. V) Level Translation C L = 5pF = 3.3V, = 5V =.V =.V I CC (m) DT RTE (Mbps) =.V, = 3.3V =.V, =.V - I CC (m) Mbps Mbps 5Mbps Mbps CPCITIVE LOD (pf) -3 Figure 7. ICC vs. Data Rate (Y Level Translation) Figure. ICC vs. Capacitive Load at Pin for Y (. V. V) Level Translation Rev. D Page of

9 9 7 =.V = 3.3V 5Mbps 7 5 = 3.3V = 5V 5Mbps I CCY (m) 5 3Mbps 3 Mbps Mbps 5Mbps CPCITIVE LOD (pf) 5- I CC (m) 3Mbps 3 Mbps Mbps 5Mbps CPCITIVE LOD (pf) - Figure. ICCY vs. Capacitive Load at Pin Y for Y (. V 3.3 V) Level Translation Figure. ICC vs. Capacitive Load at Pin for Y (5 V 3.3 V) Level Translation =.V = 3.3V 9 DT RTE = 5kbps =.V, =.V I CC (m) Mbps CPCITIVE LOD (pf) 5Mbps 3Mbps Mbps Mbps Figure. ICC vs. Capacitive Load at Pin for Y (3.3 V. V) Level Translation -7 RISE TIME (ns) =.V, = 3.3V = 3.3V, = 5V CPCITIVE LOD (pf) Figure 5. Rise Time vs. Capacitive Load at Pin Y ( Y Level Translation) -3 = 3.3V = 5V 5Mbps DT RTE = 5kbps =.V, =.V I CCY (m) 3Mbps Mbps Mbps FLL TIME (ns) =.V, = 3.3V = 3.3V, = 5V 5Mbps CPCITIVE LOD (pf) CPCITIVE LOD (pf) - Figure 3. ICCY vs. Capacitive Load at Pin Y for Y (3.3 V 5 V) Level Translation Figure. Fall Time vs. Capacitive Load at Pin Y ( Y Level Translation) Rev. D Page 9 of

10 RISE TIME (ns) DT RTE = 5kbps =.V, =.V CPCITIVE LOD (pf) =.V, = 3.3V = 3.3V, = 5V -5 PROPGTION DELY (ns) DT RTE = 5kbps T = 5 C CPCITIVE LOD (pf) =.V, =.V =.V, = 3.3V = 3.3V, = 5V - Figure 7. Rise Time vs. Capacitive Load at Pin (Y Level Translation) Figure. Propagation Delay (tphl) vs. Capacitive Load at Pin Y ( Y Level Translation). 3.5 DT RTE = 5kbps 9 DT RTE = 5kbps FLL TIME (ns) =.V, =.V =.V, = 3.3V = 3.3V, = 5V PROPGTION DELY (ns) =.V, = 3.3V =.V, =.V.5 = 3.3V, = 5V CPCITIVE LOD (pf) CPCITIVE LOD (pf) -9 Figure. Fall Time vs. Capacitive Load at Pin (Y Level Translation) Figure. Propagation Delay (tplh) vs. Capacitive Load at Pin (Y Level Translation) PROPGTION DELY (ns) DT RTE = 5kbps =.V, = 3.3V =.V, =.V = 3.3V, = 5V PROPGTION DELY (ns) DT RTE = 5kbps =.V, = 3.3V =.V, =.V = 3.3V, = 5V CPCITIVE LOD (pf) CPCITIVE LOD (pf) -3 Figure 9. Propagation Delay (tplh) vs. Capacitive Load at Pin Y ( Y Level Translation) Figure. Propagation Delay (tphl) vs. Capacitive Load at Pin (Y Level Translation) Rev. D Page of

11 DT RTE = 5Mbps C L = 5pF DT RTE = 5Mbps C L = 5pF mv/div 5ns/DIV -37 mv/div 3ns/DIV - Figure 3. Eye Diagram at Y Output (. V to. V Level Translation, 5 Mbps) Figure. Eye Diagram at Output (3.3 V to. V Level Translation, 5 Mbps) DT RTE = 5Mbps C L = 5pF DT RTE = 5Mbps CL = 5pF mv/div 5ns/DIV -3 V/DIV 3ns/DIV - Figure. Eye Diagram at Output (. V to. V Level Translation, 5 Mbps) Figure 7. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 5 Mbps) DT RTE = 5Mbps C L = 5pF DT RTE = 5Mbps C L = 5pF 5mV/DIV 3ns/DIV -39 mv/div 3ns/DIV - Figure 5. Eye Diagram at Y Output (. V to 3.3 V Level Translation, 5 Mbps) Figure. Eye Diagram at Output (5 V to 3.3 V Level Translation, 5 Mbps) Rev. D Page of

12 TEST CIRCUITS.µF.µF Y K.µF.µF K Y K I OH I OL -3 - Figure 9. VOH/VOL Voltages at Pin Figure 3. Three-State Leakage Current at Pin Y.µF.µF K Y.µF.µF K Y I OH I OL K - Figure 3. VOH/VOL Voltages at Pin Y.µF.µF K Y -5-7 Figure 33. Pin Leakage Current CPCITNCE METER Y - Figure 3. Three-State Leakage Current at Pin Figure 3. Capacitance at Pin Rev. D Page of

13 Y Y Figure 35. Capacitance at Pin Y CPCITNCE METER -9 Y DIRECTION. F + F. F + F M SIGNL SOURCE K V Y 5pF V Y K M R S Z = 5 V 5 RT 5 Y DIRECTION. F + F. F + F M SIGNL SOURCE K M V 5pF V Y K R S Z = 5 V 5 RT 5 V V /V Y 9% V Y /V t V / V / V V V /V Y t V / V Y /V % NOTES. t IS WHICHEVER IS LRGER BETWE t ND t IN BOTH Y ND Y DIRECTIONS. Figure 3. Enable Time V / V -5 Rev. D Page 3 of

14 Y Y SIGNL SOURCE +.µf µf +.µf µf +.µf µf +.µf µf SIGNL SOURCE R S Z = 5Ω V V Y V V Y Z = 5Ω R S 5Ω R T 5Ω 5pF 5pF R T 5Ω 5Ω V V Y 5% 5% 9% 5% % V Y t P, Y t F, Y t P, Y t R, Y Figure 37. Switching Characteristics ( Y Level Translation) -5 9% 5% % V t P,Y t F,Y t P,Y t R,Y Figure 3. Switching Characteristics (Y Level Translation) -5 Rev. D Page of

15 TERMINOLOGY VIH Logic input high voltage at Pin to Pin. VIL Logic input low voltage at Pin to Pin. VOH Logic output high voltage at Pin to Pin. VOL Logic output low voltage at Pin to Pin. C Capacitance measured at Pin to Pin ( = ). IL, Hi-Z Leakage current at Pin to Pin when = (high impedance state at Pin to Pin ). VIHY Logic input high voltage at Pin Y to Pin Y. VILY Logic input low voltage at Pin Y to Pin Y. VOHY Logic output high voltage at Pin Y to Pin Y. VOLY Logic output low voltage at Pin Y to Pin Y. CY Capacitance measured at Pin Y to Pin Y ( = ). ILY, Hi-Z Leakage current at Pin Y to Pin Y when = (high impedance state at Pin Y to Pin Y). VIH Logic input high voltage at the pin. VIL Logic input low voltage at the pin. C Capacitance measured at pin. IL Enable () pin leakage current. t Three-state enable time for Pin to Pin and Pin Y to Pin Y. tp, Y Propagation delay when translating logic levels in the Y direction. tr, Y Rise time when translating logic levels in the Y direction. TF, Y Fall time when translating logic levels in the Y direction. DMX, Y Guaranteed data rate when translating logic levels in the Y direction under the driving and loading conditions specified in Table. TSKEW, Y Difference between propagation delays on any two channels when translating logic levels in the Y direction. tppskew, Y Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the Y direction. tp, Y Propagation delay when translating logic levels in the Y direction. tr, Y Rise time when translating logic levels in the Y direction. tf, Y Fall time when translating logic levels in the Y direction. DMX, Y Guaranteed data rate when translating logic levels in the Y direction under the driving and loading conditions specified in Table. tskew, Y Difference between propagation delays on any two channels when translating logic levels in the Y direction. tppskew, Y Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the Y direction. VCC VCC supply voltage. VCCY VCCY supply voltage. ICC VCC supply current. ICCY VCCY supply current. IHi-Z, VCC supply current during three-state mode ( = ). IHi-Z, Y VCCY supply current during three-state mode ( = ). Rev. D Page 5 of

16 THEORY OF OPERTION The level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCC and VCCY (VCC VCCY). These supplies set the logic levels on each side of the device. When driving the pins, the device translates the VCC-compatible logic levels to VCCY-compatible logic levels available at the Y pins. Similarly, because the device is capable of bidirectional translation, when driving the Y pins, the VCCYcompatible logic levels are translated to VCC-compatible logic levels available at the pins. When =, Pin to Pin and Pin Y to Pin Y are three-stated. When is driven high, the goes into normal operation mode and performs level translation. LEVEL TRNSLTOR RCHITECTURE The consists of four bidirectional channels. Each channel can translate logic levels in either the Y or the Y direction. It uses a one-shot accelerator architecture, which ensures excellent switching characteristics. Figure 39 shows a simplified block diagram of a bidirectional channel. T T kω U kω P ONE-SHOT GERTOR N U U U3 Figure 39. Simplified Block Diagram of an Channel The logic level translation in the Y direction is performed using a level translator (U) and an inverter (U), while the translation in the Y direction is performed using Inverter U3 and Inverter U. The one-shot generator detects a rising or falling edge present on either the side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T to T) for a rising edge, or the NMOS transistors (T3 to T) for a falling edge. This charges/discharges the capacitive load faster, which results in faster rise and fall times. T T3 Y -53 INPUT DRIVING REQUIREMTS To ensure correct operation of the, the circuit that drives the input of the channels should have an output impedance of less than or equal to 5 Ω and a minimum peak current driving capability of 3 m. OUTPUT LOD REQUIREMTS The level translator is designed to drive CMOScompatible loads. If current-driving capability is required, it is recommended to use buffers between the outputs and the load. BLE OPERTION The provides three-state operation at the and Y I/O pins by using the enable pin (), as shown in Table 5. Table 5. Truth Table Y I/O Pins I/O Pins Hi-Z Hi-Z Normal operation Normal operation High impedance state. In normal operation, the performs level translation. While =, the enters into three-state mode. In this mode, the current consumption from both the VCC and VCCY supplies is reduced, allowing the user to save power, which is critical, especially on battery-operated systems. The input pin can be driven with either VCC-compatible or VCCY-compatible logic levels. POWER SUPPLIES For proper operation of the, the voltage applied to the VCC must be less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCC. The operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where, during power-up, VCC can be greater than VCCY due to a significant increase in the current taken from the VCC supply. For optimum performance, the VCC pin and VCCY pin should be decoupled to as close as possible to the device. The inputs of the unused channels ( or Y) should be tied to their corresponding VCC rail (VCC or VCCY) or to. Rev. D Page of

17 DT RTE The maximum data rate at which the device is guaranteed to operate is a function of the VCC and VCCY supply voltage combination and the load capacitance. It is given by the maximum frequency of a square wave that can be applied to the device, which meets the VOH and VOL levels at the output and does not exceed the maximum junction temperature (see the bsolute Maximum Ratings section). Table shows the guaranteed data rates at which the can operate in both directions ( Y or Y level translation) for various VCC and VCCY supply combinations. Table. Guaranteed Data Rate (Mbps). V.5 V 3.3 V 5 V VCC (.5 V to.95 V) (.3 V to.7 V) (3. V to 3. V) (.5 V to 5.5 V). V (.5 V to.3 V) 5 3. V (.5 V to.95 V) V (.3 V to.7 V) V (3. V to 3. V) V (.5 V to 5.5 V) The load capacitance used is 5 pf when translating in the Y direction and 5 pf when translating in the Y direction. VCCY Rev. D Page 7 of

18 PPLICTIONS The is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the pins, and the higher voltage logic signals are connected to the Y pins. The can provide level translation in both directions from Y or Y on all four channels, eliminating the need for a level translator IC for each direction. The internal architecture allows the to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. It also allows simultaneous data flow in both directions on the same part, for example, when two channels translate in Y direction while the other two translate in Y direction. This simplifies the design by eliminating the timing requirements for the direction signal and reducing the number of ICs used for level translation. Figure shows an application where two microprocessors operating at. V and 3.3 V, respectively, can transfer data simultaneously using two full-duplex serial links, TX/RX and TX/RX. nf nf MICROPROCESSOR/ MICROCONTROLLER/ DSP.V 3.3V I/O L Y I/O H I/O L Y I/O H I/O L3 I/O L CS nf nf 3 Y3 Y Y Y 3 Y3 Y nf nf I/O H3 I/O H I/O H I/O H I/O H3 I/O H Figure.. V to 3.3 V Level Translation Circuit Using the Three-State Feature PERIPHERL DEVICE 3.3V PERIPHERL DEVICE -55 MICROPROCESSOR/ MICROCONTROLLER/ DSP.V 3.3V TX Y RX RX TX RX 3 Y Y3 Y TX MICROPROCESSOR/ MICROCONTROLLER/ DSP RX TX Figure.. V to 3.3 V Level Translation Circuit on Two Full-Duplex Serial Links When the application requires level translation between a microprocessor and multiple peripheral devices, the I/O pins can be three-stated by setting =. This feature allows the to share the data buses with other devices without causing contention issues. Figure shows an application where a. V microprocessor is connected to a 3.3 V peripheral device using the three-state feature. -5 LYOUT GUIDELINES s with any high speed digital IC, the printed circuit board layout is important for the overall performance of the circuit. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCC and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCC pin and the VCCY pin. The parasitic inductance of the high speed signal track may cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. solid copper plane for the return path () is also recommended. Rev. D Page of

19 OUTLINE DIMSIONS BSC 7 PIN BSC COPLNRITY.9.. MX SETING PLNE..9 COMPLINT TO JEDEC STNDRDS MO-53-B- Figure. -Lead Thin Shrink Small Outline Package [TSSOP] (RU-) Dimensions shown in millimeters BOTTOM VIEW (BLL SIDE UP) 3 BLL IDTIFIER REF B C TOP VIEW (BLL SIDE DOWN) D VIEW BSC COPLNRITY D. REF SETING PLNE Figure 3. -Ball Wafer Level Chip Scale Package [WLCSP] (CB--) Dimensions shown in millimeters 9--- Rev. D Page 9 of

20 ORDERING GUIDE PIN INDICTOR..5. SETING PLNE.. SQ 3.9 TOP VIEW MX. MX.5 TYP BCS SQ. MX.5 BSC MX. NOM COPLNRITY.. REF. MX COMPLINT TOJEDEC STNDRDS MO--VGGD- 5 EXPOSED PD 5 BOTTOM VIEW PIN INDICTOR.5. SQ.95.5 MIN FOR PROPER CONNECTION OF THE EXPOSED PD, REFER TO THE PIN CONFIGURTION ND FUNCTION DESCRIPTIONS SECTION OF THIS DT SHEET. Figure. -Lead Lead Frame Chip Scale Package [LFCSP_VQ] mm mm Body, Very Thin Quad (CP--) Dimensions shown in millimeters Model, Temperature Range Package Description Branding 3 Option Package BRUZ C to +5 C -Lead Thin Shrink Small Outline Package [TSSOP] RU- BRUZ-REEL C to +5 C -Lead Thin Shrink Small Outline Package [TSSOP] RU- BRUZ-REEL7 C to +5 C -Lead Thin Shrink Small Outline Package [TSSOP] RU- BCPZ-REEL C to +5 C -Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-- BCPZ-REEL7 C to +5 C -Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-- BCBZ-REEL C to +5 C -Ball Wafer Level Chip Scale Package [WLCSP] SDC CB-- BCBZ-REEL7 C to +5 C -Ball Wafer Level Chip Scale Package [WLCSP] SDC CB-- WBRUZ-REEL C to +5 C -Lead Thin Shrink Small Outline Package [TSSOP] RU- Z = RoHS Compliant Part. W = Qualified for utomotive pplications. 3 Branding on these packages is limited to three characters due to space constraints. -9--B UTOMOTIVE PRODUCTS The W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local nalog Devices account representative for specific product ordering information and to obtain the specific utomotive Reliability reports for these models. 5 3 nalog Devices, Inc. ll rights reserved. Trademarks and registered trademarks are the property of their respective owners. D--/3(D) Rev. D Page of