Expanding the Role of Fan- in and FO- WLP: Technology and Infrastructure Developments
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1 Expanding the Role of Fan- in and FO- WLP: Technology and Infrastructure Developments E. Jan Vardaman, President and Founder, TechSearch InternaGonal
2 Mobile Products ConGnue to Get Thinner Source: ASE.
3 iphone Trends: Increasing Number of WLPs 30 iphone Evolution WLCSPs Thickness (mm) /2007 3GS /2009 4S / /2012 5S / / /2014 iphone Model/year WLPs Thickness 6 iphone WLPs iphone 3GS WLPs iphone 4S WLPs iphone WLPs iphone 5S WLPs iphone WLPs iphone 6 Plus WLPs Shown to scale Source: ASE and TechSearch International, Inc., adapted from TPSS.
4 Drivers for WLP Major applicagons for WLP Smartphones (highest volume applicagon) Digital cameras and camcorders Laptops and tablets Medical AutomoGve Wearable electronics such as watch WLP meets system packaging needs Small form factor Need for low profile packages Lower cost (less material) Form Factor is Key Low profile Limited space on PCB
5 ConvenGonal WLP ApplicaGons ConvenGonal WLPs for many device types (analog, digital, sensor, discrete) Power management IC (PMIC) Audio CODEC RF IPD, ESD protecgon, filter LED driver Electronic compass Controller MOSFET CMOS image sensors Ambient light sensors EEPROM ConvenGonal WLPs trends Highest I/O count 309 (Fujitsu power management IC) Largest body size Qualcomm PMIC 6.5 mm x 6.5 mmx 0.71 mm, 0.4mm pitch Increasing number of 0.4mm pitch parts, some 0.35mm pitch Fine pitch parts need high- density PCB to route signals Source: ASE.
6 Fan- In WLP Market ProjecGons 50,000 40,000 Millions' of'units 30,000 20,000 10,000 0 ConvenGonal fan- in WLP demand Growth driven by greater adopgon in smartphones, tablets, and wearable electronics CAGR of almost 9% from 2014 to Source:33TechSearch3International, Inc.
7 Drivers for FO- WLP Smaller form factor, lower profile package: similar to convengonal WLP in profile (can be 0.4 mm) Thinner than flip chip package (no substrate) Can enable a low- profile PoP solu3on as large as 15mm x 15mm body Support increased I/O density Allows use of WLP with advanced semiconductor technology nodes with die shrinks With increased I/O and smaller die can t fan- in using conven3onal WLP Split die package or mulg- die package/sip Mul3ple die in package possible Die fabricated from different technology nodes can be assembled in a single package Can integrate passives Excellent electrical and thermal performance Excellent high temperature warpage performance Improved board- level reliability Fine L/S (10/10µm), roadmaps for ( 5/5µm) Source: STATS ChipPAC. Intel Wireless Division LTE analog baseband 5.32 x 5.04 x 0.7mm ewlb 127 balls, 0.4mm pitch Source: TPSS.
8 NANIUM s ewlb Technology Roadmap Package Size (mm 2) 12 x x 25 (SiP) 30 x 30 (SiP) Metallization Layers (RDL & UBM) 1x2 Single Side 1x3 Single Side 2x1 Double Side 1x4 Single Side 2x2 Double Side Line / Space (µm/µm) Panel Size (mm) Die-to-Die (µm) Die-to-Pkg (µm) 10/ dia /8 5/5 2/2 300plus dia 450 dia rectangular Package Construction Single Die Multi-Die SbS w/ Passives PoP Stacked-Die Source: Nanium
9 MulG- Die/SiP FO- WLP SoluGon 2 Layer- RDL InterconnecGon 2 AcGve Die + 10 Passives 0201 SMD After Thin Film Processing, Solder Ball Attach and Singulation After Molding After Pick & Place 2015 TechSearch International, Inc. Source: NANIUM
10 FO- WLP for AutomoGve ApplicaGon Drivers Growth of acgve safety systems for automogve applicagons FO- WLP being adopted for mmwave applicagons Parking slot measurement (SRR) Blind spot detec3on (SRR) Adap3ve cruise control (LRR 77GHz) Emergency breaking Lane correc3on Volumetric shrink of current and future systems (40 to 90%) Increased funcgonality with heterogeneous integragon Improved in system performance Low parasi3cs Low inductance Improved board level reliability NXP radar module in FO-WLP Continental announced it is integrating Freescale s 77GHz radar technology into its next generation short- and midrange automotive radar modules Source: Freescale. Source: NXP.
11 ApplicaGon Processor Packaging Trends Thinner package and smaller footprint Today 1.0mm height requirement Future 0.8 mm 3D IC with TSV provides the ulgmate in package height reducgon, but congnues to be pushed out Silicon interposers too expensive for many mobile products PoP in high- end smartphones Op3on 1: Con3nue with FC on thin substrate Op3on 2: Embedded AP in boaom laminate substrate (MCeP) Op3on 3: Fan- out WLP with applica3on processor as boaom package Op3on 4: Some new format (SWIFT, NTI, etc.) FO- WLP AP in bokom PoP Low profile High rou3ng density Handle high power System integra3on with compe33ve cost Today s PoP (1.0mm) FO-WLP as Bottom PoP (<0.8mm)
12 FO- WLP ProjecGons 2,100" 1,800" Millions'of'Units' 1,500" 1,200" 900" 600" 300" 0" 2014" 2015" 2016" 2017" 2018" 2019" Source:""TechSearch"Interna:onal,"Inc." Early products included baseband processor (Infineon Wireless Division) Device types include RF such as Bluetooth, NFC, GPS, PMIC, automogve radar, future applicagon processors
13 FO- WLP Merchant Suppliers Status Amkor Technology redeploying FO- WLP with new 300mm line (ewlb) in K4 plant ADL Engineering 200mm pilot line in Taiwan ASE license for Infineon s ewlb with 300mm in Taiwan, also offers chip last panel version Deca Technologies (300mm panel format) FCI/Fujikura (embedded WLP in flex circuit) NANIUM (300mm wafer) license for Infineon s ewlb NEPES (300mm line in Korea) based on Freescale s RCP process PTI (R&D on panel) SPIL (300mm wafer) STATS ChipPAC (300mm wafer) will be purchased by JCET, license for Infineon s ewlb TSMC (300mm wafer InFO WLP) New suppliers TBD
14 Industry Needs Same Package Choice from Suppliers Success of McDonald s Hamburgers Looks the same Taste the same No maaer which geographic region Packages need to. Look the same Have the same reliability No maaer which company/ country loca3on 2015 TechSearch International, Inc.
15 ExcepGons to the McDonald s Hamburger Rule When a foundry. Provides its foundry customer a packaging solu3on Enables faster 3me to market with silicon and package delivery Provides a warranty accepted by end customer When a company is vergcally integrated. From silicon design and fabrica3on to IC package and assembly to end product If same funcgon is accepted Different process Alterna3ve accepted with same func3on, performance, and reliability
16 AlternaGves to ReconsGtuted Wafer FO- WLP Reconstituted Wafer FO Amkor s SWIFT ASE s chip last ConvenGonal flip chip Source: Infineon. Source: Amkor. SPIL s NTI Molded Interconnect Substrate (MIS) Embedded die solugon/panel processing Source: ASE. IC IC Source: TDK. Source: SPIL TechSearch International, Inc.
17 Amkor s SWIFT Target Markets Mobile, Networking BB, AP, Logic + Memory, Deconstructed SoC UGlizes ExisGng Bump and Assembly Capability Polymer based Flexible Mul3- die and large die capability Large package body capability Advanced die integra3on Stepper capability down to 2um line/space Die shig / orthogonal rota3on elimina3on Down to 30um in- line copper pillar pitch 3D capability Package stack capability using Cu pillars or TMV SWIFT TM Single Die Overmold SWIFT TM 2 Die Overmold SWIFT TM 2 Die Exposed SWIFT TM 2 Die TMV PoP Overmold SWIFT TM 2 Die Fan-in PoP
18 ASE s Chip s Last Package Source: ASE. Uses low- cost coreless substrate Fine pitch capable (15 L/S today, 12µm L/S development) Manufactured in double panel format Assembled in strip format Mul3- die and passives possible Can be boaom PoP Thin package (<375 µm) High current and thermal handling capabiliges Due to thicker Cu (15-20 µm) Uses exisgng FC infrastructure Flip chip with Cu pillar mounted on coreless substrate Mass reflow and molded underfill
19 Fan Out Chip Last Panel vs Wafer UGlizaGon Panel Size: 510x410 mm (209, 100mm 2 ) X 2 Strip Size: 240x76.2 mm (X2L) Strip Array: 34x13 => 442 ea Wafer size : 300mm(70,686mm 2 ) 6:1 Area Source: ASE.
20 Molded Interconnect Substrate External% Terminal Top%View Wire%bond% Terminal Bo5om%View Inner)Lead)for) WB)or)FC Carrier Outer)Lead)with) NiPdAu)or)OSP Outer)Lead)with) NiPdAu)or)OSP Source: JCET. MIS- BGA offered by JCET (owns APS) and SPIL Versions offered by other OSATs 2015 TechSearch International, Inc.
21 Is Panel Processing a Viable AlternaGve? What size panel is feasible? Assembly of die on panel Die placement accuracy may be more difficult to control with large panels Large area bonders may be required Throughput (3me required to pick and place die in panel) How is placement accuracy impacted by tape and mold compound? What level of inspec3on is required to verify accuracy? What speed? Dielectric dispense methods? How to control run- out at edge? Need inspec3on for even coa3ng? Molding materials and process? Panel warpage Warpage increases with panel size Impact of materials (mold compound and filler) What type of inspec3on is requires and how will it work with warped panels Via formagon method (minimum via diameter) Via alignment Metal plagng Metal to dielectric interface (what inspecgon requirements?) How to spuker seed layer? Interconnect reliability? InspecGon for broken metal traces etc. SingulaGon method? Solder ball placement and inspecgon method?
22 AddiGonal ConsideraGons for Panel Processing Warpage (impacts assembly/ manufacturability) Heterogeneous materials and non- symmetric structures can cause bowing Polymer materials with adapted CTE and modulus, plus low shrink Accuracy/resoluGon (miniaturizagon) Improved op3cal recogni3on systems for placement equipment Imaging with high depth of focus and high resolu3on Yield (impacts cost) Suited materials and components Op3mized processes Produc3on experience Source: Fraunhofer IZM.
23 Conclusions Mobile products require low profile packages Fan- in WLP FO- WLP Demand for lower cost solugons drives adopgon of new package designs and formats Round panels? New chip last packages? MIS on modified leadframe? Large area processing? Many package choices Few standard op3ons except conven3onal WLP Growing number of companies selec3ng FO- WLP with recons3tuted wafer Alterna3ves will con3nue to be developed
24 Thank you! TechSearch Interna3onal, Inc Spicewood Springs Road, Suite 150 Aus3n, Texas USA
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