SiP Technology and Testing. Name: Philippe Cauvet Date: 2007, March 28

Transcription

1 SiP Technology and Testing Name: Philippe Cauvet Date: 2007, March 28

2 Outline Definition Market / Applications Design and technology Packaging Technologies Test Challenges Conclusion Journée EEA Montpellier 2

3 What is a SiP? System-in-package (SiP) = any combination of semiconductors, passives, and interconnects integrated into a single package SiP (System-in-Package) is a functional system or subsystem assembled into a single package Journée EEA Montpellier 3

5 Market Trends Industry moves to SiP Why a slowdown? Missing CAD tools certainly an obstacle Source: Gartner 1Q06 SiP Market Projection CAGR % Mu Shipment Automotive Communications Consumer Data Processing Industrial Gartner updates every quarter its SiP Market Projection Gartner view slightly increased since 3Q04 with 10% CAGR compared to 5% CAGR for Semiconductors: SiP and SoC grow in parallel! Gartner sees as much SiP in Consumer as Communication Journée EEA Montpellier 5

6 Applications Leading Applications for SiPs Applications include portable consumer products such as digital camcorders and cameras Mobile phone is the volume driver Logic and memory combo Digital baseband section Transceiver section RF section Journée EEA Montpellier 6

7 Applications: DSC SiPs show up in portable devices Journée EEA Montpellier 7

8 Applications: Mobile phones Journée EEA Montpellier 8

9 Applications: Bluetooth TM Bluetooth Radio: >1Billion Units shipped in 2006 Journée EEA Montpellier 9

10 Applications: OneChipSTB EEPROM 16Kb 16Mb SDRAM One board PCB 2 layers I²C 16 CVBS Tuner Channel RF input Front panel Bi-colour LED and IrDA Receiver One package STB sbsip + technology ISO7816 I²S Analogue video Audio DAC SVHS CINCH Right CINCH Left MPEG2 Video & Audio Decoder Smart Card(s) UARTs 16 4Mb FLASH 6.83 mm 9.43 mm Pics die 268 wires 64.4 mm² MOJO die PNX8316 MPEG2 A/V decoder 292 bumps 20.4mm² - 1W Silicon Tuner die TDA bumps Tuner 4.9mm² W Channel die Channel TDA bumps decoder 7.4mm² W BGA292 (drawing not to scale) Journée EEA Montpellier 10

12 SiP vs SoC (1) SoC Single piece of silicon Single technology Single level of interconnection Multiple chips Multiple technologies Multiple levels of interconnection and 3D SiP Journée EEA Montpellier 12

13 SiP vs SoC (2) Low Production Volume High Simple Technical Mix Consider Factors Carefully. Favor the use of SiP. Favor the use of SoC. Consider Factors Carefully. High Performance / Speed Factors to Consider: Production Volume Design Environment Dev Cost (Incl. IP Cost) Reliability Die Maturity Technologies (RF, Memories ) + Market Environment Complex Short Time to Market Long Low Source: Gartner 2006 Contibutor: JM Yannou, NXP SiP Innovation Manager Journée EEA Montpellier 13

14 Focus on EMC (and SiP): new challenges non SiP system Components placement is done empirically after circuits design SiP Components placement is done at the same time as circuits design: predictability needed!? system goes 3D! + components are closer to each other!? Journée EEA Montpellier 14

15 Example of an inter-system (inter SiP in susceptibility) EMC challenge Digital IC TV: up to 862MHz GSM: from 890MHz on The GSM antenna emits signals considered as noise by the close-by low-amplitude large-bandwidth TV RF receiving subsystem Decoupling capacitors integrated in silicon (Philips PICS technology), flip-chip bumped on digital: -16dB noise reduction measured! Analog IC Journée EEA Montpellier 15

17 SiP vs SoC Journée EEA Montpellier 17

18 Packaging challenges Higher integration requires smaller chips, with smaller pad pitch and size More chips = thinner chips (how to handle <100µm wafers?) More functionalities = more power Cost of materials Journée EEA Montpellier 18

19 Packaging Source: STATSChippac Journée EEA Montpellier 19

20 Packaging Source: DPC Journée EEA Montpellier 20

21 Intel Packaging Package-on-Package construction (folded flex circuit from Tessera) Processor, flash & SDRAM Prototype of 8-dies stack with no interposer (50µm die thickness) Intel is now using copper pillar bumping for its processors Journée EEA Montpellier 21 15

22 Tessera Packaging Carrier R L (Q) C Interconnectivity Flex no 60 no 14 lines/mm Si/GaAs no? 0,11nF/mm²? Package-on-Package (folded carrier) 2 metal-layer polymide providing electrical and mechanical properties for interconnect Processor with associated memory Tessera/Intel folded stacked CSP package Configuration examples Folded Stacked CSP assembly process Sources : Prismark wireless technology report March 2005 Journée EEA Montpellier 22

23 MMM6000 Module Freescale Packaging Single package transceiver for quad band EGPRS (GSM/GPRS/EDGE) 11.2x9mm 9 SMDs SMDs x2.6mm 0.13µm CMOS 2.7x2.9mm 0.18µm RFCMOS 1.1x1.1mm IPD device Journée EEA Montpellier 23

24 Sychip Packaging Silicon substrate with integrated passives Size (mm) I/O Availability Known Partnerships 9x9 12x12 Sampling?? Source : Sychip Journée EEA Montpellier 24

25 Packaging NXP Silicon-based SiP concept Flip chip Passive die Standard HVQFN package Molding compound Passive die lead tip Active die tip lead Key benefits Performance (flip chip interconnects) Inductance / 4 to 6! Size (3D stacking, passive integration) Low thermal resistance Flip chip Active die Journée EEA Montpellier 25

26 MEMS Packaging Journée EEA Montpellier 26

27 MEMS packaging SAW filter on silicon substrate PICS substrate LiTaO3 substrate Cavity Polymer pattern on PICS SAW filter Assembly: Thermo-compression Assembly enabling an electrical contact and sealing PICS substrate LiTaO3 SAW filter 1mm Polymer seal ring Gold stud-bump Journée EEA Montpellier 27

28 MEMS Acceloremeter stacked die package STMicroelectronics Targeted applications Toys, medicals, phones, anti-theft 4.3x4.0x0.4mm MEMS die 3.9x4.0x0.4mm cap die 3x2.8x0.2mm logic die QFN 28 I/O, 2 stacked die Die to die and die-leadframe wirebonds Journée EEA Montpellier 28 26

30 SiP vs SoC Compared to a SoC,, a SiP may have more Circuit Functions Supply Voltages Process Techno. Signal Frequencies Suppliers Signal Levels Quality Levels Failure mod./mech. Journée EEA Montpellier 30

31 NXP SiP Test Vision Chip A Chip B Chip C Test Test Test Test cost = 3U Today: + Test of PCB + Interconnects + Passives + Functional Test cost = 4U Future (w SiP): Test cost < 3U - Test of PCB With a Higher - Interconnects Coverage! - Passives (almost 0!) = Functional Test cost << 4U Journée EEA Montpellier 31

32 A Complex Test Flow Wafer Test Final Test Fab of X & PCM Test Fab of B Fab of A & PCM Test Known Good Die B Dies! Die X Wafer Test Die A Wafer Test SiP Packaging. SiP Final Test D E L I V E R Y Digital or Mixed-mode Passive Substrate Analog/RF System-level Test: DfT Quality level Yield Fast Diagnosis at and a reasonable Test Known-Good-Dies! cost! Journée EEA Montpellier 32

33 Known-Good-Die KGD Definition: (from a test perspective) Good enough to meet, at die level, at least the same quality level as a packaged IC Implies that : KGD test = WT + FT of a packaged die!! Journée EEA Montpellier 33

34 Cantilever RF probing concept Package: Wire bonding length Die under probes: Needle length Bonding: 1-3mm Leadframe: mm size Probe tips: 3-5mm Rule of thumb: 10mm represent 10nH serial inductance impossible to test a for example! Total Probe length: 10-15mm Journée EEA Montpellier 34

35 Microstrip transmission line Thin film technologies for RF probing 40um-60um Thin film, Μr 25um Ground plane Rule of thumb: Membrane 0.05mm represents less than 0.5nH serial inductance (typical 0.2nH specified) Contact bumps Forced-delivery mechanism Terminations and bypasses Carrier PCB Membrane Contact bumps Journée EEA Montpellier 35

36 MEMS technologies for RF probing Springs for solder bumps Cantilevers for contact pads RMS roughness 15 nm Length to 600 µm Width µm Thickness 11 µm Planarity 1.07 µm over 1 mm range Journée EEA Montpellier 36

37 Full Test at Wafer Alternative Test Methods Signature-based Testing (V DD Test Pattern) I DD R Power supply sweep I-V Signatures Multiple observation points Simple method black-box methodology No functional testing Short test time Package (Reference Clock Signal) L=1n H CLKI N DUT VOS C R LP F CLKOU T V CLK C LPF Journée EEA Montpellier 37

38 Management of diversity Which leads SiP package test to: Require greater diversity of ATE resources than SoC Require greater diversity of test & reliability screen methods than SoC Have large disparities in test times and resource utilization among die Solutions: Insert in multiple testers Better scheduling of test resources to allow independent, simultaneous test of each accessible chip in SiP BIST / DfT / DSP Journée EEA Montpellier 38

39 System Testing Issues Intermediate Test Points may affect signal integrity and leads to longer test times TX Data bits PA Buf D Philips: A Philips: DigRF DigRF interface interface advantage LNA advantage vs vs disadvantage disadvantage D AGC A DSP core TX-FEM RX Transceiver Baseband So, what to do? Journée EEA Montpellier 39

40 1. Test Rx and Tx paths independently Ref: Seamless test of Digital Components in M/S paths, S. Ozev et al TX Data bits Modulated RF Modulated RF TX-FEM PA Buf Philips: A Philips: DigRF DigRF interface interface advantage LNA advantage vs vs disadvantage disadvantage D AGC RX Transceiver Baseband A D DSP core DSP DSP Pro: Contra: - close to the application conditions - two-pass test = reduced test time - reduced risk of signal degradation - expensive ATE - quality of contacts critical - diagnosis?? Journée EEA Montpellier 40

41 2. Test Rx and Tx paths together (loop-back) Ref: Wafer level RF Test and DfT for VCO Modulating Transceiver Architectures, S. Ozev et al TX PA Buf D Philips: A Philips: DigRF DigRF interface interface advantage LNA advantage vs vs disadvantage disadvantage D A AGC DSP core Data bits DSP DSP Pro: TX-FEM RX Transceiver Baseband Contra: - low-cost (no?) ATE - benefit from PICS capabilities - test simulation - easier BIST implementation - need DfT (not a simple short-circuit!) - correlation with lab measurements - mgt of yield / test escapes - diagnosis?? Journée EEA Montpellier 41

42 Loop-back starts at the beginning Biggest advantage: Full digital test Auxiliary function LNA Auxiliary function ADC N BPF BPF LO BPF VGA ADC N ADC1 LNA HPA ADC1 DAC1 BPF BPF LO BPF VGA HPA Challenges: Transceiver : RF Die Loop-back: Analog Design For Test issue Auxiliary function Test methods: digital post processing ADCs DACs test Transceiver : RF Die Auxiliary function DAC1 ADC M Mixed Signal Die ADC M Mixed Signal Die Compensate data converters errors improve their performances similar to measurement instruments Test each block through other blocks Journée EEA Montpellier 42

43 Loop-back starts at the beginning DAC1 Digital part 1 ADC2 Analog Part 2 RF Part Digital part 3 ADC3 Analog Part 1 Digital part 2 DAC4 Digital part 4 ADC1 Analog Part 1 ANC DAC3 ADC4 Strategy: 1. Find DSP-based methods / algorithms to re-use the analog/ms blocks as instruments 2. Implement hardware that supports the methods Journée EEA Montpellier 43

44 SiP Testing Diagnosis capabilities using signatures TX Data Faults PA Buf D Philips: A Philips: DigRF DigRF interface interface advantage LNAFaults advantage vs vs disadvantage disadvantage D A AGC DSP core Faults DSP DSP TX-FEM RX Transceiver Baseband Journée EEA Montpellier 44

45 Testing Wirelessly (LIRMM+NXP) Transmitter/ Receiver ATE Test Control Block Die 1 Die 3 Die 2 SIP Architecture for testing a SiP wirelessly Journée EEA Montpellier 45

47 Summary SiP is: significantly growing not a SoC represents many challenges in: design (tools, EMC, ) packaging (stacked, planar, PiP, PoP, ) test (KGD, System Testing, ) thus, SiP technologies offer many perspectives / opportunities to students, researchers and engineers Journée EEA Montpellier 47

48 Thank You

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50 Le Mastère Spécialisé «Microelectronics System Design & Technology» forme des spécialistes de la conception de systèmes micro-électroniques & micro-technologiques The specialized Master in «Microelectronics System Design & Technology» trains specialists in micro-electronic and microtechnological systems design Journée EEA Montpellier 50

51 Introduction 20h SoC Design Methodologies 60h Coupling Effects 60h Advanced Processes 60h Manufacturing 40h CONTACTS SiP Design Methodologies 80h Advanced Tests 80h hours 560 h classrooms (5 months) and exercises (1 month) 910 h Internship (6 months) 2 intakes: February and September Business Management 40h Executive Master s Degree (Bac+6) Journée EEA Montpellier 51