How to avoid Layout and Assembly got chas with advanced packages

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Charleen Allen
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1 How to avoid Layout and Assembly got chas with advanced packages Parts and pitch get smaller. Pin counts get larger. Design cycles get shorter. BGA, MicroBGA, QFN, DQFN, CSP packages are taking the design world by storm. Learn how to avoid the most common trip-ups when designing with these packages. Also learn how the various board finishes can impact the use of advanced package components in a prototype world.

2 Presenter Bio: Duane Benson is a 25-year technology veteran and runs the marketing department at Screaming Circuits, a quick-turn prototype pcb assembly company.

3 Why are you all here? Small means something different now 1 to 0.5 is no big deal 1mm to 0.5mm is

4 Why is it such an issue now? Old days TH first Now, just small packages because of volumes

5 What is advanced packaging 0.5mm or smaller pitch BGA, ubga, CSP, LGA QFN 0402, 0201 and passives A little RoHS, just because Look close: 0201s and 01005s

6 BGA, ubga, CSP, LGA

7 BGA LAYOUT Lead vs. no lead Assembly has to follow the BGA Non-soldermask defined pads are preferred Better mechanical connection

8 BGA LAYOUT Non Solder Mask Defined land pad side view NSMD SMD

9 MICRO BGA ROUTING Not enough room Don t change pad size or shape

10 VIA TYPES A little refresher

11 BGA VIA IN PAD Not a time to buy a board based on price

12 BGA VIA IN PAD Capillary action = bad Sucking solder through a straw much worse than sipping cider through a straw Worse with lead

13 VIA IN PAD Open Ye haw!

14 BGA VIA IN PAD Bad, bad, bad example board Uneven board surface Giant via holes Low precision

15 BGA VIA NEAR PAD

16 BGA VIA NEAR PAD B: Via can still wick solder away B: Solder mask defined pads, not recommended

17 MASKED VIAS The intention was good, the workmanship was not

18 ALL-AROUND AWFUL

19 VIA NEAR PAD W/O MASK Post reflow Solder balls were sucked right off these two pads

20 BGA BOARD SURFACE HASL not really appropriate for ubga and CSP Flat surface is very important with super small parts

21 BGA BOARD SURFACE Bumpy HASL surface is not much of a problem with large parts Can be a problem with fine pitch and small CSP or ubga

22 PLUGGED VIA Flat (coplanar) surface is very important with the very small parts

23 PLUGGED VIA Flat (coplanar) surface is very important with the very small parts

24 PLUGGED VIA Flat (coplanar) surface is very important with the very small parts

25 QFN

26 QFN Thermal pad Heat sink May require lots of vias Grounding Simple low-speed ground may not require any vias High speed & RF may require engineered via placement

27 QFN LAYOUT Solder paste stencil opening No big openings Bad Good

28 QFN FULL CENTER LAND Ideal if stencil is made correctly Little chance for tilt

29 QFN WRONG AND RIGHT May cause even less stable placement resulting in tilted component Reduces solder more evenly over the entire land area

30 QFN COPPER PATTERNS Some parts require Special copper patterns (From Freescale appnote)

31 QFN COPPER PATTERNS Don t forget the stencil pattern A full opening will almost guarantee faulty placement Make matching cutouts at reduced size (From Freescale appnote)

32 VIA IN PAD Via in pad Plug it and/or mask it, please Or, at least, make it very, very tiny Capping the chip-side is better than capping the bottom Reduce chance of outgassing and voids

33 QFN SMALL CENTER LAND Signal vias may short to ground Part may tilt Vias not fully capped

34 QFN VIA IN PAD

35 MASKED VIAS IN PAD Solder mask Better than nothing May break open

36 PLUGGED VIAS IN PAD Conductive fill Thicker via wall and non-conductive fill Plugs Plated over

37 PLUGGED AND MASKED Reduced chance of break-through or outgassing Can contribute to excess solder in center pad (simulated image)

38 BLORT

39 A BETTER WAY

40 0402, 0201, 01005

41 VERY SMALL PASSIVES Tombstoning Some process related causes Some layout related causes

42 TOMBSTONING Possible layout causes: Inner layers Uneven traces Large components close by Inner layer Sinks heat Wide trace Sinks heat

43 SOLDERMASK Raised soldermask can create a well and lead to tombstoning with tiny passives Can be cause by thick mask or SMD pads

44 MISCELLANEA

45 RoHS WETTING Can allow via in pad in some situations Lead-Free solder may not wick down small via holes Can allow smaller pad sizes for greater component density

46 RoHS SORT OF When is a RoHS passive, not RoHS?

47 ENIG & IMMERSION SILVER Black pad Micro voids Don t touch Don t cap both via sides on silver boards Keep dark, keep sealed

48 OSP Check for contamination Surface should be bright and consistent Caused by poor surface preparation at the fab house Caused by poor handling Caused by atmospheric contamination

49 OSP

50 So long and thanks for all the lead

DRIVING COST OUT OF YOUR DESIGNS THROUGH YOUR PCB FABRICATOR S EYES!

DRIVING COST OUT OF YOUR DESIGNS THROUGH YOUR PCB FABRICATOR S EYES! 4/3/2013 S THROUGH YOUR PCB FABRICATOR S EYES! Brett McCoy Eagle Electronics Schaumburg IL. New England Design and Manufacturing Tech Conference Brett McCoy: Vice President / Director of Sales Circuit