The Movement to Large Array Packaging: Opportunities and Options

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Hubert Pitts
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1 The Moveent to Large Array Packaging: Opportunities and Options E. Jan Vardaan, President w w w. t e c h s e a r c h i n c. c o

2 Mobile Products Continue to Get Thinner Source: ASE.

3 Sartphone ASPs Continue to Decline Source: Adapted fro IDC Sartphone ASPs continue to decline Creates price pressure on packages

4 What Packaging Solutions Enable Thin Products? And How Do We Lower Cost? Source: Infineon. Source: ASE. Source: IMC by TPSS. Source: Infineon. Source: TDK.

WLCSPs Thickness () iphone Trends: Increasing Nuber of WLPs 30 iphone Evolution 13 25 12 20 11 10 15 9 10 8 5 7

2 WLPs iphone 3GS 2009 4 WLPs iphone 4S 2011 7 WLPs iphone 5 2013 11+ WLPs iphone 5S 2013 22 WLPs iphone 6 2014

5 WLCSPs Thickness () iphone Trends: Increasing Nuber of WLPs 30 iphone Evolution /2007 3GS /2009 4S / /2012 5S / / /2014 iphone Model/year WLPs Thickness 6 iphone WLPs iphone 3GS WLPs iphone 4S WLPs iphone WLPs iphone 5S WLPs iphone WLPs iphone 6 Plus WLPs Shown to scale Source: TechSearch International, Inc., adapted fro TPSS.

6 Drivers for WLP Major applications for WLP Sartphones (highest volue application) Digital caeras and cacorders Laptops and tablets Medical Autootive Wearable electronics such as watch WLP eets syste packaging needs Sall for factor Need for low profile packages Lower cost (less aterial) For Factor is Key Low profile Liited space on PCB

7 Conventional WLP Applications Conventional WLPs for any device types (analog, digital, sensor, discrete) Power anageent IC Audio CODEC RF IPD, ESD protection, filter LED driver Electronic copass Controller MOSFET Iage sensors Abient light sensors Conventional WLPs trends Highest I/O count 309 (Fujitsu power anageent IC) Largest body size Apple/Cirrus Logic Audio CODEC 5.72 x 6.03 x 0.59, 121 solder balls, 0.5 pitch Increasing nuber of 0.4 pitch parts, soe 0.35 pitch Fine pitch parts need high-density PCB to route signals Source: ASE.

8 What Set the Stage for FO-WLP? Historically, conventional WLPs for low I/O sall die 2 to 100 I/Os Next 100s of I/Os Now 400+ I/Os With increased I/O can t fan-in using conventional WLP Need for split die package or ultidie package Source: Casio Micronics Source: ASE Intel Wireless Division LTE analog baseband 5.32 x 5.04 x 0.7 ewlb 127 balls, 0.4 pitch

9 FO-WLP Drivers Saller for factor, lower profile package: siilar to conventional WLP in profile (can be 0.4 ) Thinner than flip chip package (no substrate) Support increased I/O density Excellent electrical and theral perforance Excellent high teperature warpage perforance Fine L/S (10/10µ) Can enable a low-profile PoP solution as large as 15 x 15 Multiple die in package possible Die fabricated fro different technology nodes can be assebled in a single package Source: STATS ChipPAC.

10 Multi-Die FO-WLP Solution 2 Layer-RDL Interconnection 2 Active Die + 10 Passives 0201 SMD After Thin Fil Processing, Solder Ball Attach and Singulation After Molding After Pick & Place Source: NANIUM

11 FO-WLP Projections Device types include RF such as Bluetooth, NFC, GPS, PMIC, autootive radar, future application processors Assues that cost targets, business, and reliability requireents are et

12 FO-WLP Merchant Suppliers Status Akor Technology redeploying FO-WLP with new 300 line (ewlb) in K4 plant ADL Engineering 200 pilot line in Taiwan ASE license for Infineon s ewlb with 300 in Taiwan, also offers chip last panel version Deca Technologies (300 panel forat) FCI/Fujikura (ebedded WLP in flex circuit) NANIUM (300 wafer) license for Infineon s ewlb NEPES (300 line in Korea) SPIL (300 wafer, R&D on panel) STATS ChipPAC (300 wafer) will be purchased by JCET, license for Infineon s ewlb TSMC (300 wafer InFO WLP) New supplier TBD

13 What s Next?... Wafer Processing Moves Closer to PCB Fabrication

lines and spaces in cobination with seiconductor equipent and organic substrates Ebedding of bare

14 Panel Level is: The intelligent cobination of Wafer Level Processing and PCB Processing (Fraunhofer IZM in Gerany) Fusion of sei WLP / LCD / PCB / Solar / flexible electronic infrastructures Finer lines and spaces in cobination with seiconductor equipent and organic substrates Ebedding of bare dies into organic substrates Glas, PCB, Filled Epoxy KGDpanel TechSearch International, Inc.

15 PLP Strategies Panel-Size FO-WLP PCB Ebedding Large-area olding 18" x 24" Through old vias for 3D Interconnects using PCB aterials & technology Mold ebedding of sensors Source: Fraunhofer IZM. Use of new polyers / lainates thin layers (10 µ) for high density high breakthrough (>40 kv/) for power Iproved resolution for interconnects 10 µ 5 µ 2 µ Processes to reduce warpage

16 PCB Ebedding Today: Power and Logic The production of ebedded packages increasing Sart Phone Market DC/DC converters Power anageent units Connectivity odule Coputer arket MOSFET packages Driver MOS SiPs PCB Ebedding Technology is ipleented or will coe soon at PCB anufacturers Seiconductor anufacturers OSATs Source: Fraunhofer IZM.

17 Fraunhofer IZM Substrate Integration Line Datacon evo/ ASM Siplace CA3 Mahr OMS 600/ IMPEX prox3 WL: Towa up to 8 PL: APIC up to 18 x24 incl. 12 WL (Q3 2014) Lauffer/ Bürkle Sieens Microbea/ Scholl Picodrill with HYPER RAPID 50 Scholl MX1 Ragraber autoatic plating line Orbotech Paragon Ultra 200 Schid

18 Panel Molding 18 x 24 APIC Yaada Equipent in Japan before shipent First olded panel 18" x 24 " Large area copression olding: Wafer Level: 300 up to 450 possible Panel Level: 18 x 24 (456 x 610 ²) Laination Up and Running as of Q4/2014

19 Akor/J-Devices Panel Level Processing Starts with copper base plate (provides good theral perforance) Build substrate on top of die, ball attach, and singulation» Source: J-Devices.

Circuitry Opening Via Holes Proprietary Via Fill Technology Co-Laination Die Ebedding, Layer Stack

20 FCI s ChipletT Fan-Out on Flex Circuit Ebedded IC Wafer Level Packaging Process Foring RDL Backgrinding / Polilshing Singulation Wiring board Flexible Printed Circuit Process Foring Copper Circuitry Opening Via Holes Proprietary Via Fill Technology Co-Laination Die Ebedding, Layer Stack Up & Laination Backend Processing SMT, Molding, Buping, Marking, Singulation Source: FlipChip International.

21 ChipsetT TM Ebedded Die Panel Processing Panel Scale Ebedding Process Precision Ebedded Coponent Placeent Single Step Laination Current Panel Size: 250 x 350 Panel Size Extendibility to 350 x 500 Source: FlipChip International, Inc.

cost Fan out Packaging Low Cost Coreless Substrate Chip Last vs Chip First for Higher Assebly yields Fine Pitch

22 ASE s Fan Out Chip Last Package Utilizing Low Cost FC Coreless Substrate Ebedded Traces & Pads Fine Pitch capable Cobined with Mass Reflow fine pitch Cu Pillar FC & Molded Underfill (MUF) Creates new Paradig in low cost Fan out Packaging Low Cost Coreless Substrate Chip Last vs Chip First for Higher Assebly yields Fine Pitch buping direct on die pad without RDL Thicker Copper (15-50 µ) allows higher current Thin Package < 375µ MSL 1 Source: ASE.

23 FO-WLP Panel Issues ( 17 x 17) What size panel is feasible? Assebly of die on panel Die placeent accuracy ay be ore difficult to control with large panels Large area bonders ay be required Throughput (tie required to pick and place die in panel) How is placeent accuracy ipacted by tape and old copound? What level of inspection is required to verify accuracy? What speed? Dielectric dispense ethods? Spin coat? Other ethods? How to control run-out at edge? Need inspection for even coating? Molding aterials and process? Panel warpage Warpage increases with panel size Ipact of aterials (old copound and filler) What type of inspection is requires and how will it work with warped panels Via foration ethod (iniu via diaeter) Via alignent Metal plating Metal to dielectric interface (what inspection requireents?) How to sputter seed layer? Interconnect reliability? Inspection for broken etal traces etc. Singulation ethod? Solder ball placeent and inspection ethod?

24 Conclusions Mobile produces require low profile packages Fan-in WLP FO-WLP Ebedded die Declining ASPs for end products create price pressure driving developent of new low cost package options Deand for lower cost solutions drives adoption of large area packaging Panel-based processing Adoption of new panel technology eans the wafer fab side, back end assebly, and PCB segents are erging Challenges in panel level processing create opportunities for all

25 Thank you! TechSearch International, Inc Spicewood Springs Road, Suite 150 Austin, Texas USA w w w. t e c h s e a r c h i n c. c o

Opportunities and Challenges for Fan-out Panel Level Packaging (FOPLP)

Opportunities and Challenges for Fan-out Panel Level Packaging (FOPLP) T. Braun ( 1 ), M. Töpper ( 1 ), S. Raatz ( 1 ), S. Voges ( 2 ), R. Kahle ( 2 ), V. Bader ( 1 ), J. Bauer ( 1 ), K.-F. Becker ( 1