How To Test A Power Supply On A Powerline On A 2.5V Power Supply

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1 Product is End of Life 3/24 Si975 In-Rush Current Limit MOSFET Driver DESCRIPTION The Si975 current limit MOSFET interface IC is designed to operate between a power source and a load using a low onresistance power MOSFET with a sense terminal or in conjunction with a low ohmic sense resistor. The Si975 current limiter prevents source and load transients during hot swap and power-on with programmable dv/dt and di/dt. Both turnon and steady-state current limits can be individually programmed, providing protection against short circuits. Power on RESET and logic controls allow complete microprocessor interfacing. The RESET function of the Si975 is industrystandard with full programmability. FEATURES 2.9 to 3 V Input Operating Range Microprocessor RESET Integrated High-Side Driver for N-Channel MOSFET Programmable di/dt Current The Si975 is available in a 6-pin SOIC package and is rated over the commercial temperature range ( to 7 C). The Si975 is available in both standard and lead (Pb)-free packages. FUNCTIONAL BLOCK DIAGRAM COIL L BOOST R BIAS Bias Ref Boost BOOST HI/LO ENABLE Control Gate Drive POR GATE C BOOST Low R DS N-Channel FET STATUS I BIAS C GATE C RETRY Retry Delay Overcurrent + - SENSE LIMSET R LIMSET R SENSE (mw) LOAD V LOAD C RST GND POR Bandgap POR Reset Delay Ref Reset - + Ref V RST RESET Load Document Number: 728 S-4754-Rev. D, 9-Apr-4

2 Si975 Product is End of Life 3/24 ABSOLUTE MAXIMUM RATINGS Parameter Limit Unit Voltages Referenced to Ground 5 Boost Voltage 29 V Inputs/Outputs (except Gate, Boost and V RST ) -.3 to +.3 V RST Input Current ( < V RST < 5 V) 2 Inputs/Outputs Current 2 RESET Current 3 ma STATUS Current 3 Storage Temperature - 65 to 25 Junction Temperature 5 C Power Dissipation (package) a 6-Pin SOIC b 9 mw Thermal Impedance (Θ JA ) 4 C/W Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 7.2 mw/ C above 25 C. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified 2.9 V 3.2 V HI/LO = GND, R BIAS = 2.5 kω L BOOST = µh, C BOOST = nf Limits to 7 C Min a Typ b Max a Supply Quiescent Current I Q ENABLE = Logic Low 4 8 ma Logic Enable Turn-On Voltage V EN(on).3 x Enable Turn-Off Voltage V EN(off).7 x V Enable Source Current I ENSRC V ENABLE = V 4 2 µa Turn-On Time t ON 5 See Figure 3 Turn-Off Time t OFF 5 Turn-On Boost t ON(BST) See Figure 4 6 µs t OFF Initial Short Circuit t OFF(ISC) C GATE = 33 nf, See Figure 6 t OFF Short Circuit t OFF(SC) C GATE = 33 nf, See Figure 7 2 Status Output Voltage V STAT I SINK = 2 µa.4 V Status Output Delay Time t STDLY See Figure 8 25 µs Unit HI/LO Turn-On Voltage V HILO(on).7 x V Status Threshold V STATTHR.85 x.95 x HI/LO Turn-Off Voltage V HILO(off).3 x Gate Drive Enhancement Voltage (V GATE - V SENSE ) V GS V Source Current V CBOOST = 9 V Sink Current I SINK ma Current Sense Circuit Current Sense Amplifier Common Mode Range V CMR +.3 V Current Sense Amplifier Voltage Offset V OS mv Current Sense Amplifier Bias Current I SOS Normal Operation -.2 R LIMSET Reference Current I RLIMSET µa Current Sense Amplifier Hysteresis V HYST 2 Current Sense Amplifier Series Offset V SOS HI/LO =, V CMR >.5 V 2 mv 2 Document Number: 728 S-4754-Rev. D, 9-Apr-4

3 Product is End of Life 3/24 Si975 SPECIFICATIONS Parameter Symbol Test Conditions Unless Specified 2.9 V 3.2 V HI/LO = GND, R BIAS = 2.5 kω L BOOST = µh, C BOOST = nf Limits to 7 C Min a Typ b Max a Power On Reset RESET Output Voltage V OP(rst) I OUT = ma, > 2 V.4 V RESET Output Hysteresis c V HYST See Note c 2 mv RESET Comparator Input Threshold V RST V RESET Comparator Offset Voltage d V RBIAS.5 mv RESET Comparator Input Bias Current I BIAS -.2 µa RESET Timer Delay t RSTD C RST = 5 nf, See Figure µs RETRY t RETRY C RETRY = nf ms Notes: a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test. c. In a practical situation, V HYST is multiplied by ratio of a resistor divider chain. For = 3.2 V, V HYST = 2 mv. d. The RESET comparator input threshold specification (V RST ) includes the RESET comparator offset voltage. PIN CONFIGURATION AND ORDERING INFORMATION SOIC-6 Unit BOOST GATE LOAD SENSE LIMSET COIL GND C RST C RETRY RESET STATUS ORDERING INFORMATION Part Number Temperature Range Package Si975CY Si975CY-T Si975CY-T-E3 to 7 C SOIC-6 HI/LO 7 V RST ENABLE 8 9 R BIAS Top View PIN DESCRIPTION Pin Number Function Description BOOST Output of on-chip Boost converter. A nf capacitor should be connected between BOOST and GND 2 Positive supply pin. 3 GATE Connection to external power MOSFET gate. 4 LOAD Connection to positive supply side of LOAD. 5 SENSE Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard MOSFET may also be used in conjunction with a low ohmic value shunt resistor. 6 LIMSET Connects overcurrent limit set resistor R LIMSET to the reference input of overcurrent trip comparator. 7 HI/LO CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND for low Capacitive loads and to for high capacitive loads. 8 ENABLE CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high. 9 R A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator BIAS resistor R LIMSET and the GATE (on) charge current. See Functional Description for equations. V RST Input to voltage monitor comparator. STATUS Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than 9 % of. 2 RESET Open drain NMOS output. This pin is driven low during power on reset or when V RST is lower than the internal.25 V reference. 3 C RETRY A capacitor connected from this pin to GND programs the retry timer. 4 C RST A capacitor connected from this pin to GND programs the reset timer. 5 GND Negative supply pin. 6 C OIL Connection to Boost converter inductor. Document Number: 728 S-4754-Rev. D, 9-Apr-4 3

4 Si975 Product is End of Life 3/24 FUNCTIONAL DESCRIPTION The Si975 together with an N-Channel MOSFET provides the following functions: limits di/dt current for hot insertion applications provides complete short circuit protection high-side drive allows N-Channel MOSFET to be used, for lower power dissipation industry-standard microprocessor reset function logic control input and outputs If the HI/LO pin is tied low the current limit is 2 % higher during turn-on than the steady state current limit point. I LOAD x R SENSE >.2 x I BIAS x R LIMSET (with pin HI/LO = Low) If a higher current limit is needed at start-up, the HI/LO pin can be tied high. The equation becomes: (2) Setting the Current Limit (SENSE, HI/LO pins, R LIMSET, R SENSE ) I LOAD x R SENSE >.2 x I BIAS x R LIMSET + I BIAS ( kω + R HI ) (HI/LO = High) (3) The current limit point is determined by the voltage across R SENSE, the value of R LIMSET, and the bias current. The current limit circuit is shown in Figure The steady state current is set by the equation: I LOAD x R SENSE > I BIAS x R LIMSET Due to the highly capacitive nature of some loads, the Si975 has an option to increase the current limit point to a much higher level at turn-on. In this case, turn-on is defined as V GATE < V. This function is implemented with the HI/LO pin. () Notice that any current limit can be set at turn-on using an optional resistor, R HI. Relaxation Mode Current Limit (C RETRY pin) In an overload condition, the Si975 will go into a relaxation mode current limit operation that not only protects the source and load, but also reduces the power dissipated in the MOS- FET. When an overload is detected, the circuit quickly turns off, then goes into a retry mode whereby the current is ramped up slowly. If the fault still exists, the current will ramp down again. This sequence will repeat indefinitely at a period defined by 6 x C RETRY until the fault is removed. Typically, capacitors in the range of nf to µf can be used on C RETRY, but the period should be > 5 ms. Si975 I BIAS Overcurrent + kω, ± 2 % HI/LO SENSE GATE LIMSET HI/LO R HI (Optional) R LIMSET R SENSE I LOAD V LOAD 33 Ω 33 Ω 33 nf Figure. 4 Document Number: 728 S-4754-Rev. D, 9-Apr-4

5 Product is End of Life 3/24 Si975 FUNCTIONAL DESCRIPTION (CONT D) di/dt Limiting On Hot and Cold Insertion (GATE pin) The GATE pin provides a constant current source that is used to control the rate of rise of the gate of the MOSFET, and hence to control the di/dt of the load and source current. The equation that governs the gate current is: =.25 V x 2 R BIAS (for R BIAS = 2.5 kω).2 ma (4) Boost Converter (COIL, BOOST pins) The boost converter generates the gate drive for the external N-Channel MOSFET. This is limited to typically + V. The boost inductor should typically be µh, < 3.5 Ω, > 8 ma dc, and the boost capacitor should be nf. Logic Control (STATUS, ENABLE, RESET, V RST and C RST pins) Typically, a 33 nf capacitor should be connected from the GATE pin to ground. If a large is needed for high di/ dt, a 33 Ω resistor in series with C GATE may be necessary to prevent oscillation. In the case that > 6 V, a resistor of approximately 33 Ω is also recommended in series with the gate. (Figure ). Reference Bias Current (R BIAS pin) This pin sets the internal current used by R LIMSET to determine all the current limit points. Typically R BIAS = 2.5 kω which sets a 2 µa bias current. The equation which relates R BIAS to I BIAS is: I BIAS =.25 V 2 µa 5xR BIAS (5) STATUS. The status monitor detects when the load voltage is 9 % of input voltage, V LOAD >.9 x. This pin is an open-drain NMOS output, capable of sinking 2 µa at V OL =.4 V. If this pin is used in conjunction with the ENABLE of another unit, power supply sequencing (or daisy-chaining) is easily implemented. ENABLE. This CMOS logic compatible input serves as the on/off control pin. This pin has 4 µa minimum pull-up to. RESET (V RST, C RST, RESET pins). This is a standard implementation of the microprocessor reset function. A comparator looks at the voltage on V RST pin and compares it with.25 V. This function is programmable by using an external voltage divider. When V RST is higher than.25 V, the reset signal is delayed by the C RST pin, defined by Equation (6) and then goes high. (Figure 2): (for R BIAS = 2.5 kω) Reset delay t RSTD 4 x C RST (6) Power on Reset (POR) ( pin) HI/LO Pin R LIMSET C RETRY This function monitors the voltage on the pin and signals the system if all input voltage requirements have been met. At turn-on when > 2.7 V ± 2 mv, a POR signal is generated for a duration of µs. After this point the system is released into operation. If falls below 2.7 V ± 2 mv, a second POR signal will be generated. If two POR signals are detected, this indicates that the source for is not capable of supplying the load current. The IC then turns off the MOS- FET and initiates its retry period, hence fully protecting the MOSFET from an over-power condition. Current Turn-On V GATE > V Short Circuit Applied to Output Current Limit Point I LOAD Figure 2. Typical Operation Under Start-up Condition With An Overcurrent Fault Applied to the Output Document Number: 728 S-4754-Rev. D, 9-Apr-4 5

6 Si975 Product is End of Life 3/24 TYPICAL CHARACTERISTICS 25 C unless noted Gate-Source Current (ma ) I SINK - Gate-Sink Current (ma ) R BIAS (kω) (V) Gate-Source Drive Current vs. R BIAS Gate-Sink vs. 5 4 (µa) Current I R(LIMSET) - R LIMSET (µs) Delay Timer t RESET RESE T R BIAS (kω) C RST (nf) R LIMSET Current vs. R BIAS RESET Timer Delay vs. C RESET RETRY Delay (ms ) t RETRY C RETRY (nf) RETRY Delay vs. C RETRY 6 Document Number: 728 S-4754-Rev. D, 9-Apr-4

7 Product is End of Life 3/24 Si975 SWITCHING TIME TEST CIRCUITS ENABLE.7.3 t ON t OFF 5 % 5 % I SINK Figure 3. Normal-Mode Operation ENABLE t ON(bst) 5 % V BOOST t BOOST 9 % Figure 4. Timing Definition with ENABLE Already On Figure 5. Start of Boost Converter t RETRY I LOAD I LOAD V SENSE Threshold V SENSE Threshold t OFF(isc) t OFF(sc) V G Figure 6. First Short Circuit V I SINK 5 % Figure 7. Relaxation-Mode Current Limit V G V LOAD Status Threshold STATUS t STDLY t STDLY.3 x RESET(2) t RSTD (2) With reset input divider correctly set, monitoring V LOAD Figure 8. STATUS and RESET maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see Document Number: 728 S-4754-Rev. D, 9-Apr-4 7

8 Package Information SOIC (NARROW): 6-LEAD (POWER IC ONLY) JEDEC Part Number: MS E MILLIMETERS INCHES Dim Min Max Min Max A A B C D E e.27 BSC.5 BSC H L ECN: S-48 Rev. A, 2-Feb-4 DWG: 592 D H C All Leads e B A L. mm.4 IN Document Number: Jan-4

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