An FPGA-based high-speed network performance measurement for RFC 2544

Transcription

1 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 RESEARCH Open Access An FPGA-sed high-speed network performnce mesurement for RFC 2544 Yong Wng 1*, Yong Liu 2, Xioling To 3 nd Qin He 3 Astrct Aiming t the prolem tht existing network performnce mesurements hve low ccurcy for (Request for Comments) RFC 2544, this pper proposes high-speed network performnce mesurement sed on field-progrmmle gte rry (FPGA). The ctive mesurement method is used to generte proe dt frmes, nd pssive mesurement method is employed to count network trffic. According to the sttisticl lws sed on throughput vrition, intervl stretching mechnism is used to dynmiclly djust interfrme gp. When our pproch pproches the mximum throughput, the network performnce prmeters re chieved. A prototype sed on NetFPGA is lso implemented for evlution. Experimentl results show tht our pproch cn e pplied in high-speed network nd the ltency cn e ccurte to the nnosecond. Compred with network performnce mesurement using softwre to send proe dt frmes nd similr work sed on FPGA, our pproch cn e more flexile nd the evlution dt remoreccurte. Keywords: RFC 2544; Active mesurement; Pssive mesurement; Trffic genertor; Intervl stretching; Network performnce mesurement 1 Introduction The explosive growth in Internet deployment for constntly growing vriety of pplictions hs creted mssive increse in demnd for network performnce prmeters, such s throughput, ltency, nd pcket loss rte [1-6], which re very importnt for providing differentited network services. Accurte network performnce prmeters cn help to improve the qulity of network services, including ctive nd pssive resource mngement, trffic engineering, s well s providing qulity of service (QoS) gurntees for end-user pplictions. In prticulr, s modern network mngement systems shift their focus forwrd service-level nd ppliction-level mngement, the network monitoring process requires more dt to e collected in higher frequency. With the development of new network pplictions nd vlue-dded services, network trffic chrcteristics hve ecome more nd more complex. Different pplictions hve different flow chrcteristics nd ehviorl chrcteristics, so it is not enough to nlyze only using * Correspondence: wng@guet.edu.cn 1 CSIP Gungxi Center, Guilin University of Electronic Technology, Guilin , Chin Full list of uthor informtion is ville t the end of the rticle mthemticl simultion nd the clssicl queuing theory mode. But through the result of the network performnce prmeters nd its nlysis, we could simulte the Internet environment ccurtely, which helps us to optimize the network nd design the network equipment to certin extent. Different network pplictions hve different requirements for QoS. For exmple, file trnsfer services require low pcket loss rte nd high throughput, nd rel-time multimedi services demnd low ltency [7]. Through network mesurement, the users cn detect network congestion, locte network performnce ottlenecks, nd provide the sis for the network resource optimiztion. Fced with n incresingly serious thret to network security, the lrge-scle network mesurements re used to nlyze nd ssess the network performnce in norml circumstnces so erly wrning cn e provided to prevent lrge-scle network ttcks. Therefore, network mesurement method lso hs ecome n importnt men to protect the network security nd prevent lrgescle network ttcks. The most frequent used methods re ping nd trceroute. By clculting the time etween sending the 2015 Wng et l. This is n Open Access rticle distriuted under the terms of the Cretive Commons Attriution License ( which permits unrestricted use, distriution, nd reproduction in ny medium, provided the originl work is properly credited.

2 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 2 of 10 Internet Control Messge Protocol (ICMP) or User Dtgrm Protocol (UDP) pcket nd receiving the response pcket, the end-loop time cn e otined, ut the processing rte restricts the performnce of the ove solutions, which only enles the ltency to e ccurte to the milliseconds. Trnsmission Control Protocol (TCP) stte detection [8] performs nlysis of TCP flows. It utilizes TCP dt pckets nd its cknowledgement (ACK) pckets to mesure the throughput nd ltency. Unfortuntely, the results re only closer to the ctul network. Using the softwre [9,10] to generte test flow cn e esy to chieve, ut its results re difficult to mke the users stisfy to certin extent ecuse it could crete n extr overhed when generting the test flows constntly. It usully is not suitle to e deployed in high-speed network. In ddition, common network performnce nlyzers, such s SmrtBits nd TestCenter, re too expensive to e suitle for generl performnce enchmrks. In this pper, n FPGA-sed high-speed network performnce mesurement for RFC 2544 [11] is proposed. The ctive mesurement method is employed to generte lot of proe dt frmes set y the user. The pssive mesurement method is used to precisely count network trffic of ech Ethernet interfce nd other relted prmeters through Register I/O in rel time. According to the chnge of throughput, it dynmiclly djusts the interfrme gp to rech the limit of network performnce. Our pproch not only gets the ltency tht is ccurte to the nnosecond ut lso cn e pplied in high-speed network. The rest of this pper is orgnized s follows. Section 2 discusses relted work on network performnce mesurement. In Section 3, we put forwrd the network performnce mesurement enchmrks. The design of our pproch is shown in Section 4. Then in Section 5, experimentl tests nd performnce nlysis re given. Section 6 concludes the pper. 2 Relted work Currently, the mjority of existing network performnce mesurement methods is softwre-sed nd concentrtes on the mesurement of throughput, ltency, pcket loss rte, nd so on. The network performnce mesurement techniques re divided into two ctegories [12]. One is the ctive mesurement method nd the other is pssive mesurement method. The ctive mesurement method usully does not require collortion mong multiple nodes, which is very flexile. It is lso esy to operte. A methodology tht estimtes pcket loss rte etween ritrry end hosts without control on either end is developed in [13]. Using UDP y defult to trnsmit Domin Nme Service (DNS) queries ctively, it tkes dvntge of the retrnsmission ehvior of deployed DNS servers to conduct mesurements, ut it needs much more resources thn others, which could ring some difficulties to some extent. Sending proe frmes or Internet Protocol (IP) pckets to conduct the mesurements is nother solution. The network trffic configured y the users is needed to generte in the client windows. When the dt flows re sent or received, it should count the network trffic. Then, the relted prmeters, such s ltency, pcket loss rte, nd throughput, re clculted. The hrdwre-sed method cn process network trffic t much higher dt rtes. A hrdwre circuit is tested using n FPGA device which conducts n Ethernet tester [14] complint with the throughput nd ltency tests specified y the RFC 2544 for 10/100 Mps Ethernet networks; the usul limittions dded y severl hrdwre nd softwre lyers cn e overcome y implementing frme genertor directly in n FPGA device, ut it is only deployed in 10/100 Mps Ethernet networks. It is lso not flexile enough. A trffic genertor [15,16] sed on FPGA cn chieve full gigit link utiliztion, which motivtes us to do it etter. The pssive mesurement method does not tke up network ndwidth nd hs less impct on the network. It cn lso help us to get ccurte results. To clculte per-ppliction pcket loss, [17] periodiclly retrieves the expired flows from the two pssive monitoring sensors. Allowing pinpointing loss events for specific clsses of trffic, the pcket loss rte of individul trffic flows cn e mesured. Since it gets the relted informtion periodiclly, the pcket loss rte is difficult to e chieved in rel time. The recognition of lost nd retrnsmitted pckets nd segments for pcket-sed methods is one of chllenges in pssive round-trip time (RTT) mesurement. To overcome this prolem, [18] proposes n estimtion technique for RTT mesurement sed on flow monitoring. It clcultes RTT from five-tuple flow mesurement, which identifies the flow, s well s strt time nd end time for ech flow record, ut it should run much more time nd its results re not ccurte. 3 Benchmrks RFC 2544 provides lot of prmeters pplied in different network equipment test. In this pper, the ltency, throughput, nd pcket loss rte in our pproch re provided to conduct network performnce mesurement. 3.1 Ltency The frme forwrding dely cn e divided into queuing dely, trnsmission dely, nd the propgtion dely three prts. The trnsmission process of frme is shown in Figure 1. For frme k, the queuing dely is t ðþ k k iq, the trnsmission dely is t ðþ id, nd the propgtion dely is t ðkþ. The node in Figure 1 is trget device such ld

3 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 3 of 10 Figure 2 Interfrme gp model. S ð nþ ¼ Xn S i i¼1 ð3þ Figure 1 Trnsmission process of frme. s firewll, switch, router, nd so on or n equipment conducting mesurement. Supposing tht the dely of the frme k t the node i is T (k), we cn clculte it s follows: T k ð Þ iq ð Þ ¼ t k þ t ðkþ id þ t ðkþ ld ð1þ t ðþ k id nd t ðþ k ld re certin under specific mesurement condition. Due to the network trffic congestion nd other fctors in the cche of the node i, the length of the queue is dynmic, which mkes the t ðþ k iq chnged. The current network performnce mesurement method usully uses round-trip dely to evlute the network performnce. However, the one-wy dely my e more meningful for network services nd its error is smller thn the round-trip dely [19]. Therefore, we use one-wy dely to revel the ltency in this pper. We ssume tht T ðþ k t is the dely of the frme k t the node j nd T ðþ k o is the overlp etween the node i sending the dt frme nd the node j receiving the dt frme; Then, we cn get the one-wy dely T ðþ k, which is stted s follows: ð Þ T ð kþ ¼ T ðkþ þ T k t ð o Þ T k ð2þ 3.2 Throughput When sequence of frmes {P 1,P 2,,P n } re trnsmitted, δ is interfrme gp etween P i nd P i + 1 (1 i n 1). The forwrding dely of the ove frmes is clerly illustrted in the interfrme gp model shown in Figure 2. S i is the frme size corresponding to the frme P i.the totl size S ðnþ of the ove frmes sequence cn e set s follows: The time t i required for processing the frme P i is divided into two prts. One is the interfrme gp δ nd the other is the dely of forwrding frme. The t i ndthetotlforwrdingdelyt ðnþ cn e otined s follows: 8 S >< i t i ¼ C ; i ¼ 1 >: δ þ S i C ; 1 < i n T ð nþ ¼ Xn t i ; i 1 ð4þ ð5þ where C is the ottleneck ndwidth. The first frme P 1 does not need to wit for the interfrme gp. Thus, we cn clculte the throughput T B t the ove nodes denoted s follows: ð Þ T B ¼ S n =T ð nþ ¼ Xn S i = Xn t i i¼1 i¼1 ð6þ We define tht the throughput of entering the node represents the downlink throughput, while the throughput of leving the node indictes the upstrem throughput. Assuming tht V ={T BI,T B2,,T Bm } is set consisting of vlid mesurement of throughput on the sequence of frmes {P 1,P 2,,P n }for m times, we cn get the ottleneck ndwidth C s follows: C ¼ mxð T BiÞ ð7þ T Bi V From Equtions 4, 5, nd 6, it is ovious tht if we reduce the δ, then the T ðnþ will lso e reduced so tht the T B will increse correspondingly; ut conversely, if we increse the δ, it will mke the T B decresing in turn. Therefore, it is theoreticlly proved tht we cn dynmiclly djust the interfrme gp to grdully pproch to the mximum throughput, which enles us to implement the mesurement of the ottleneck ndwidth.

4 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 4 of 10 Figure 3 Lyout of the network performnce mesurement. 3.3 Pcket loss rte For the ove sequence of frmes {P 1,P 2,,P n } sent, the numer of the frmes sent nd the totl ytes of the sequence sent re S ðnþ out nd S ðnþ out t the node i, respectively. On other hnd, t the node j, the numer of the frmes stored nd the totl size of the sequence stored re S ðnþ in nd S ðþ in, respectively. Thus, frmes loss rte L f nd ytes loss rte L cn e set s follows: L f ¼ S ðnþ L ¼ S ðnþ out S ðnþ in S ðnþ out out S ðnþ in S ðnþ out 100% 100% ð8þ ð9þ 4 The FPGA-sed network performnce mesurement 4.1 Architecture The lyout of the components long with dt frme nd component interctions is shown in Figure 3. It minly includes trffic genertion, trffic sttistics, nd communiction interction. The ctive mesurement method is used to generte proe dt frmes. user dt pth is the core of dt pth processing, which includes n input riter nd trffic genertor. The input riter chooses dt frme from MAC RxQ or CPU RxQ nd then mkes it entry into the trffic genertor. By ccessing the sttic rndom ccess memory (SRAM), lot of dt frmes re generted y the trffic genertor ccording to the prmeters configured y the user. The pssive mesurement method is employed to count network trffic. The MAC RxQ nd TxQ re prt of frme processor, which receives nd trnsmits the dt frmes from the Ethernet interfce GigE Rx nd Tx, respectively. The network trffic stored nd sent ccording to its Ethernet interfce nd the frme forwrding dely re lso counted y it. The host computer often communictes with the FPGA to complete the performnce mesurement. Through Peripherl Component Interconnect (PCI) us interfce, not only the host computer cn send dt frmes to FPGA through the direct memory ccess (DMA)-engine, ut lso the host computer cn ccess the internl registers of the FPGA ny time. A CPU RxQ receives the dt frmes configured y the user from the host computer vi PCI us, which isthesourceoftheproedtfrme. Figure 4 Lyout of the trffic genertor.

5 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 5 of Trffic genertor The trffic genertor uses the ctive mesurement to generte network trffic. The originl proe dt frme configured y such prmeter s the frme length is generted y the linet [20] in the host computer, which instlls the NetFPGA ord. Through PCI us interfce, it is trnsmitted to CPU RxQ. Next, the input riter chooses dt frme from the ove CPU RxQ. Then, the dt frme enters the trffic genertor vi 64-it wide dt us. The lyout of the trffic genertor is shown in Figure 4. The dt frme trverses the circuit following the pth indicted y the old nd white rrows, while the register vlues crossing the circuit re shown y the old nd lck rrows. The dt frme is initilly processed y FIFO uffer which uffers some ytes if there re ny downstrem processing delys. Then, the frme flows into frme store. Next, the frme is stored in SRAM vi SRAM interfce. The ssocited frmes with the pproprite frme context informtion re retrieved vi Register I/O so tht the dt frme in the SRAM cn e monitored. When the lst word of the dt frme is written into the SRAM, the frme store will send control signl to mke frme remove informed, which tells the frme remove to egin reding the dt frmes in the SRAM. The frme remove provides client interfce nd psses the dt frme in the SRAM to MAC TxQ. It otins output Ethernet interfce x, thenumerof dt frmes y, nd interfrme gp z vi Register I/O, which re configured y the user through PCI us Figure 5 Trffic genertor process. Figure 6 Lyout of the frme processor. interfce t the eginning of the FPGA working. Using the ctive mesurement method, the frme remove reds the dt frme in the SRAM nd sends it to MAC TxQ ccording to x for y times. When reding two djcent frmes in the SRAM, it should wit for z clock cycles. In order to identify the success of the mesurement, it llows setting the different 64 its of specil tgs in the first nd lst dt frme. The trffic genertor process is shown in Figure Frme processor The frme processor uses the pssive mesurement to count the network trffic, nd it lso trnsmits nd receives the proe frme. Our pproch hs four gigit Ethernet interfces corresponding to ech frme processor. The lyout of the frme processor is shown in Figure 6. The MAC TxQ receives the dt frmes from the trffic genertor nd lso records tg of ech new frme nd the frme length simultneously. When getting the tg nd the frme length, it will ccumultively clculte the numer of the dt frmes nd totl ytes received, etc., which re used seprtely in Equtions 6, 8, nd 9. Those enle us to chieve the network trffic through Register I/O in rel time. Besides, the MAC TxQ needs to ressemle the dt frmes from 64-it to 8- it wide. Next, the dt frmes will e sent to CAM FSM, nd the dt frmes checked y cyclicl redundncy check (CRC) re trnsmitted to Tri-Mode Ethernet MAC (TEMAC) vi n 8-it wide dt us. The content ddressle memory (CAM) is the core of the CAM FSM. At the eginning of the CAM FSM working, the CAM is initilized firstly. With two stge pipelines, the dt formed y ccumulting the yte which is received y the CAM FSM re used to mtch the specil tgs (64 its) set in the trffic genertor. Through the ove mtching, the mtching

6 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 6 of 10 mrk of the dt frme nd its vlid mrk re recorded. For one thing, the totl dt frme trnsmission time cn e chieved y clock cycles, which is used in Eqution 6. For nother thing, using the vlid mrk cn help us to void invlid sttistics out clock cycles when the tg in the dt frmes is missing. The TEMAC generted y the intellectul property (IP) core of Xilinx is used to process the dt frmes. It sends dt frmes to the GigE Tx nd receives dt frmes from the GigE Rx. TheMACRxQ is similr with the MAC TxQ, which is just in different trnsmission direction. When the MAC TxQ sends dt frme, counter is opened; while the MAC RxQ finishes receiving tht dt frme, the ove counter is closed y the MAC TxQ immeditely. By their collortion, the ltency shown in Eqution 2, which is ccurte to the nnosecond, cn e otined. 4.4 Intervl stretching The intervl stretching is used to dynmiclly djust the interfrme gp, which enles the trffic genertor to generte the perfect network trffic, so the ccurte mesurements cn e conducted. According to the sttisticl lws sed on throughput vrition, our pproch dynmiclly djusts the interfrme gp to generte proe dt frmes nd count network trffic gin nd gin. When it pproches the limit of the network, the network performnce prmeters re chieved. To find n optimized intervl is importnt to get ccurte evlution results. The intervl [, ] represents the interfrme gp intervl determined y the ove sequence of frmes {P 1,P 2,,P n }, which is mesured for certin time. The nd show the clock cycles of the interfrme gp. After the mesurement, four kinds of rtionl situtions cn e determined. The model of intervl stretching is shown in Figure 7. The rrows show the chnges of the interfrme gp. Thefirstoneisthtwhenδ =,ourpprochfils to conduct the mesurement ut while δ =, the mesurement is successful. In Figure 7, it will djust to the interfrme gp intervl [ l, ]. The second one is tht when oth δ = nd δ =, our method fils to perform the mesurements. From Figure7,itwilldjusttotheinterfrmegpintervl [, r ] fter expnding to [, r ]. The ove two situtions usully pper erly with inry serch. Thethirdoneislsothtwhenδ =, our pproch fils to conduct the mesurement ut while δ =, the mesurement is successful. It usully should djust to the interfrme gp intervl [ r, ], tht is to sy, compressing the interfrme gp intervl, which is shown in Figure 7c. The lst one is tht when oth δ = nd δ =, the mesurements re successful. It often should djust to the interfrme gp intervl [ l, ] fter extending to the intervl [ l, ], s we cn see in Figure 7d, ut the ove two situtions often occur in the lte with fine-tuning. The intervl stretching is stted in Algorithm 1. In Step 6, the mesurement expected represents tht when δ =, it fils ut while δ =, it conducts mesurement successfully. l r r l Figure 7 Model of intervl stretching.

7 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 7 of 10 5 Experiments nd nlysis In order to verify the fesiility of our pproch, highspeed network performnce mesurement system is implemented. The FPGA-sed network performnce mesurement pltform is designed on NetFPGA crd version 2 with Virtex II-Pro FPGA device (Xilinx, Sn Jose, CA, USA), which is shown in Figure 8. The NetFPGA is PCI crd which provides low-cost reusle hrdwre pltform for network reserchers. The ottom crd is the NetFPGA in Figure 8. The host computer opertes t Intel Pentium Dul E2200 (2.20 GHz) nd Cent OS 5.4 (Linux kernel ). We connect one network interfce to nother on NetFPGA ord in the experiments for the idel network ndwidth 1 Gps. To fcilitte the nlysis of the results, the visuliztion of network trffic informtion for ech Ethernet interfce nd network performnce prmeters informtion re chieved y the softwre. And we compre our system with nother system using the softwre to send dt frmes for the sme one communiction pth. Besides, similr pproch sed on FPGA [14] is lso compred with our pproch on the NetFPGA. 5.1 Network performnce For the dt frme of different length under different interfrme gp, it is sent for 20,000 times. We compre it with the sme one communiction pth for ltency, throughput, nd pcket loss rte. From Figure 9, the ltency of the given frme length converges to fixed vlue. With the growth of the frme length, the ltency increses ccordingly. It cn lso e found tht the ltency is not directly proportionl to the frme length ccording to the sttistics. Figure 9 Ltency under different frme length. The mesurements of throughput for given frme length under different interfrme gp re shown in Figure 10. It cnefoundthtforgivenfrmelengthunderspecified interfrme gp, the throughput decreses clerly with the growth of interfrme gp. It is ovious tht the downlink throughput is never less thn the upstrem throughput. From the intersection etween the downlink throughput nd upstrem throughput, the mximum throughput of the communiction pth cn e determined. So, the ccurte ottleneck ndwidth cn e gined. The ottleneck ndwidth is 871, 910, nd 931 Mps when the dt frme length is 256, 512 nd 1,024 ytes, respectively. Besides, the frme length under the specific throughput is pproximtely proportionl to the interfrme gp, which is drwn y the scope of the interfrme gp under different frme length. Figure 11 plots the correspondence of interfrme gp nd pcket loss rte for given frme length. It is cler to see tht with the growth of interfrme gp, the pcket loss rte drops to zero nd then tends to e stle under the fixed frme length. To put it simply, the ytes loss rte is only e shown ecuse in the ove experiments, the frmes loss rte re ll zero. Moreover, with the frme length incresing, the pcket loss rte will decline when the mesurements pproch the limit of network; the pcket loss rte lso revels the reltionships etween the downlink throughput nd upstrem throughput, which tells us why the downlink throughput is never less thn the upstrem throughput. On the whole, with the frme length growing, the network performnce of the communiction pth is improved, tht is to sy, leving the throughput incresing nd mking the pcket loss rte decresing. But the incresing ltency is lso pid. Figure 8 The hrdwre of mesurement pltform. 5.2 Performnce stility The network performnce mesurement under the specil frme length nd the fixed interfrme gp is

8 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 8 of 10 Figure 10 Throughput under different frme length. shown in Tle 1. It cn e found tht for given interfrme gp under the mximum throughput, the performnce prmeters of throughput, ltency, nd pcket loss rte re stle with the growth of the numer of frmes. It is ovious tht the network performnce mesurement prmeters under different frme length re credile. 5.3 Performnce comprison In order to fully evlute our pproch, the network performnce mesurement system of our pproch is compred with it using softwre to send proe dt frmes for the sme one communiction pth. The softwre system opertes t the host computer. It uses the linet to cycliclly encpsulte dt frme ccording to the user s configurtions. Then, it forwrds those dt frmes immeditely. Menwhile, in order to monitor the network trffic trnsmitted nd received for ech network interfce, the ove NetFPGA is lso used to count the network trffic in the softwre system. Moreover, we do not wit for the interfrme gp when sending those dt frmes so s to mximize the network performnce, nmely sending ck-to-ck dt frmes to revel the network performnce. Figure 11 Pcket loss rte under different frme length.

9 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 9 of 10 Tle 1 Network performnce mesurement under specil frme length nd interfrme gp Frme length (Bytes) Interfrme gp (numer of clock cycle) Numer of frme (10,000) Downlink throughput (Mps) Upstrem throughput (Mps) Ltency (ns) Frmes loss rte (%) , , , , , , , , , , Bytes loss rte (%) The proe dt frmes sent in the NetFPGA nd the softwre for mximum throughput re presented in Tle 2. When the frme length is 256 ytes, the mximum throughput is 132 Mps in the softwre, which is fr elow it in the NetFPGA; even if the frme length is incresing to 1,024 ytes, the mximum throughput is merely 220 Mps, which is fr less thn the idel network ndwidth 1 Gps. On the contrry, our pproch cn e pplied in highspeed network nd it lso cn e migrted to ten gigit high-speed networks. A similr work sed on FPGA is lso compred with our pproch. The chnnel utiliztion under different pltforms is shown in Tle 3. For the frmes per second, the mximum throughput of 71% of the idel one is given for 64 ytes in [14]. Its ltency is only ccurte to microsecond nd it is merely presented for n Ethernet 100 Mps. But the chnnel utiliztion of our pproch on the NetFPGA cn e 100% of the idel one for 64 ytes under 100 Mps. And the ltency cn e ccurte to the nnosecond. In ddition, when it is deployed in n Ethernet 1 Gps, the mximum throughput of our pproch is 721 Mps under 66 clock cycles for 64 ytes when Tle 2 The proe dt frmes sent in the NetFPGA nd softwre for mximum throughput Frme length NetFPGA Softwre (Byte) Mximum throughput (Mps) Mximum throughput (Mps) , the dt frmes re not missing. It is ovious tht our pproch hs etter performnce thn it. 6 Conclusions In this pper, n FPGA-sed high-speed network performnce mesurement solution for RFC 2544 is proposed. The ctive mesurement method is employed to send proe dt frmes. The pssive mesurement method is used to monitor network trffic of ech Ethernet interfce. Our rchitecture lso supports CAM interfce to mtch the specil tgs with two stge pipelines, which helps us to clculte the throughput nd ltency precisely. A SRAM interfce is provided to ccess the dt frme, which enles our pproch to e pplied in high-speed network. An FPGA-sed prototype is lso implemented for evlution. It lso cn e migrted to ten gigit high-speed networks. The experimentl results show tht the network performnce prmeters cn e mesured ccurtely. Compring with the network performnce mesurement using softwre to send proe dt frmes nd similr work sed on FPGA, it cn e used in high-speed network nd the ltency cn e ccurte to the nnosecond. In order to e pplied in the rel network widely, generting more complex nd rel network trffic ccording to the users choice will e considered in our future reserch. Extending our method relily lso will e tken into ccount. Thus, more perfect performnce will e provided for the users. Tle 3 The chnnel utiliztion under different pltforms Frme length (Byte) Performnce index FPGA NetFPGA 64 Chnnel 71% 100% utiliztion

10 Wng et l. EURASIP Journl on Wireless Communictions nd Networking 2015, 2015:2 Pge 10 of 10 Competing interests The uthors hve declred tht no competing interests exist. Authors informtion Yong Wng ws orn in He received his PhD in Est Chin University of Science nd Technology, Shnghi, Chin, in He is currently professor t Guilin University of Electronic Technology. His reserch interests minly include intelligent control ppliction nd network mngement. Yong Liu ws orn in He received his B.S in Wuhn Textile University, Wuhn, Chin, in He is currently grdute student in the Deprtment of Computer Science nd Engineering t the Guilin University of Electronic Technology. His reserch interest is minly on compute network nd ppliction. To Xioling ws orn in She received her B.S nd M.S in Guilin University of Electronic Technology, Guilin, Chin, in 1999 nd She is currently n ssocite professor t Guilin University of Electronic Technology. Her reserch interest is minly on network security. Qin He ws orn in He received his PhD in Beijing University of Posts nd Telecommunictions, Beijing, Chin, in He is currently professor t Guilin University of Electronic Technology. His reserch interests lie in network security nd distriute computing. Acknowledgements The mnuscript ws received lst Novemer 2013; ccepted Ferury This work is supported y the Ntionl Nturl Science Foundtion of Chin (No , , nd ). Author detils 1 CSIP Gungxi Center, Guilin University of Electronic Technology, Guilin , Chin. 2 College of Computer Science nd Engineering, Guilin University of Electronic Technology, Guilin , Chin. 3 College of Informtion nd Communiction, Guilin University of Electronic Technology, Guilin , Chin. 12. ZCi,WZho,JYinetl.,Using Pssive Mesuring to Clirte Active Mesuring Ltency, Informtion Networking, Convergence in Brodnd nd Moile Networking (Springer Berlin Heidelerg, Berlin, Germny, 2005), pp YA Wng, C Hung, J Li et l., Queen: Estimting Pcket Loss Rte etween Aritrry Internet Hosts, Pssive nd Active Network Mesurement (Springer Berlin Heidelerg, Berlin, Germny, 2009), pp CB Both, C Bttisti, FA Kuentzer et l., FPGA implementtion nd performnce evlution of n RFC 2544 complint Ethernet test set. Int J High Perform Syst Architecture 2(2), (2009) 15. J Wu, J Zhng, Z Hn et l., The Implementtion of High Speed Ethernet Trffic Genertor Bsed on FPGA. Adv Mter Res 433, (2012) 16. A Tockhorn, P Dnielis, D Timmermnn, A Configurle FPGA-Bsed Trffic Genertor for High-Performnce Tests of Pcket Processing Systems (ICIMP 2011, St.Mrten, The Netherlnds Antilles, 2011), pp A Friedl, S Uik, A Kprvelos et l., Relistic Pssive Pcket Loss Mesurement for High-Speed Networks, Proceedings of the First Interntionl Workshop on Trffic Monitoring nd Anlysis (Springer Berlin Heidelerg, Berlin, Germny, 2009), pp F Strohmeier, P Dorfinger, B Trmmell, Network Performnce Evlution Bsed on Flow Dt (IEEE IWCMC 2011, Istnul, Turkey, 2011), pp T Jones, Network Performnce Mesurement: Accurcy in Highspeed Provide Networks (IEEE MIPRO 2011, Optij, Croti, 2011), pp MD Schiffmn, The Linet Pcket Construction Lirry, doi: / Cite this rticle s: Wng et l.: An FPGA-sed high-speed network performnce mesurement for RFC EURASIP Journl on Wireless Communictions nd Networking :2. Received: 23 Decemer 2013 Accepted: 28 August 2014 Pulished: 26 June 2015 References 1. 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