http://www.artistembedded.org/fp6/ ARTIST Workshop at DATE 06 W4: Design Issues in Distributed, CommunicationCentric Systems Modelling Networked Embedded Systems: From MPSoC to Sensor Networks Jan Madsen Technical University of Denmark Multiprocessor SystemonChip % 0 574.08847 4:7908 41,.!,2 1
Software/Hardware architecture mem private pe 1 application application Software Hardware Periphery shared private private private Cache CPU I/O RTOSAPIs RTOS drivers Int Timer Timer Bus CTRL HW/SW Plattform Bus ce 1 4:7908 41 #4 17389 %&7,:38. 0 Platformbased design 1 2 3 4 3 4 os os mapping 1 2 os a b c a b c L 1 L 2 R 1 R 2 R 3 L 3 2
Outline The #%$ framework basic model Modelling multiprocessor SystemonChip Simple multi media terminal Modelling wirekess sensor networks Simple examples Summary #%$ objectives Systemlevel modeling framework Bridging, Application RTOS Execution platform Processing elements NoC Supporting Systemlevel analysis Early design space exploration 7488, 07 459 2,9 43 3
Systemlevel analysis Consequences of RTOS selection scheduling, synchronization and resource allocation policies Processor selection General purpose, semicustom or dedicated hardware Network selection topologies and communication protocols. Task mapping to processors software or hardware On Performance Area Memory profile Power Basic #%$ model rtos a rtos b rtos c rtos d network 4
Uniprocessor... rtos a Framework to experiment with different RTOS strategies Focus on analysis of timing and resource sharing Abstract software model, i.e. no behavior/functionality Easy to create tasks and implement RTOS models Based on SystemC System model Task messages: ready finished RTOS commands: run preempt Resume rtos 5
Task model C p >0 idle C p ==0 ready ready!run!preempt & C r >0 C r ==0 finish running run preempt resume preempt!resume rtos scheduler Scheduling model Aim: Simple way to describe the scheduling algorithm Scheduler should only handle one message at a time Schedulers: RM DM EDF static 6
Data dependencies synchronizer scheduler Resource sharing synchronizer allocator scheduler 7
Multiprocessors Communication latency? synchronizer allocator scheduler allocator scheduler Communication modelling Fully interconnected or pointtopoint Allows concurrent communication 1 2 a b a 1 b 2 8
Busbased Shared resource Communication modelling 1 2 2 a 1 a b bus m x b 2 Communication modelling Torus network Concurrent, shared and multihop 1 2 2 R1 a 1 L 1 R 2 a b L 2 R 3 b 2 L 1 L 2 R 1 R 2 R 3 L 3 9
#%$ Framework Application Applicat ion RTOS IO adaptor model Application τ... τ τ 1 n IO IO port1 IO... port2 IO portn IO adaptor model RTOS SoC communication interface (i.e. OCP 2.0) IO adaptor RTOS model Intermediate Intermediate adapter1 adapter2 Synchronnizer Resource Allocator IO adaptor model SoC allocator Application RTOS IO adaptor model Scheduler SoC Master resource usage buffer Intermediate adaptern IO adaptor model HW model OCP IO device Slave #%$ Simulation framework based on SystemC #%$ PE module: Application OS IO ports (OCP 2.0 interface) IO device drivers #%$ Communication module: Network topology and protocol Network adapters IO ports (OCP 2.0 interface) Applications of #%$: MPSoC(NoCexploration) Wireless sensor networks Automotive systems (TT vs. ET) Dynamic reconfiguration SoC scheduler SoC communication interface (OCP) SoC communication layer model Outline The #%$ framework basic model Modelling multiprocessor SystemonChip Simple multi media terminal Modelling wirekess sensor networks Simple examples Summary 10
Design of a handheld multimedia terminal Application JPEG Encoder JPEG Decoder MP3 Decoder GSM Encoder GSM Decoder # tasks 5 6 16 53 34 Deadline 250 ms 500 ms 25 ms 20 ms 20 ms JPEG Decoder 0 1 2 3 4 5 [Application from Marcus Schmitz, TU Linkoping] Case study: Execution platform t t t t os t os t os t t t t PE1 PE2 PE3 PE4 PE5 PE6 PE GPP0 GPP1 GPP2 FPGA Frequency (MHz) 25 10 6.6 2.5 2.5 OS RM (Rate Monotonic) EDF (Early Deadline First) 11
Case study: Architectures PE1 PE2 PE3 PE4 PE5 PE6 Arch1 IP Type GPP0 OS RM Tasks 21 15 15 18 13 32 Arch2 IP Type GPP0 FPGA FPGA FPGA OS RM RM RM RM Tasks 18 15 21 18 18 24 Arch3 IP Type FPGA GPP0 GPP0 OS RM RM RM Tasks 15 15 15 18 19 32 Arch4 IP Type FPGA GPP0 GPP0 OS EDF EDF EDF Tasks 15 15 15 18 19 32 Processor Utilization Arch1 Arch2 Arch3 Arch4 12
Bus Contention Memory Profile of Arch3 32bit Words (Instruction + Dynamic Memory) Time (µs) 13
Simple memory model τ X τ 1 2 3 Y τ (a) Memory@PE1 X PDM( 1) X Y X Y PDM( 2) Y PDM( 3) PM( 3) PM( 2) PM( 1) time (b) PE1 1 2 3 time Memory@PE1 PE1 bus y x PDM( 1) io io PDM( 3) PM( 3) PM( 1) time 1 io io 3 X Y (c) PE2 io 2 io time Memory Profile 32bit Words (Instruction + Dynamic Memory) Time (µs) Arch1 ~ 40% Arch2 Time (µs) 14
Outline The #%$ framework basic model Modelling multiprocessor SystemonChip Simple multi media terminal Modelling wirekess sensor networks Simple examples Summary Modelling wireless sensor networks rtos a rtos b rtos c rtos d network 15
Sensor network model Sensor node model 16
Energy modeling Communication example Send node τ 1 sτ 2 Wireless Network Receive node rτ 3 τ 4 τ 5 synch. synch. allocator allocator scheduler scheduler 17
Modeling radio communication 4/0 3 9 0 $57494.4 $03/07 803/!7494.4.8 4 4.8.8 % 5 % 5 % 5 % / % / % / % / % /.,77 07 80380 570,2 0 /,9,!& %7,38 ;07 CSMA Protocol for sending!send bo_counter>0 cs_counter>0 idle send back off bo_counter==0!channel clear carrier sense channel clear & cs_counter==0 pr_counter>0 data_counter==0 Tx preamble pr_counter==0 Tx data data_counter>0 18
$03/07!7494.4!& %7,38 ;07 Modeling radio communication.8 4 4.8.8 % 5 % 5 % 5 % / % / % / % / % /.,77 07 80380 570,2 0 /,9, #0.0 ;07!7494.4 54 54 54 8 3 8 3 # / # / # / # / # / 54.,330 8 3. 743 0 /,9,!& %7,38 ;07 Sensor network example 19
Example 1: Simple broadcast $03/ 3 9,8,.,. 11.,77 07 8038 3 97,382 9 570,2 0 97,382 9 /,9, #0.0 ; 3 9,8 54 3 8 3. 743 0 70.0 ;0 /,9, 55.,9 43 9,8 70,/ 7:33 3 57002590/ 80 1 80 157002590/ 0us 100us 200us 300us 400us 500us 600us 700us 800us 900us Node1_Processing_Task 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Node1_Receive_Protocol 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Node1_Receive_Task 0 0 0 0 0 0 0 0 Node1_Send_Protocol 2 1 3 4 0 Node1_Send_Task 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 Node2_Receive_Protocol 1 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0 1 0 Node2_Receive_Task 0 0 0 0 0 4 4 4 4 4 0 0 0 0 0 0 0 Node3_Receive_Protocol 1 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0 1 0 Node3_Receive_Task 0 0 0 0 0 4 4 4 4 4 0 0 0 0 0 0 0 Example 2: Radio interference Node1_Receive_Protocol Node1_Receive_Task Node1_Send_Protocol 0us 100us 200us 300us 400us 500us 600us 700us 800us 900us Node1_Send_Task 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 Node2_Receive_Protocol Node2_Receive_Task Node2_Send_Protocol $03/ 3 9,8,.,. 11.,77 07 8038 3 97,382 9 570,2 0 97,382 9 /,9, #0.0 ; 3 9,8 54 3 8 3. 743 0 70.0 ;0 /,9, 1 0 1 0 1 0 1 0 1 2 3 0 0 0 0 0 0 4 4 4 4 4 4 4 4 0 2 1 3 4 0 Node2_Send_Task 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 Node3_Receive_Protocol 1 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 2 3 0 Node3_Receive_Task 0 0 0 0 0 4 4 4 4 4 0 0 0 0 0 4 4 4 4 4 0 Node4_Receive_Protocol 1 0 1 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 2 3 0 Node4_Receive_Task 0 0 0 0 0 4 4 4 4 4 0 0 0 0 0 4 4 4 4 4 0 Node5_Receive_Protocol 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 0 Node5_Receive_Task 0 0 0 0 0 0 0 0 0 0 0 4 4 4 4 4 4 0 1 0 55.,9 43 9,8 70,/ 7:33 3 57002590/ 80 1 80 157002590/ 2 1 2 1 2 1 3 4 0 20
Example 3: Network routing Time Node3_Receive_Protocol=1 Node3_Receive_Task=0 Node3_Routing_Task=0 Node3_Forward_Protocol=0 Node3_Forward_Task=0 Node3_Send_Protocol=1 Node3_Send_Task=2 Node2_Receive_Protocol=0 Node2_Receive_Task=0 Node2_Routing_Task=0 Node2_Forward_Protocol=0 Node2_Forward_Task=0 Node1_Receive_Protocol=0 Node1_Receive_Task=0 Example 3: Routing $03/ 3 9,8,.,. 11.,77 07 8038 3 97,382 9 570,2 0 97,382 9 /,9, #0.0 ; 3 9,8 54 3 8 3. 743 0 70.0 ;0 /,9, 55.,9 43 9,8 70,/ 7:33 3 57002590/ 80 1 80 157002590/ 0 300 us 601 us 901 us 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 0 0 0 4 4 4 4 4 4 4 0 0 0 0 0 0 0 0 0 1 3 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 1 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 1 0 0 0 0 4 4 4 4 4 0 0 0 0 0 0 0 0 0 2 1 3 4 0 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 1 0 1 0 1 2 3 0 1 0 1 2 3 0 1 0 1 0 1 0 1 0 0 0 0 4 4 4 4 4 0 0 4 4 4 4 4 4 4 4 0 0 0 0 0 21
ime Node3_Receive_Protocol=1 Node3_Receive_Task=0 Node3_Routing_Task=0 Node3_Forward_Protocol=0 Node3_Forward_Task=0 Node3_Send_Protocol=2 Node3_Send_Task=2 Node2_Receive_Protocol=1 Node2_Receive_Task=0 Node2_Routing_Task=0 Node2_Forward_Protocol=0 Node2_Forward_Task=0 Node1_Receive_Protocol=1 Node1_Receive_Task=0 Example 3: Battery shortage $03/ 3 9,8,.,. 11.,77 07 8038 3 97,382 9 570,2 0 97,382 9 /,9, #0.0 ; 3 9,8 54 3 8 3. 743 0 70.0 ;0 /,9, 55.,9 43 9,8 70,/ 7:33 3 57002590/ 80 1 80 157002590/ 0 321 us 643 us 965 us 1 0 1 0 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 4 4 0 0 0 0 0 0 0 0 0 1 3 4 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 0 1 0 1 0 1 2 3 0 1 0 0 0 4 4 4 4 4 0 5 0 0 5 0 2 1 3 4 0 4 4 4 4 4 4 4 4 4 4 + 5 Node 2 runs out of battery 1 0 1 0 1 2 3 0 1 0 1 2 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 4 4 4 4 4 0 0 4 4 4 0 0 0 0 0 0 Summary Systemlevel modeling framework Bridging, Application RTOS Execution platform Processing elements NoC Supporting Systemlevel analysis Early design space exploration Applications MPSoC Wireless Sensor Networks 22
Summary Work in progress Mixedlevel simulation together with MPARM from University of Bologna (Luca Benini) Linking to formal modelling based on UppAal from University of Aalborg (Kim G. Larsen) Mixed TT and ET communication models and hierarchical schedulers together with Technical University of Linkoping (Petru Eles) To be used in the Hogthrob project Thursdays Keynote on Wireless Sensor Networks Acknowledgements ARTS Shankar Mahadevan (PhD student) Kashif Virk (PhD student) Michael Storgaard (MSc. student) Knud Hansen (MSc. student) Mercury Gonzalez (MSc. student) 23