Laboratoryof Electronics, Antennas and Telecommunications (UMR 7248)

Transcription

1 INSIS Laboratoryof Electronics, Antennas and Telecommunications (UMR 7248) LEAT - Université Nice-Sophia Antipolis, UMR CNRS 7248 Campus Sophi@Tech - Bâtiment Forum 930 route des Colles, BP 145, Sophia Antipolis cedex tél.+33.(0) , fax.+33.(0) leat.unice.fr

2 INSIS Campus Sophia Antipolis MCSOC Team : Research activities System Modeling and design for Communicating Objects Contact: Cécile Belleudy [email protected] LEAT - Université Nice-Sophia Antipolis, UMR CNRS 7248 Campus Sophi@Tech - Bâtiment Forum 930 route des Colles, BP 145, Sophia Antipolis cedex tél.+33.(0) , fax.+33.(0) leat.unice.fr

3 MCSoC Team Permanent ber M. Auguin C. Belleudy S. Bilavarn D. Gaffé A. Giulieri L. Kwiatowski F. Muller A. Pegatoquet W. Tatinian F.Verdier Non Permanent member H. Affes N. Trong U. Cerasani M. Abdelmouna B. Ouni C. Chaabane K. Baathi H. Nguyen C. Foucher O. Mbarek 3

4 Research topics Wireless sensor network Autonomous System Projects : GEODES, GRECO Heterogeneous System (MPSoC) Multiprocessors, reconfigurable unit. Projects : Openpeople, HELP, COMCAS, Respected, HOPE Video application (H262), software radio,... HPRC Reconfigurable Architecture Auto-adaptivity Data and code distribution Projects : HARDMAHN FOSFOR BENEFIC 4

5 Axe 1 : Energy Optimization in communicating object Objective Model and design of low power (Energy-aware) system Contexte Monocore and Multicore architecture, reconfigurable unit (IP), wireless sensor network, energy harvesting Problematic Low power scheduling, System level Modeling Approach for low power design Dynamic Reconfiguration and energy Power consumption management in WSN, Temperature management for multicore SoC architecture 28-janv.-13 Modélisation et Conception Système d Objet Communiquant 5

6 Embedded system : Multicores and power management Low power scheduling policy for Multicores Architectutre (DFVS, DPM) Multicores Architecture Configuration Unit INSTR DATA PE_1 Type 1 INSTR DATA OSoC PE_2 Type 1 Reconfigurable Data Network INSTR DATA PE_1 Type 2 AG AG AG AG AG MMU I/O ctrl I/O I/O ctrl I/O European Project COMCAS Main Instruction ory ANR Openpeople Project Instr Instr Instr Instr Instr Instr Main Data memory Linux Implementation => Definition of OS services dedicated for managing the power consumption Outcomes : - Approach limitation - Applicability domain - Definition of more realistic Policy in relation with application domain Example : => Gain : 56% on a H264 décoder HW/SW Exploration of low power architecture at high level (meta model) : Adequation architecture vs scheduling => Verification of requirements with reliability => autonomy => power peak => average power => energy 6

7 Objective : Simulation of SoCfunctional architecture and power consumption => components of the power architecture and control (in SystemC-TLM) Checking of functional and power properties Results : TLM Power architecture modeling(systemc) ANR Project : HELP- HOPE TLM Library : components for power (power switches, level shifters, power controllers abstraction of standard like UPF-CPF) TLM modeling tool Simulation tool Extension : Thermal aspect, 3D circuit. Modélisation et Conception Système d Objet Communiquant 7

8 Autonomous wireless sensor network Energy harvester ANR Project : GRECO Communication Protocol vsenergy harvesting (PHY, MAC, Routing) Definition and implementation of power manager (global view) : QoS vs Power Heterogeneous Modeling of node : systemc/systemc-ams(rf) Difficulty to link model with discrete and continuous time => Different level of simulation (Accuracy) => Architecture exploration (energy harvester, battery capacity, RF, protocol) => Network Simulation : binding to OMNET Gain : 50% on data rate 8

9 Objectives : Model and design dynamic reconfigurable systems (FPGA) Context Auto-adaptive real time systems, High Performance Reconfigurable Computing (HPRC) Problematic : Axe 2 : Reconfigurable, auto-adaptive systems Speedup of dynamic reconfiguration Validation of reconfigurable architectures Design space Exploration tool Methodology for application mapping (digital signal processing) on heterogeneous architectures Reference A B C D E Name Reed- Solomon AES IIR FFT Basic DES 9

10 Axe 2 : Reconfigurable, auto-adaptive systems Project ANR FOSFOR, ARDHMAN, BENEFIC Developpment of IP FaRM (Fast Reconfiguration Manager) to speed up the management of the reconfigurability «RecoSim» Simulator : definition of hardware/software region Hard and soft real time verification Design space exploration Methodology for reconfigurable architecture : FoRTReSS (Flow for Reconfigurable architectures in Real-time SystemS) - tool Methodology for deploying digital signal processing applications on heterogeneous architectures Methods, tools and library for programming Setting up a guide of recommendations to assess the machine which present the best compromise for a given algorithm 10

11 Axe 3 : Soc Validation by synchronous approach Objective Behavioral formal verification of IP blocs IP for SoC Context smart card : contactless, secured, multifunction, low energy budget Problematic Specification and validation with modular synchronous languages Modeling and architecture of control Automatic Exploration of state space governing all possible behaviors Verification a priori and a posteriori of global behavior recherche/clem_tools.html 11

12 Axe 4 : Modelingand design RF front Objectives Modeling and design of analog/rf system for wireless application sans Context wireless transmission, biomedical Problematic Electrical Modeling of RF blocs, architecture exploration Modeling of heterogeneous systems Analog/digital Systems (Projet GRECO) Electronic and Electromagnetic systems Electrical/physical Systems : cochlear implant Analog and RF Design Codesign of circuits and antenna (themes CMA/S2DS2A) 12

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