Academic Course Description

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1 Academic Course Description Course (catalog) description: IP cores and application specific design is becoming the order of the day. Because of usefulness of this for both VLSI and embedded students this subject is provided Compulsory/Elective course: Elective course for M. Tech (VLSI) II year students Credit hours: 3 credits Course coordinator: Mr. P.Vijayakumar, Assistant Professor (Sr.G), Department of ECE Instructor(s) SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2110 SYSTEM ON CHIP DESIGN Third Semester, (Odd semester) Name of the instructor Class handling M.TECH Mr. P.Vijayakumar VLSI A&B Relationship to other courses Pre-requisites Office location TP12S8 Office phone : Basic knowledge in system design Assumed knowledge : Basic Knowledge in embedded system Following courses Reference Books : Nill Vijayakumar.p@ktr.srmuniv.ac.in Consultation Day AM to 12.00PM 1. Hoi-jun yoo, Kangmin Lee, Jun Kyoung kim, Low power NoC for high performance SoC desing,crc press, Vijay K. Madisetti Chonlameth Arpikanondt, A Platform-Centric Approach to System-on-Chip (SOC) Design, Springer, Class schedule: Four 50 minutes Lecture sessions per week Section VLSI A&B Schedule Day-1 2 nd hr Day-3 5 th hr Day-4 1 st hr Day-5 2 nd hr Page 1 of 5

Tech (VLSI) II year students Credit hours: 3 credits Course coordinator: Mr. P.Vijayakumar, Assistant Professor (Sr.

2 Professional component General - 0% Basic Sciences - 0% Engineering sciences & Technical arts - 0% Professional subject - 100% Broad area: Communication Signal Processing Electronics VLSI Embedded Test Schedule - Theory S. No. Test Portions Duration 1 Cycle Test Sessions 1 to 12 1 hr 40 min 2 Model Exam sessions 13 to 60 3 hrs Course objectives 1. To learn System on chip fundamentals, their applications. 2. To gain knowledge on NOC design. 3. To learn the various computation models of SOCs Session plan UNIT I - INTRODUCTION (9 hours) Introduction to SoC Design., Platform-Based SoC Design., Multiprocessor SoC and Network on Chip, Low- Power SoC Design 1 Introduction to SoC Design 2 Introduction to SoC Design 3 Introduction to SoC Design 4 Platform-Based SoC Design 5 Platform-Based SoC Design 6 Multiprocessor SoC and Network on Chip 7 Multiprocessor SoC and Network on Chip Page 2 of 5

To learn System on chip fundamentals, their applications. 2. To gain knowledge on NOC design. 3.

3 8 9 Low-Power SoC Design Low-Power SoC Design UNIT II - SYSTEM DESIGN WITH MODEL OF COMPUTATION AND CO-DESIGN (9 hours) System Models, Validation and Verification, Hardware/Software Codesign Application Analysis, Synthesis 10 System Models 11 System Models 12 Validation and Verification References [1] 13 Hardware/Software Codesign 14 Application Analysis 14 Application Analysis 16 Application Analysis 17 Synthesis 18 System Models-part2 UNIT III - COMPUTATION COMMUNICATION PARTITIONING AND NETWORK ON CHIP- BASED SOC (9 hours) Communication System: Current Trend, Separation of Communication and Computation. Communication- Centric SoC Design, Communication Synthesis, Network-Based Design, Network on Chip, Architecture of NoC 19 Communication System 20 Current Trend, 21 Separation of Communication and Computation References [1] 22 Communication-Centric SoC Design Page 3 of 5

Application Analysis 17 Synthesis 18 System Models-part2 UNIT III - COMPUTATION COMMUNICATION PARTITIONING AND NETWORK ON CHIP- BASED SOC (9 hours) Communication System: Current Trend, Separation of

4 23 Communication-Centric SoC Design 24 Communication Synthesis 25 Network-Based Design, Network on Chip, Architecture of NoC Architecture of NoC UNIT IV - NOC DESIGN (9 hours) Practical Design of NoC, NoC Topology-Analysis Methodology, Energy Exploration, NoC Protocol Design, Low-Power Design for NoC: Low-Power Signaling, On-Chip Serialization, Low-Power Clocking, Low- Power Channel Coding, Low-Power Switch, Low-Power Network on Chip Protocol 28 Practical Design of NoC 29 NoC Topology 30 Analysis Methodology 31 Energy Exploration 32 NoC Protocol Design References [1] 33 Low-Power Design for NoC: Low-Power Signaling, On-Chip Serialization 34 Low-Power Clocking, Low-Power Channel Coding 35 Low-Power Switch, 36 Low-Power Network on Chip Protocol UNIT V - NOC /SOC CASE STUDIES (9 hours) Real Chip Implementation-BONE Series-,BONE 1-4, Industrial Implementations-,Intel s Tera-FLOP 80- Core NoC, Intel s Scalable Communication Architecture, Academic Implementations-FAUST, RAW; design case study of SoC digital camera Page 4 of 5

Coding, Low-Power Switch, Low-Power Network on Chip Protocol 28 Practical Design of NoC 29 NoC Topology 30 Analysis Methodology 31 Energy Exploration 32 NoC Protocol Design References [1] 33

5 37 Real Chip Implementation 38 BONE Series-,BONE 1-4, 39 BONE Series-,BONE 1-4, 40 Industrial Implementations-,Intel s Tera 41 FLOP Core NoC 43 Intel s Scalable Communication Architecture 44 Academic Implementations-FAUST, RAW; 45 design case study of SoC digital camera Evaluation methods Cycle Test - 20% Model Test - 20% Term Paper/surprise test - 10% Final exam - 50% Prepared by: Mr. P.Vijayakumar, Assistant Professor (Sr.G), Department of ECE Dated: 25 th June 2014 Revision No.: 00 Date of revision: NA Page 5 of 5

digital camera Evaluation methods Cycle Test - 20% Model Test - 20% Term Paper/surprise test - 10% Final exam - 50% Prepared by: Mr.

Systems on Chip Design

Systems on Chip Design College: Engineering Department: Electrical First: Course Definition, a Summary: 1 Course Code: EE 19 Units: 3 credit hrs 3 Level: 3 rd 4 Prerequisite: Basic knowledge of microprocessor/microcontroller