MOS Field-Effect Transistors (MOSFETs)

MOS Field-Effect Transistors (MOSFETs) 1

BJT Bipolar Junction Transistor MOSFET Metal Oxide Semiconductor Field Effect Transistor É o transistor mais utilizado, principalmente em circuitos integrados Requer menor área no circuito integrado Processo de fabricação mais simples Consumo de energia menor Circuitos Integrados VLSI Very Large Scale Integration 200.000.000 transistores em um único circuito integrado Tipos de MOSFETS: JFET Junction FET Depletion - Depleção Enhancement - Crescimento 2

t ox = 2 a 50 nm W = 0. 2 a 100 μm L = 0. 1a 3 μm Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) crosssection. Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm. 3

Operação do transistor sem tensão no gate Resistência do canal = 10 12 Ω 4

Criação do canal V t tensão de limiar ou threshold voltage V t = 0,5 a 1 V Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate. 5

Operação com baixa tensão v DS Figure 4.3 An NMOS transistor with v GS > V t and with a small v DS applied. The device acts as a resistance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS V t and thus i D is proportional to (v GS V t ) v DS. Note that the depletion region is not shown (for simplicity). 6

Operação com baixa tensão v DS Qual o valor da resistência entre dreno e fonte em cada reta? v GS V t - tensão efetiva de gate Figure 4.4 The i D v DS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, v DS, is kept small. The device operates as a linear resistor whose value is controlled by v GS. 7

Figure 4.5 Operation of the enhancement NMOS transistor as v DS is increased. The induced channel acquires a tapered shape, and its resistance increases as v DS is increased. Here, v GS is kept constant at a value > V t. 8

Figure 4.6 The drain current i D versus the drain-to-source voltage v DS for an enhancement-type NMOS transistor operated with v GS > V t. 9

Figure 4.7 Increasing v DS causes the channel to acquire a tapered shape. Eventually, as v DS reaches v GS V t the channel is pinched off at the drain end. Increasing v DS above v GS V t has little effect (theoretically, no effect) on the channel s shape. 10

Figure 4.8 Derivation of the i D v DS characteristic of the NMOS transistor. 11

ε C ox ε = t 11 ox = 3. 45 10 F / ox ox m Capacitância por unidade de área na região do canal Permissividade do óxido de silício t ox Espessura da camada de óxido de silício A capacitância da faixa de largura dx é igual a Wdx C ox A quantidade de carga no canal, nesta região é igual a capacitância desta faixa multiplicada pela tensão efetiva no canal neste ponto [ vgs v( x) Vt ] dq = C ox ( Wdx)[ vgs v( x) Vt ] O campo elétrico produzido pela tensão v DS no ponto x é igual a: dv( x) E( x) = dx 12

O campo elétrico E(x) faz com que a carga dq se mova em direção ao dreno com uma velocidade dx dt = μ E( x) = μ n n dv( x) dx A corrente de drift resultante pode ser calculada como i dq dq dx = = = μnc dt dx dt ox dv( x) W[ vgs v( x) Vt ] dx A corrente de dreno é então i D = i = μ C n ox dv( x) W[ vgs v( x) Vt ] dx Rearranjando esta equação i D dx = μncoxw [ vgs v( x) Vt ] dv( x) 13

Integrando os dois lados desta equação de x = 0 até x = L correspondendo a v(0) = 0 até v(l) = v DS L iddx 0 v = DS n 0 μ C oxw [ vgs v( x) Vt ] dv( x) Temos a equação do FET na região de triodo i D = ( μ C n ox W )( L )[( v GS V ) v t DS 1 2 v DS 2 ] Para a região de saturação tem-se v DS = v GS V t id 1 W 2 = ( μncox )( )( vgs Vt ) 2 L K ' n = μ C n ox Parâmetro de transcondutância do processo 14

Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device. 15

Símbolos do MOSFET Figure 4.10 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant. 16

Carracterística i D x v DS id = 1 2 ' W Kn( L )( vgs 2 Vt ) i D = K W ( )[( v L 1 2 n ' GS Vt ) vds vds 2 ] ' W i D = Kn( )( vgs Vt ) vds L Figure 4.11 (a) An n-channel enhancement-type MOSFET with v GS and v DS applied and with the normal directions of current flow indicated. (b) The i D v DS characteristics for a device with k n (W/L) = 1.0 ma/v 2. 17

Característica i D x v DS id = 1 2 ' W Kn( )( vgs L 2 Vt ) i D = ' W K ( )[( ) 1 2 n v GS V t v DS v ] L 2 DS ' W i D = Kn( )( vgs Vt ) vds L r DS = K ' n W L 1 ( V GS V ) t = K ' n 1 W V L OV V OV = VGS Vt Gate to source overdrive voltage 18

Região de saturação id = 1 2 ' W Kn( L )( vgs 2 Vt ) Figure 4.12 The i D v GS characteristic for an enhancement-type NMOS transistor in saturation (V t = 1 V, k n W/L = 1.0 ma/v 2 ). 19

Circuito equivalente para grandes sinais do MOSFET Figure 4.13 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation region. 20

Figure 4.14 The relative levels of the terminal voltages of the enhancement NMOS transistor for operation in the triode region and in the saturation region. 21

Modulação do Comprimento do Canal id = 1 2 ' W Kn( L )( vgs 2 Vt ) Figure 4.15 Increasing v DS beyond v DSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by DL). 22

23 Figure 4.16 Effect of v DS on i D in the saturation region. The MOSFET parameter V A depends on the process technology and, for a given process, is proportional to the channel length L. Tensão de Early (J. M. Early) V A 2 2 1 ) )( ( ' t GS n D V v L W K I = ) ( ) )( ( ) ( ' DS A t GS n DS A D DS A D D D v V V v L W K v V I v V I I i 1 1 2 1 1 1 2 + = + = + = 2 2 1 ) )( ( ' t GS n A D A o V v L W K V I V r = =

r o V = I A D = 1 2 K ' n W ( L V A )( v GS V t ) 2 Figure 4.17 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance r o. The output resistance models the linear dependence of i D on v DS and is given by Eq. (4.22). 24

Figure 4.18 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body. (d) The MOSFET with voltages applied and the directions of current flow indicated. Note that v GS and v DS are negative and i D flows out of the drain terminal. 25

Equações do FET canal P Região de Triodo: vgs V t v DS v GS V t i D = K W ( )[( v L 1 2 ' p GS Vt ) vds vds 2 ] Região de Saturação: vgs V t vds vgs Vt ' W i D = K p( )( vgs Vt ) v L DS 26

Figure 4.19 The relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region. 27

Exercício 4.8 V t = -1 V K p = 60 μa/v 2 W/L = 10 Figure E4.8 28

Body Effect Em um circuito integrado do tipo NMOS o substrato é conectado à tensão mais negativa do circuito, impedindo assim a condução do diodo de substrato para fonte. Esta polarização reversa (V SB ) tem como efeito, a redução da profundidade do canal, afetando portanto a corrente de dreno. O efeito de V SB é geralmente representado como uma alteração na tensão de limiar. V t cresce com o aumento de V SB. 29

Efeitos da Temperatura V t cai 2 mv para cada 1 o C de aumento da temperatura. K diminui com o aumento da temperatura. A corrente de dreno diminui com o aumento da temperatura. 30

Breakdown (Avalanche) 1 A junção pn entre dreno e substrato entra em avalanche para tensões entre 20 V e 150 V. 2 Quando a tensão entre gate e fonte atinge 30 V, rompe-se a rigidez dielétrica do óxido de silício na região canal, danificando definitivamente o dispositivo. Isto pode ocorrer mesmo com eletricidade estática. 31

Table 4.1 32

Exemplo 4.2 Faça I D = 0,4 ma e V D = 0,5V Dados: V t = 0,7 V μ n C ox = 100 μa/v 2 L = 1 µm W = 32 µm Figure 4.20 Circuit for Example 4.2. 33

Exemplo 4.3 Faça I D = 80 µa. Calcule R e V D. Dados: V t = 0,6 V μ n C ox = 200 μa/v 2 L = 0,8 µm W = 4 µm Figure 4.21 Circuit for Example 4.3. 34

Exercício 4.12 Como continuação do exemplo anterior, com R = 25 KΩ, I D = 80 µa em Q1. Calcule a corrente de dreno em Q 2. Dados: V t = 0,6 V μ n C ox = 200 μa/v 2 L = 0,8 µm W = 4 µm Figure E4.12 35

Exemplo 4.4 Faça V D = 0,1V e projete o circuito. Qual a resistência entre dreno e source neste ponto de operação? Dados: V t = 1 V K n (W/L) = 1 ma/v 2 Figure 4.22 Circuit for Example 4.4. 36

Exemplo 4.5 Analise o circuito. Dados: V t = 1 V K n (W/L) = 1 ma/v 2 Figure 4.23 (a) Circuit for Example 4.5. (b) The circuit with some of the analysis details shown. 37

Exemplo 4.6 Projete o circuito para que o transistor opere na região de saturação com V D = 3 V e I D = 0,5 ma. Qual a máxima resistência R D que ainda mantém o transistor na região de saturação? Dados: V t = -1 V K p (W/L) = 1 ma/v 2 Figure 4.24 Circuit for Example 4.6. 38

Exemplo 4.7 Calcule i DN, i DP e v o para: v I = 0 V, 2,5 V e -2,5 V. Dados: -V tp = V tn = 1 V K n (W/L) = K p (W/L) =1 ma/v 2 Figure 4.25 Circuits for Example 4.7. 39

Exercício 4.16 Calcule i DN, i DP e v o para: v I = 0 V, 2,5 V e -2,5 V. Dados: -V tp = V tn = 1 V K n (W/L) = K p (W/L) =1 ma/v 2 Figure E4.16 40

Característica de Transferência i D VDD 1 = vds Reta de carga R R D D Figure 4.26 (a) Basic structure of the common-source amplifier. (b) Graphical construction to determine the transfer characteristic of the amplifier in (a). 41

Característica de Transferência A v dv dt o = Ganho do Amplificador v i = V IQ Figure 4.26 (Continued) (c) Transfer characteristic showing operation as an amplifier biased at point Q. 42

Figure 4.27 Two load lines and corresponding bias points. Bias point Q 1 does not leave sufficient room for positive signal swing at the drain (too close to V DD ). Bias point Q 2 is too close to the boundary of the triode region and might not allow for sufficient negative signal swing. 43

Figure 4.28 Example 4.8. 44

Figure 4.28 (Continued) 45

Polarização do MOSFET fixando a tensão V GS I D 1 = μnc 2 ox W L ( VGS Vt ) 2 V t, C ox, W e L variam de dispositivo para dispositivo da mesma família V t, e μ n variam com a temperatura. Figure 4.29 The use of fixed bias (constant V GS ) can result in a large variability in the value of I D. Devices 1 and 2 represent extremes among units of the same type. 46

Polarização com V G constante e resistor de fonte I D V = G V R S GS Figure 4.30 Biasing using a fixed voltage at the gate, V G, and a resistance in the source lead, R S : (a) basic arrangement; (b) reduced variability in I D ; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor C C1 ; (e) practical implementation using two supplies. 47

I D V = SS V R S GS 48

Projete o circuito para I D = 0,5 ma Dados: V DD = 15 V V t = 1 V K n (W/L) = 1 ma/v 2 Qual a variação de I D quando o MOSFET é trocado por outro com V t = 1,5 V? Figure 4.31 Circuit for Example 4.9. 49

Polarização com resistor de realimentação entre dreno e gate I D V = DD V R D GS Figure 4.32 Biasing the MOSFET using a large drain-to-gate feedback resistance, R G. 50

51 Figure 4.33 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I using a current mirror. R V V I GS DD REF + = SS V 2 2 2 2 1 ) ( ' t GS n D V V L W K I = 2 1 1 2 1 ) ( ' t GS n D V V L W K I = Polarização com fonte de corrente constante 1 2 2 ) / ( ) / ( L W L W I I REF D =

52 Figure 4.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier. 2 2 1 ) ( ' t GS n D V V L W K I = t GS D V V V gs GS GS v V v = 2 2 1 ) ( ' t gs GS n D V v V L W K i + = 2 2 2 1 2 1 gs n gs t GS n t GS n D v L W K v V V L W K V V L W K i ' ' ' ) ( ) ( + + = Análise C.C. Introduzindo agora o sinal: corrente c.c. de polarização: I D amplificação distorção

Condição de pequenos sinais: K ' n W L ( V V ) v >> GS t gs 1 2 K ' n W L v 2 gs v gs << 2 ( VGS Vt ) vgs << 2V OV Desprezando o termo de distorção: i I + i D D d ' W i d = Kn ( VGS Vt ) vgs = L g m v gs g m ' W ' W = Kn ( VGS Vt ) = Kn VOV ganho de transcondutância L L 53

Interpretação gráfica do ganho de transcondutância g m = i v d GS vgs = VGS Figure 4.35 Small-signal operation of the enhancement MOSFET amplifier. 54

v D = V DD R D i D v = V R + D DD D( ID id ) v d = R i D d = g m R D v gs A v v = v d gs = g m R D Figure 4.36 Total instantaneous voltages v GS and v D for the circuit in Fig. 4.34. 55

Modelo de pequenos sinais do MOSFET i = d g m v gs r o V = I A D g m = K ' n W L ( V GS V ) t 2I = D V V GS t Figure 4.37 Small-signal models for the MOSFET: (a) neglecting the dependence of i D on v DS in saturation (the channel-length modulation effect); and (b) including the effect of channel-length modulation, modeled by output resistance r o = V A /I D. 56

Analise o circuito e determine o ganho, resistência de entrada e máxima excursão do sinal de saída. Dados: V t = 1,5 V K n (W/L) = 0,25 ma/v 2 V A = 50V Figure 4.38 Example 4.10: (a) amplifier circuit; (b) equivalent-circuit model. 57

Modelo T Figure 4.39 Development of the T equivalent-circuit model for the MOSFET. For simplicity, r o has been omitted but can be added between D and S in the T model of (d). 58

Modelo T incluindo a resistência de saída Figure 4.40 (a) The T model of the MOSFET augmented with the drain-to-source resistance r o. (b) An alternative representation of the T model. 59

Modelamento do Efeito Corpo ( Body ) g mb i = v Transcondutância do corpo D v BS GS = const. vds = const. Figure 4.41 Small-signal equivalent-circuit model of a MOSFET in which the source is not connected to the body. 60

Modelos de Pequenos Sinais Table 4.2 61

Amplificadores com MOSFET de estágio único Polarização utilizada nos exemplos: Figure 4.42 Basic structure of the circuit used to realize single-stage discrete-circuit MOS amplifier configurations. 62

Determine V OV, V GS, V S, V D. Calcule g m e r o. Dados: V t = 1,5 V K n (W/L) = 1 ma/v 2 V A = 50V Figure E4.30 63

Table 4.3 64

Amplificador fonte comum Figure 4.43 (a) Common-source amplifier based on the circuit of Fig. 4.42. (b) Equivalent circuit of the amplifier for small-signal analysis. (c) Small-signal analysis performed directly on the amplifier circuit with the MOSFET model implicitly utilized. 65

Análise direta no circuito 66

Amplificador Fonte comum com resistor de fonte Figure 4.44 (a) Common-source amplifier with a resistance R S in the source lead. (b) Small-signal equivalent circuit with r o neglected. 67

Amplificador gate comum Figure 4.45 (a) A common-gate amplifier based on the circuit of Fig. 4.42. (b) A small-signal equivalent circuit of the amplifier in (a). (c) The common-gate amplifier fed with a current-signal input. 68

(c) The common-gate amplifier fed with a current-signal input. 69

Amplificador dreno comum Figure 4.46 (a) A common-drain or source-follower amplifier. (b) Small-signal equivalent-circuit model. 70

(c) Small-signal analysis performed directly on the circuit. (d) Circuit for determining the output resistance Rout of the source follower. 71

Amp. fonte comum Amp. fonte comum com resistor de fonte Table 4.4 72

Amp. gate comum Amp. dreno comum Table 4.4 (Continued) 73

Figure 4.47 (a) High-frequency equivalent circuit model for the MOSFET. (b) The equivalent circuit for the case in which the source is connected to the substrate (body). (c) The equivalent circuit model of (b) with C db neglected (to simplify analysis). 74

Figure 4.48 Determining the short-circuit current gain I o /I i. 75

Table 4.5 76

Figure 4.49 (a) Capacitively coupled common-source amplifier. (b) A sketch of the frequency response of the amplifier in (a) delineating the three frequency bands of interest. 77

Figure 4.50 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output; 78

Figure 4.50 (Continued) (c) the equivalent circuit with C gd replaced at the input side with the equivalent capacitance C eq ; (d) the frequency response plot, which is that of a low-pass single-time-constant circuit. 79

Figure 4.51 Analysis of the CS amplifier to determine its low-frequency transfer function. For simplicity, r o is neglected. 80

Figure 4.52 Sketch of the low-frequency magnitude response of a CS amplifier for which the three break frequencies are sufficiently separated for their effects to appear distinct. 81

Figure 4.53 The CMOS inverter. 82

Figure 4.54 Operation of the CMOS inverter when v I is high: (a) circuit with v I = V DD (logic-1 level, or V OH ); (b) graphical construction to determine the operating point; (c) equivalent circuit. 83

Figure 4.55 Operation of the CMOS inverter when v I is low: (a) circuit with v I = 0 V (logic-0 level, or V OL ); (b) graphical construction to determine the operating point; (c) equivalent circuit. 84

Figure 4.56 The voltage transfer characteristic of the CMOS inverter. 85

Figure 4.57 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and output waveforms; (c) trajectory of the operating point as the input goes high and C discharges through Q N ; (d) equivalent circuit during the capacitor discharge. 86

Figure 4.58 The current in the CMOS inverter versus the input voltage. 87

Figure 4.59 (a) Circuit symbol for the n-channel depletion-type MOSFET. (b) Simplified circuit symbol applicable for the case the substrate (B) is connected to the source (S). 88

Figure 4.60 The current-voltage characteristics of a depletion-type n-channel MOSFET for which V t = 4 V and k n (W/L) = 2 ma/v2 : (a) transistor with current and voltage polarities indicated; (b) the i D v DS characteristics; (c) the i D v GS characteristic in saturation. 89

Figure 4.61 The relative levels of terminal voltages of a depletion-type NMOS transistor for operation in the triode and the saturation regions. The case shown is for operation in the enhancement mode (v GS is positive). 90

Figure 4.62 Sketches of the i D v GS characteristics for MOSFETs of enhancement and depletion types, of both polarities (operating in saturation). Note that the characteristic curves intersect the v GS axis at V t. Also note that for generality somewhat different values of V t are shown for n-channel and p-channel devices. 91

Figure E4.51 92

Figure E4.52 93

Figure 4.63 Capture schematic of the CS amplifier in Example 4.14. 94

Figure 4.64 Frequency response of the CS amplifier in Example 4.14 with C S = 10 mf and C S = 0 (i.e., C S removed). 95

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