The MC013B dual ype D flip flop is consruced wih MOS P channel and N channel enhancemen mode devices in a single monolihic srucure. Each flip flop has independen Daa, (D), Direc Se, (S), Direc Rese, (R), and Clock (C) inpus and complemenary oupus (Q and Q). These devices may be used as shif regiser elemens or as ype T flip flops for couner and oggle applicaions. Saic Operaion Diode Proecion on All Inpus Supply Volage Range = 3.0 Vdc o 18 Vdc Logic Edge Clocked Flip Flop Design Logic sae is reained indefiniely wih clock level eiher high or low; informaion is ransferred o he oupu only on he posiive going edge of he clock pulse Capable of Driving Two Low power TTL Loads or One Low power Schoky TTL Load Over he Raed Temperaure Range Pin for Pin Replacemen for CD4013B PDIP P SUFFIX CASE 646 SOIC D SUFFIX CASE 751A MARKING DIAGRAMS 1 1 MC013BCP AWLYYWW 013B AWLYWW MAXIMUM RATINGS (Volages Referenced o V SS ) (Noe 2.) Symbol Parameer Value Uni V DD DC Supply Volage Range 0.5 o +18.0 V V in, V ou Inpu or Oupu Volage Range (DC or Transien) 0.5 o V DD + 0.5 V I in, I ou P D Inpu or Oupu Curren (DC or Transien) per Pin Power Dissipaion, per Package (Noe 3.) ±10 ma 500 mw T A Ambien Temperaure Range 55 o +125 C T sg Sorage Temperaure Range 65 o +150 C T L Lead Temperaure (8 Second Soldering) 260 C 2. Maximum Raings are hose values beyond which damage o he device may occur. 3. Temperaure Deraing: Plasic P and D/DW Packages: 7.0 mw/c From 65C To 125C This device conains proecion circuiry o guard agains damage due o high saic volages or elecric fields. However, precauions mus be aken o avoid applicaions of any volage higher han maximum raed volages o his high impedance circui. For proper operaion, V in and V ou should be consrained o he range V SS (V in or V ou ) V DD. Unused inpus mus always be ied o an appropriae logic volage level (e.g., eiher V SS or V DD ). Unused oupus mus be lef open. A WL, L YY, Y WW, W = Assembly Locaion = Wafer Lo = Year = Work Week ORDERING INFORMATION Device Package Shipping MC013BCP PDIP 2000/Box MC013BD SOIC 55/Rail MC013BDR2 SOIC 2500/Tape & Reel MC013BDT MC013BF TSSOP DT SUFFIX CASE 948G SOEIAJ F SUFFIX CASE 965 TSSOP SOEIAJ 1 1 013B ALYW MC013B ALYW 96/Rail MC013BDTR2 TSSOP 2500/Tape & Reel See Noe 1. MC013BFEL SOEIAJ See Noe 1. 1. For ordering informaion on he EIAJ version of he SOIC packages, please conac your local ON Semiconducor represenaive. Semiconducor Componens Indusries, LLC, 2000 Augus, 2000 Rev. 4 1 Publicaion Order Number: MC013B/D
TRUTH TABLE Inpus Oupus Clock Daa Rese Se Q Q 0 0 0 0 1 1 0 0 1 0 X 0 0 Q Q X X 1 0 0 1 X X 0 1 1 0 X X 1 1 1 1 X = Don Care = Level Change No Change PIN ASSIGNMENT BLOCK DIAGRAM 2
ELECTRICAL CHARACTERISTICS (Volages Referenced o V SS ) ÎÎ 55C 25C ÎÎ 125C V DD Characerisic Î Symbol Vdc Min MaxÎ Min Typ (4.) Î Max Min Max Uni Oupu Volage 0 Level Î V OL 5.0 0.05Î 0 Î 0.05 0.05 Vdc V in = V DD or 0 10 0.05 0 0.05 0.05 15 0.05 0 0.05 0.05 V in = 0 or V DD 1 LevelÎ V OH ÎÎ 5.0 4.95 10 9.95 4.95 Î 9.95 5.0 4.95 10 Î 9.95 Vdc 15.95.95 15.95 Inpu Volage 0 Level V (V O = 4.5 or 0.5 Vdc) Î IL Vdc 5.0 (V O = 9.0 or 1.0 Vdc) 10 1.5 2.25Î 1.5 3.0Î 4.50Î 3.0 1.5 3.0 (V O = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0 (V O = 0.5 or 4.5 Vdc) 1 Level V (V O = 1.0 or 9.0 Vdc) Î IH 5.0 3.5 3.5 2.75 3.5 Vdc 10 7.0 Î 7.0 5.50Î 7.0 (V O = 1.5 or 13.5 Vdc) 15 11 Î 11 8.25Î 11 Oupu Drive Curren Î I OH ÎÎ madc (V OH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7 (V OH = 4.6 Vdc) 5.0 0.64 Î 0.51 0.88Î 0.36 (V OH = 9.5 Vdc) 10 1.6 Î 1.3 2.25Î 0.9 (V OH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4 (V OL = 0.4 Vdc) Sink I (V OL = 0.5 Vdc) Î OL 5.0 0.64 0.51 0.88 0.36 madc 10 1.6 Î 1.3 2.25Î 0.9 (V OL = 1.5 Vdc) 15 4.2 Î 3.4 8.8 Î 2.4 Inpu Curren Î I in 15 ± 0.1 Î ±0.00001 Î ± 0.1 ± 1.0 µadc Inpu Capaciance Î C in (V in = 0) Î 5.0 Î 7.5 pf Quiescen Curren I (Per Package) Î DD 5.0 1.0 0.002 1.0 30 µadc 10 2.0Î 0.004Î 2.0 60 15 4.0Î 0.006Î 4.0 120 Toal Supply Curren (5.) (6.) Î I T 5.0 ÎÎ I T = (0.75 µa/khz) f + I DD µadc (Dynamic plus Quiescen, 10 I Per Package) 15 ÎÎ T = (1.5 µa/khz) f + I DD I T = (2.3 µa/khz) f + I DD (C L = 50 pf on all oupus, all buffers swiching) 4. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance. 5. The formulas given are for he ypical characerisics only a 25C. 6. To calculae oal supply curren a loads oher han 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in µa (per package), C L in pf, V = (V DD V SS ) in vols, f in khz is inpu frequency, and k = 0.002. 3
SWITCHING CHARACTERISTICS (7.) (C L = 50 pf, T A = 25C) Characerisic ÎÎ Symbol Î V DD Î Min Î Typ (8.) Î Max Uni Oupu Rise and Fall Time ÎÎ TLH, ns Î Î Î TLH, THL = (1.5 ns/pf) C L + 25 ns TLH, THL = (0.75 ns/pf) C L + 12.5 ns ÎÎ THL 5.0 100 200 Î 10 Î Î 50 Î 100 TLH, THL = (0.55 ns/pf) C L + 9.5 ns ÎÎ 15 Î Î 40 Î 80 Propagaion Delay Time ÎÎ PLH ns Î Î Î Clock o Q, Q PLH, PHL = (1.7 ns/pf) C L + 90 ns ÎÎ PHL Î 5.0 Î Î 175 Î 350 PLH, PHL = (0.66 ns/pf) C L + 42 ns 10 75 150 Î PLH, PHL = (0.5 ns/pf) C L + 25 ns 15 50 100 Se o Q, Q PLH, PHL = (1.7 ns/pf) C L + 90 ns ÎÎ 5.0 Î Î 175 Î 350 PLH, PHL = (0.66 ns/pf) C L + 42 ns ÎÎ 10 Î Î 75 Î 150 PLH, PHL = (0.5 ns/pf) C L + 25 ns 15 50 100 Rese o Q, Q PLH, PHL = (1.7 ns/pf) C L + 265 ns ÎÎ 5.0 Î Î 225 Î 450 PLH, PHL = (0.66 ns/pf) C L + 67 ns ÎÎ 10 Î Î 100 Î 200 PLH, PHL = (0.5 ns/pf) C L + 50 ns 15 75 150 Seup Times (9.) ÎÎ su 5.0 40 20 ns Î 10 Î 20 Î 10 Î Î 15 Î 15 Î 7.5 Î Hold Times (9.) ÎÎ h 5.0 40 20 ns Î Î Î 10 20 10 Î 15 Î 15 Î 7.5 Î Clock Pulse Widh ÎÎ WL, WH Î 5.0 Î 250 Î 125 Î ns 10 100 50 15 70 35 Clock Pulse Frequency ÎÎ f cl Î 5.0 Î Î 4.0 Î 2.0 Î 10 Î Î 10 Î 5.0 MHz 15 7.0 Clock Pulse Rise and Fall Time Î TLH 5.0 15 µs THL Î 10 Î Î Î 5.0 Î 15 Î Î Î 4.0 Se and Rese Pulse Widh Î WL, WH Î 5.0 Î 250 Î 125 ns 10 100 50 Î 15 Î 70 Î 35 Î Removal Times ÎÎ rem Î Î Î ns Se 5 80 0 10 45 5 Î 15 Î 35 Î 5 Î Rese ÎÎ Î Î 5 Î 50 Î 35 Î 10 30 10 Î Î Î 7. The formulas given are for he ypical characerisics only a 25C. 8. Daa labelled Typ is no o be used for design purposes bu is inended as an indicaion of he IC s poenial performance. 9. Daa mus be valid for 250 ns wih a 5 V supply, 100 ns wih 10 V, and 70 ns wih 15 V. 15 25 5 LOGIC DIAGRAM (1/2 of Device Shown) 4
Inpus R and S low. Figure 1. Dynamic Signal Waveforms (Daa, Clock, and Oupu) Figure 2. Dynamic Signal Waveforms (Se, Rese, Clock, and Oupu) TYPICAL APPLICATIONS n STAGE SHIFT REGISTER BINARY RIPPLE UP COUNTER (Divide by 2 n ) MODIFIED RING COUNTER (Divide by (n+1)) 5
PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646 06 ISSUE M B T N A F L C K J H G D PL M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A 03 ISSUE F A B P 7 PL T G D PL K C R X 45 F M J 6
PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G 01 ISSUE O L T 2X L/2 PIN 1 IDENT. D C X K REF N M B U A V G H N J J1 F DETAIL E K K1 ÇÇÇ ÉÉ SECTION N N DETAIL E W Z D e b E A H E A 1 VIEW P F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965 01 ISSUE O M L E Q 1 L DETAIL P c 7
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