MC100LVEP V / 3.3V ECL 2, 4, 8 Clock Generation Chip

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1 2.5V / 3.3V ECL 2, 4, 8 Clock Generation Chip The MC00LVEP34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The V BB pin, an internally generated voltage supply, is available to this device only. For single ended input conditions, the unused differential input is connected to V BB as a switching reference voltage. V BB may also rebias AC coupled inputs. When used, decouple V BB and V CC via a 0.0 F capacitor and limit current sourcing or sinking to ma. When not used, V BB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start up, the internal flip flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple LVEP34s in a system. Single ended CLK input operation is limited to a V CC 3.0 V in PECL mode, or V EE 3.0 V in NECL mode. Features 35 ps Output to Output Skew Synchronous Enable/isable Master Reset for Synchronization The 00 Series Contains Temperature Compensation. PECL Mode Operating Range: V CC = V to 3.8 V with V EE = 0 V NECL Mode Operating Range: V CC = 0 V with V EE = V to 3.8 V Open Input efault State LVS Input Compatible These are Pb Free evices 6 6 SO 6 SUFFIX CASE 75B TSSOP 6 T SUFFIX CASE 948F 6 MARKING IAGRAMS* A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or = Pb Free Package 00LVEP34G AWLYWW 6 00 VP34 ALYW (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN8002/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 204 April, 204 Rev. Publication Order Number: MC00LVEP34/

2 0 6 V CC 0 2 R 2 5 EN V CC 3 R 4 NC 4 3 CLK 5 R 4 2 CLK V CC 6 V BB MR 2 8 R 8 9 V EE Warning: All V CC and V EE pins must be externally connected to Power Supply to guarantee proper operation. Figure. 6 Lead Pinout (Top View) and Logic iagram Table. PIN ESCRIPTION Pin CLK*, CLK** EN* MR* ECL iff Clock Inputs ECL Sync Enable ECL Master Reset 0, 0 ECL iff 2 Outputs, ECL iff 4 Outputs 2, 2 ECL iff 8 Outputs V BB V CC V EE NC Function Reference Voltage Output Positive Supply Negative Supply No Connect * Pins will default LOW when left open. **Pins will default to V CC /2 when left open. Table 2. FUNCTION TABLE CLK EN MR FUNCTION Z ZZ X L H X L L H Z = Low to High Transition ZZ = High to Low Transition ivide Hold 0 3 Reset 0 3 2

3 Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ES Protection Characteristics Human Body Model Machine Model Charged evice Model Value 75 k 37.5 k > 2 kv > 200 V > 2 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note ) Level Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0.25 in Transistor Count Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test 20 evices. For additional Moisture Sensitivity information, refer to Application Note AN8003/. Table 4. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Unit V CC PECL Mode Power Supply V EE = 0 V 6 V V EE NECL Mode Power Supply V CC = 0 V 6 V V I PECL Mode Input Voltage NECL Mode Input Voltage V EE = 0 V V CC = 0 V V I V CC 6 V I V EE 6 V V I out Output Current Continuous Surge ma ma I BB V BB Sink/Source ± ma T A Operating Temperature Range 40 to +85 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm SOIC 6 SOIC 6 JC Thermal Resistance (Junction to Case) Standard Board SOIC 6 33 to 36 C/W JA Thermal Resistance (Junction to Ambient) 0 lfpm 500 lfpm TSSOP 6 TSSOP 6 JC Thermal Resistance (Junction to Case) Standard Board TSSOP 6 33 to 36 C/W T sol Wave Solder <2 to C 265 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected C/W C/W C/W C/W 3

4 Table 5. 00EP C CHARACTERISTICS, PECL V CC = 2.5 V, V EE = 0 V (Note 2) Symbol Characteristic 40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 3) mv V OL Output LOW Voltage (Note 3) mv V IH Input HIGH Voltage (Single Ended) (Note 4) mv Unit V IL V IHCMR Input LOW Voltage (Single Ended) (Note 4) Input HIGH Voltage Common Mode Range (ifferential) (Note 4, Note 5) mv V I IH Input HIGH Current A I IL Input LOW Current NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary : with V CC. 3. All loading with 50 to V CC 2.0 V. 4. o not use V BB at V CC < 3.0 V. Single Ended input CLK pin operation is limited to V CC 3.0 V in PECL mode. 5. V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. A 4

5 Table 6. 00EP C CHARACTERISTICS, PECL V CC = 3.3 V, V EE = 0 V (Note 6) Symbol Characteristic 40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 7) mv V OL Output LOW Voltage (Note 7) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv V BB Output Voltage Reference (Note 8) mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential) (Note 9) V I IH Input HIGH Current A I IL Input LOW Current NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. Input and output parameters vary : with V CC. V EE can vary V to V. 7. All loading with 50 to V CC 2.0 V. 8. Single Ended input CLK pin operation is limited to V CC 3.0 V in PECL mode. 9. V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit A Table 7. 00EP C CHARACTERISTICS, NECL V CC = 0 V, V EE = 3.8 V to V (Note 0) Symbol Characteristic 40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note ) mv V OL Output LOW Voltage (Note ) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv V BB Output Voltage Reference (Note 2) mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential) (Note 3) V EE V EE V EE V I IH Input HIGH Current A I IL Input LOW Current NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 0.Input and output parameters vary : with V CC.. All loading with 50 to V CC 2.0 V. 2.Single Ended input CLK pin operation is limited to V EE 3.0 V in NECL mode. 3.V IHCMR min varies : with V EE, V IHCMR max varies : with V CC. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit A 5

6 Table 8. AC CHARACTERISTICS V CC = 0 V; V EE = 3.8 V to V or V CC = V to 3.8 V; V EE = 0 V (Note 4) 40 C 25 C 85 C Symbol f max Characteristic Maximum Toggle Frequency (See Figure 4. F max ) Min Typ Max Min Typ Max Min Typ Max Unit GHz t PLH Propagation CLK to 0,, 2 t PHL elay to Output MR to ps t JITTER RMS Clock Jitter IV2 2.5 GHz (See Figure 4. F max /JITTER) IV2 3.0 GHz IV4 2.5 GHz IV4 3.0 GHz IV8 2.5 GHz IV8 3.0 GHz ps t S Setup Time EN ps t H Hold Time EN ps t RR Set/Reset Recovery ps V PP Input Swing (Note 5) mv t r t f Output Rise/Fall Times (20% 80%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4.Measured using a 750 mv source, 50% duty cycle clock source. All loading with 50 to V CC 2.0 V. 5.V PP( min) is minimum input swing for which AC parameters guaranteed. The device has a C gain of 40. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6

7 There are two distinct functional relationships between the Master Reset and Clock: MR Internal Clock isabled Internal Clock Enabled CLK 0 2 EN CASE : If the MR is de asserted (H L), while the Clock is still high, the outputs will follow the second ensuing clock rising edge. MR Internal Clock isabled Internal Clock Enabled CLK 0 2 EN CASE 2: If the MR is de asserted (H L), after the Clock has transitioned low, the outputs will follow the third ensuing clock rising edge. Figure 2. Timing iagrams The EN signal will freeze the internal divider flip flops on the first falling edge of CLK after its assertion. The internal divider flip flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip flops will unfreeze and continue to their next state count with proper phase relationships. T RR T RR CLOCK CLOCK MR MR OUTPUT OUTPUT CASE CASE 2 Figure 3. Reset Recovery Time 7

8 900 9 V OUTpp (mv) / FREUENCY (MHz) Figure 4. F max river evice Z o = 50 Z o = 50 Receiver evice V TT V TT = V CC 2.0 V Figure 5. Typical Termination for Output river and evice Evaluation (See Application Note AN8020/ Termination of ECL Logic evices.) ORERING INFORMATION MC00LVEP34G evice Package Shipping SOIC 6 (Pb Free) 48 Units / Rail MC00LVEP34R2G SOIC 6 (Pb Free) 2500 / Tape & Reel MC00LVEP34TG TSSOP 6* 96 Units / Rail MC00LVEP34TR2G TSSOP 6* 2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR80/. *This package is inherently Pb Free. 8

9 Resource Reference of Application Notes AN405/ ECL Clock istribution Techniques AN406/ esigning with PECL (ECL at +5.0 V) AN503/ ECLinPS I/O SPiCE Modeling Kit AN504/ Metastability and the ECLinPS Family AN568/ Interfacing Between LVS and ECL AN672/ The ECL Translator Guide AN800/ Odd Number Counters esign AN8002/ Marking and ate Codes AN8020/ Termination of ECL Logic evices AN8066/ Interfacing with ECLinPS AN8090/ AC Characteristics of ECL evices 9

10 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PLANE L U PIN IENT. U S S 2X L/2 C 6X K REF A V G PACKAGE IMENSIONS 0.0 (0.004) M T U S V S B U TSSOP 6 CASE 948F 0 ISSUE B H J N N J F ETAIL E ETAIL E K K ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ SECTION N N 0.25 (0.00) M W NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INCLUE MOL FLASH. PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. IMENSION B OES NOT INCLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXCEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K IMENSION AT MAXIMUM MATERIAL CONITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLERING FOOTPRINT* PITCH 6X X.26 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. 0

11 PACKAGE IMENSIONS A B SOIC 6 CASE 75B 05 ISSUE K P 8 PL 0.25 (0.00) M B S NOTES:. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS A AN B O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G.27 BSC BSC J K M P R T SEATING PLANE G 6 PL 0.25 (0.00) M T B S A S K C M R X 45 J F SOLERING FOOTPRINT* 8X X.2 6 6X 8.27 PITCH 8 9 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC00LVEP34/