HDI-Baugruppen der Zukunft - Applikationen, Entwurf, Technologien

HDI-Baugruppen der Zukunft - Applikationen, Entwurf, Technologien 2,5D SiP Vertikale Integration heterogener Mikroschaltungen Stephan Guttowski 2), David Polityko 1), Herbert Reichl 1) 1) Technical University Berlin, FSP Mikroperipherik (TUB-MP) 2) Fraunhofer Institute for Reliability and Microintegration (Fraunhofer IZM Berlin) Stephan.Guttowski@izm.fraunhofer.de

Contents Introduction HDI and vertical SiP integration Physical design for 2D HDI Vertical SiP integration Manual Design approach and parameters Multicriteria design approach - automation of placement and technology selection for 2,5D SiP 1/ 31

Introduction HDI boards today HDI boards tomorrow [Amkor] [Messring] Hihgly integrated 2D PCB s and semi vertical boards with lower integration density [Amkor] 2,5D System-in-Package multiple vertically integrated HDI Boards increasing integration density 2/ 31

Introduction HDI boards today Solder Mask Cu Top l w l s S d 5 c 4 c 3 d 3 c 2 d 1 d 4 c 1 d 2 Core d i Via Land Via TH Substrate Parameter HDI MCM-L PCB common MCM-C Ceramik MCM-D Thinfilm Line width [µm] (45) 50 75 125 75..100 10 Line space [µm] (45) 50 75 125 250 10 Via Land ø [µm] (<)100 225 650 200 30 No. Layer 8 10 + 8...30 15..30 2..5 Diel. Const. 2,3 4.7 4,7 6...10 2,7...3,5 Material FR4 FR4 Keramik Si, Metall Price (approx) medium low cents/cm 2 medium high $/cm 2 3/ 31

HDI and 2,5D SiP Laminated HDI boards vs. thin film Wiring density - HDI line width line space ratio is scaled down to 50µm Very flexible via constructions (blind, buried, plugged ) Flexible substrate layers construction (prepreg-core combinations) Double sided metallisation and assembly possible Laminated substrates are well suited for application within the advance integration approaches and especially for 2,5D SiP Integration 4/ 31

HDI and 2,5D SiP Today's SiP applications a) [Intel] Intel Prozessor PXA27x as Fold-Stack-SiP in Motorola s E680 Tri-Band Mobile Phone [Motorola] PSvfBGA, [Amkor], Memories and µc µz MCP Folded-Die and Ball-Stack, [Tessera] 5/ 31

HDI and 2,5D SiP SiP Market Facts Mio. pieces 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 Automotive Consumer Wireless Others (Med.,Comp., Aero) 2004 2005 2006 2007 2008 2009 6/ 31

HDI and 2,5D SiP Future Vision Pervasive Computing Ambient Intelligence egrain Sensor Networks - heterogeneous Systems in their Nature - Extreme Miniaturization Requirements -... Fraunhofer IZM egrain Roadmap - Choosing an optimal Integration Technology for the next Miniaturization Step Sensors and Actuators Antenna / Communication µcontroller, Memory Power Supply / Generation 7/ 31

Physical Design What is System-In-Package? - any combination of semiconductors, passives, and interconnects integrated into a single package [ITRS] -no limitation to any technology or integration approach What is 2,5D SiP Integration? - Vertically Stacked Layer - Heterogeneous Components - Challenging for On-Chip Integration - Size/Weight/Integr. Density Advantages compared to On-Board Integration SiP Challenges -No Standardisation in Technology -Design Analytic - Beginning - No clear defined Parameters for Optimal Technology Selection 100 [%] 90 80 70 60 50 40 30 20 10 Bare Die (COB) Trough Hole (TO,Dip) Surface Mount (SO,QFP ) Array (FlipChip,BGA,CSP) [Smith&Tessier / Amkor] 2,5D 1980 1985 1990 1995 2000 2005 2010 2015 2020 8/ 31

Physical Design What is Physical Design? System Design: Functional & Structural Analysis Reset SW Idle S µp RF RX TX Components, Net Lists E System behaviour, Schematic definition, Components selection Verification Technol. Parameter Equipment-, Process-, Material Data Layout, Gerber Manufacturing Data, Gerber Physical Design Technology Selection Geometrical Layout Technological Realisation Prototyping 9/ 31

Planar Integration Physical Design for 2D HDI based MCM Schematic-> Net lists, Components incl. Dice-> Geometries Partitioning Layout Physical Design 2D System Complexity Placement Global Routing System Design oriented Technology Parameter Interconnect FC-WireBond Substrate MCM-L,C,D Technology Selection Thermal Simulation Technology Design Rules Detailed Routing Validation -Extraction -Parasitics Electrical Simulation 10 / 31

Planar Integration Design Main Stream: Partitioning, Placement, Routing Partitioning -Heuristic - Kerninghan&Lin -... Routing -Rents Rule - SLICE Routing -... Placement - Rubber Band -MinCut -... Mathematical Problem with different Boundary Conditions: - Wirelenth optimisation - Floor plan/area Optimisation - Analog/Dig. Separation, EMC - Thermal Aspects -... 11 / 31

Planar Integration Physical Design for 2D MCM II Schematic-> Net lists, Components incl. Dice-> Geometries Partitioning Layout Physical Design 2D System Complexity Placement Global Routing System Design oriented Technology Parameter Interconnect FC-WireBond Substrate MCM-L,C,D Technology Selection Thermal Simulation Technology Design Rules Detailed Routing Validation -Extraction -Parasitics Electrical Simulation 12 / 31

Planar Integration Technology Parameter 2D Substrate Interconnects MCM-L MCM-C MCM-D HDI Standard PCB Ceramics Thinfilm Line width [µm] 75 125 125 10 Line space [µm] 75 125 250 10 Via land ø [µm] 100 650 200 30 no. layers 8 10 8...30 15..30 2..5 Dielectrics Epoxy Current Status Epoxy 2DAlumina BCB/PBO Diel.const. 2,3 4,7 4,7 6...10 Design algorithms und numerous tools 2,7...3,5 Base material (Autoplacer, FR4 Autorouter) FR4(Mentor, Alumina Cadence...) silicon, metal Price (4 layers) medium Low (cents/cm²) medium High ($/cm²) Technology standardisation, parametrical interface to design Wire Bond Flip Chip TAB Min pad Die 50 120 60 pitch [µm] Substr. 120 120 200 Mounting serial (2-10 bonds/sec) parallel serial/parallel Electr. Performance L [nh] 1-5 0,06-0,2 1-3 C [pf] 0,2-0,6 0,02-0,03 0,2-0,6 Mechanical Protection glob top underfill none 13 / 31

Vertical Integration Physical Design for 2,5D, Manual Approach Schematic->Net lists, Components incl. Dice->Geometries System Complexity Global Partition. Global Placement Global Routing Global 2,5D Layout Technology free Physical Design 2,5D Technology Parameter Stacking Techn. Substrate, VIC Technology Selection Technology Design Rules Detailed Partitioning Detailed Placement Detailed Routing Detailed Layout 2D Layer Technology based Validation -Extraction -Parasitics Thermal Simulation Electrical Simulation 14 / 31

Vertical Integration Global Partitioning, Placement, Routing L2 Mathematical problem with a number of boundary conditions / objectives : - floor plan and volume minimization - power/ground decoupling - minim. vertical Interconnects - testability -... Routing: optimization of nets between layers L1 L1 L0 L0 Partitioning: grouping/allocation of components on certain layer L2 Placement: arrangement of layers in stack 15 / 31

Vertical Integration??? Not Uniform Nomenclature 3(2,5)D Vertical SiP, Stacked CSP, Three Dimensional Multichip Integration, Chip Stack... No Standards accepted across the Industry Classification in Literature/Papers by Integration Level (Wafer-, Chip-, Pack./Modul-Stack) [Reichl/ZM, Kada/Sharp] by Interconnects Technology (Area, Periphery) [Al-Sarawi/Adelaid Univ.] Technology oriented, further interpretation possible 16 / 31

Vertical Integration Technology Parameter 2,5D Signal Redistribution Capability Stacked Stacked Flex Molded Dice Modules Folded Devices Vertical Wiring - - high medium Lateral Wiring low high high medium Passives Discrete low high high high Integration Capability embedded low high medium medium Wire Length WL high medium high high No Funct. Layer L Up to 5 7 10 32 Layer Thickness L=G+C Layer Gap G[µm] negligible 100 1200 200 1200 50 600 Carrier C[µm] 200 600µ 50 1200 20 100 50 200 VIC Density [1/(mm 2 mm)] 0,5; ~f(g) 0,5 3;~f(G) 5 30 10 50???? 17 / 31

Vertical Integration Parameters Placement automation 18 / 31

Vertical Integration Parameters Placement automation 19 / 31

Vertical Integration Parameters Placement automation 20 / 31

Vertical Integration Parameters Placement automation 21 / 31

Vertical Integration Parameters Placement automation 0,8b b b 2 G C 200 N N=194 p s 175 150 125 100 75 50 0100 5 Thinned Dice Thin Bumps N=86 0201 SMD Thickness Area Typical Die Thickness Area N=31 0603 N= Avic 9G² 25 0402 N=12 N=8 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 G[mm] 22 / 31

Technology Constrained 2.5D Component Placement 2.5D Placement Automation: Tool for constrained component placement and technology selection based on the mathematical methods (combinatorial Optimisation) targeting multicriterial 2.5D SiP Design (Volume & Wiring Minimisation etc.) 200 175 150 125 100 75 50 25 0 N 01005 N=194 Soldered Modules N=86 0201 Stacked Dice Stacked Modules Flex Folded Molded Devices Redistribution Vertical - - high medium Capability Lateral low high high medium Passives Discrete low high high high Integration Capability embedded low high medium medium N=133 Wire Length const. Folded WL Flex high medium high high No Funct. Layer L Up to 5 7 10 32 Layer Thickness Layer Gap G[µm] negligible 100 1200 200 1200 50 600 L=G+C Carrier C[µm] 200 600µ?50 1200 20 100 50 200 VIC Density [1/(mm 2 mm)]?0,5; ~f(g) 0,5 3;~f(G) 5 30 10 50???? N=49 0402 N=31 Systemintegration Parameter 0603 N=12 N=8 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 G[mm] Fraunhofer IZM Volume Pack and sorting algorithmic.......... folded Stacked Wire lenth Fraunhofer ITWM 3D SiP Expert Autoplacer and technology selection tool 23 / 31

Vertical Integration Physical Design for 2,5D manual Approach Schematic->Net lists, Components incl. Dice->Geometries System Complexity Global Partition. Global Placement Global Routing Global 2,5D Layout Technology free ENB Physical Design 2,5D Technology Parameter Stacking Techn. Substrate, VIC Technology Selection Technology Design Rules Detailed Partitioning Detailed Placement Detailed Routing Detailed Layout 2D Layer Technology based Validation -Extraction -Parasitics Thermal Simulation Electrical Simulation 24 / 31

Vertical Integration Physical Design for 2,5D Schematic->Net lists, Components incl. Dice->Geometries System Complexity Global Partition. Global Placement Global Routing Global 2,5D Layout Technology free Physical Design 2,5D Technology Parameter Stacking Techn. Substrate, VIC Technology Selection Technology Design Rules Detailed Partitioning Detailed Placement Detailed Routing Detailed Layout 2D Layer Technology based Validation -Extraction -Parasitics Thermal Simulation Electrical Simulation 25 / 31

Multicriterial Approach for Automation of Global Design for 2,5D Schematic->Net lists, Components & Geometries Technology Modelling Constraints Parameter Technology 1 Global Part. Placement Rout. Technology 2 Global Part. Placement Rout.... Technology N Global Part. Placement Rout. Design 1...n Design 1...n Design 1...n Design/Technology-Selection Multicriterial Design Rules Detailed Partition. Detailed Placem. Detail Routing Detailed Design 2D Validation -Extraction -Parasitics Thermal Simulation Electrical simulation 26 / 31

Multicriterial Approach for Automation of Global Design for 2,5D Schematic->Net lists, Components & Geometries Technology ENB Modelling Constraints Parameter Technology 1 Global Part. Placement Rout. Technology 2 Global Part. Placement Rout.... Technology N Global Part. Placement Rout. Design 1...n Design 1...n Design 1...n Design/Technology-Selection Multicriterial Design Rules Detailed Partition. Detailed Placem. Detail Routing Detailentwurf 2D Ebenen Validation -Extraction -Parasitics Thermal Simulation Electical simulation 27 / 31

Multicriterial Optimization for 2.5D SiP Folded Stacked 3D SiP Expert - Multicriterial Layout Options and Technology Selection Stack vs. Folded Flex, constrained by technological geometry models Layer Number {2 4} Layer Size / Perimeter Volume Wire Length ViC Number -. Perspective: electromagnetic & thermal constraints NP-Hard combinatorial optimization problem Approximated Pareto frontier Patent pending 28 / 31

Multicriterial Optimization for 2.5D SiP, Stacked vs. Folded Stacked + shorter wirelength number of vertical interconnects - Bigger XY dimensions Folded Stacked Folded + smaller XY dimensions number of vertical interconnects - High Z dimension Patent pending 29 / 31

Summary HDI technology is similar important for packaging purposes as thin film or ceramics Wide usage of HDI laminated boards for vertical Integration Call for tools - new design methods are required Further researches in the area of advanced SiP are on going at Fraunhofer IZM 30 / 31

Contract Designs and Simulation for Advanced Boards 31 / 31

System Design & Integration @ IZM 32 / 31

Stephan.Guttowski@izm.fraunhofer.de 33 / 31