HIGH SPEED PARALLEL COUNTER BASED ON STATE LOOK AHEAD LOGIC Mandadi.krishnaveni 1 B.Kedarnath 2 Sk.saidulu 3 1 M.Tech (VLSI), Deportment of ECE, Gurunanak Institute of Technology 1 2 Professor and HOD of ECE, Gurunanak Institute of Technology 2 3 Assistant professor, Deportment of ECE, Gurunanak Institute of Technology 3 Mail:krishnaveni.mandadi@gmail.com 1 hodece.gnit@gniindia.com 2 sk.saidulu@gmail.com 3 Abstract High speed parallel counter is designing to get high operating frequency and to reduce the power consumption, and it can be achieved through a novel pipeline portioning technology(a counting path and state look ahead logic with CDMFF). Using only three simple repeated CMOS-logic module types: an initial module generates anticipated counting states for higher significant bit modules through the state lookahead path, simple conditional data mapping flip-flops with only 14 transistor count, and 2-bit counters. The state look-ahead path prepares the counting path s next counter state prior to the clock edge such that the clock edge triggers all modules simultaneously, thus concurrently updating the count state with a uniform delay at all counting path modules/stages with respect to the clock edge. Keywords: Architecture design, high-performance counter design, parallel counter design, DSCH, Microwind. I. INTRODUCTION Counters are used in circuit operations such as controllers, processors, mobile phone applications, programmable frequency dividers, shifters, code generators, memory select management, and various arithmetic operations. Counter architecture design methodologies explore tradeoffs between operating frequency, power consumption, area requirements, and target application specialization. Early design methodologies improved counter operating frequency by partitioning large counters into multiple smaller counting modules, such that modules of higher significance (containing higher significant bits) were enabled when all bits in all modules of lower significance (containing lower significant bits) saturate. Initializations and propagation delays such as register load time, AND logic chain decoding, and the half incrementer component delays in half adders dictated operating frequency which leads to occurring of delays, more power consumption, so to overcome the drawbacks in existing system I am proposing one parallel counter based on a counting path and state look ahead logic, this phenomena is known as novel pipeline partitioning methodology. The state look ahead logic avoids the use of an overhead delay detector circuit, in this design conditional data mapping flip flops are used simply known as CDMFF from this architecture design we can achieve low power consumption and high performance(the number of transistors are reduced in CDMFF comparing with simple D flip flop), and 2-bit counters. The objective of this project is to improve the counter operating frequency by eliminating the carry chain delay and reduce the power consumption, occupied area by reducing the no of transistor count and AND gate fan-in and fan-out irrespective of the existing systems. II. CONDITIONAL DATA MAPPING FLIP FLOP Flip-Flops are the fundamental building blocks for all sequential circuits, the basic function of flip flop is storing information. Flip- flops have their content change only either at the rising or falling edge of the enable signal. But, after the rising or falling edge of the enable signal, the flip-flop s content remains constant even if the input changes. In a conventional D Flip Flop shown in Figure 1, the clock signal always flows into the D flip-flop irrespective of whether the input changes or not. Part of the clock energy is consumed by the internal clock buffer to control the transmission gates unnecessarily. Hence, if the input of the flip-flop is identical to its output, the switching of the clock can be suppressed to conserve power. Fig1: conditional data mapping flip flop circuit Huge amount of the on-chip power is consumed by the clock drivers. It is desirable to have less clocked load in the system. For example, CCFF and CDFF used 14 transistor and 15 clocked transistors respectively. In contrast, conditional data mapping flip-flop (CDMFF) used only seven clocked transistors, resulting in about 50% reduction in the number of clocked transistors,
hence CDMFF used less port than CCFF and CDFF. (Note that CDFF used double edge triggered. For simplicity purposes, we did not include the power savings by double edge triggering on the clock distribution network.) This shows the effectiveness of reducing clocked transistor numbers to achieve low power. Since CDMFF outperforms CCFF and CDFF in view of power consumption.ccff and CDFF are not further more discussed architecture is only about CDMFF. However, there is redundant clocking capacitance in CDMFF. When data remains LOW or HIGH, the pre charging transistors, which are first two pmos transistors in top of the circuit diagram, keep switching without useful computation, resulting in redundant clocking. Clearly, it is necessary to reduce redundant power consumption here. Further, CDMFF has a floating node on critical path because its first stage is dynamic. When clock signal CLK changes from LOW to HIGH, CLKDB will stay HIGH for a short while which produces an implicit pulse window for evaluation. During that window, both the top pmos transistors are off. In addition, if D transits from LOW to HIGH, the pull down network will be disconnected by NMOS transistor N3( which is connected to pass transistor) using data mapping scheme (grounded NMOS transistor N6 from pass transistor turns off N3); If D is LOW, the pull down network is disconnected from GND too. Hence internal node between above pmos circuit and below nmos circuit is not connected with supply Vdd or GND. III. LOW POWER CDMFF BASED PARALLEL COUNTER The proposed architecture of the parallel counter is a sample 8-bit counter. The main structure consists two paths for counting operation one is state look-ahead path (all logic encompassed by the dashed box) and another one is counting path (all logic not encompassed by the dashed box).we construct our counter as a single mode counter, which sequences through a fixed set of pre assigned count states, of which each next count state represents the next counter value in sequence. The counter is subdivided into uniform 2-bit synchronous up counting modules. Next state transitions in counting modules of higher significance are enabled by the state look-ahead path on the clock cycle preceding the state transition. Therefore, all counting modules concurrently transition to their next states at the rising clock edge (CLKIN). A. Architectural Functionality The counting path s counting logic controls counting operations and the state look-ahead path s state look-ahead logic anticipates future states and thus prepares the counting path for these future states. The three module types (module-1, module-2, and module- 3S).Module-1 and module-3 are exclusive to the counting path and each module represents two counter bits.module-2 is the conventional positive edge triggered CDMFF and is present in both paths. In the counting path, each module-3 is preceded by an associated module-2. Module-3 s serve two main purposes. Their first purpose is to generate all counter bits associated with their ordered position and the second purpose is to enable (Irrespective of the generated bit from the state look-ahead path) future states in subsequent module-3 s in conjunction with stimulus from the state look-ahead path. The counter architecture consists of two parts. 1. Counting path: The counting path consists of module-1, module-2 and module-3.the counting path is the way to count sum of all paths from the lower order count to the higher order count. The counting path module-1 is responsible for lower- order bit counting and generates future states for all module-3 s by pipelining in module 1 the outputs of the conventional data mapping flip flops are given back to the inputs of nand gates the three nand gates do addition operation, the outputs of the module1 are inputs of state look ahead logic, it will enable futures states through the state lookahead path. The placement of module-2s in the counting path is critical to the novelty of counter structure. Module-2s in the counting path act as a pipeline between the module-1 and module-3 1 and between subsequent modules- 3S. Fig2: CDMFF low power parallel counter Fig3: module1 hardware schematic diagram
The module-2s in the counting path provide a 1-cycle look-ahead mechanism for triggering the module-3s, enabling the module-2s to maintain a constant delay for all stages and all module-3s to count in parallel at the rising clock edge instead of waiting for the overflow rippling in a standard ripple counter. The module-1 outputs Q1Q0 and QEN1=Q1 AND Q0. QEN1 is connects to the module-2 s DIN input. other flip-flop design. IV.SIMULATION RESULT Fig5: Schematic Diagram of Module-1 Figure4: module3 hardware schematic diagram 2. State Look-Ahead Path: The state look-ahead path operates similarly to a carry look-ahead adder in that it decodes the low-order count states and carries this decoding over several clock cycles in order to trigger high-order count states. If in case of a carry bit not generated the state look ahead path won t disturb the module-3 S it will make the system remain unchanged. From this the power consumption is also reduced, the state look-ahead logic is principally equivalent to the one-cycle look-ahead mechanism in the counting path. The placement of module-2 in the state look-ahead logic increases counter operating frequency. By removing the lengthy AND-gate rippling and large AND gate fan-in and fan-out typically present in large width parallel counters. The enabling next state s high- order bits depends on early overflow pipelining across clock cycles through the module-2s in the state look-ahead path. This state look-ahead logic organization and operation avoids the use of an overhead delay detector circuit that decodes the low order modules to generate the enable signals for higher order modules, and enables all modules to be triggered concurrently on the clock edge, thus avoiding rippling and long frequency delay. By using the CDMFF Logic family idea we are designing this circuit as well as by using the pass transistor logic we are using only one clocking transistor so it will be consuming only less power in the counter network of the Flip flop when compared to all other circuits. As well as we are having only 14 Transistors excluding the not gates also. So we will be having much reduced power and area when compared to the existing system. At the same time due to the reduced no of transistor count we can reduce the delay oriented things also. Thus we are reducing the overall switching delay and power, area consumption. So this circuit will be acting as good sequential elements when compared to Fig6: Schematic Diagram of Module-3 Fig7: Schematic Diagram of Parallel Counter
Fig8: Output Waveform of Module-1 Fig11:Layout of the proposed design Fig9: Output Waveform of Module-3 Fig12: power characteristics The graph represents the input & output characteristics of our proposed system from that we can clearly understand how it works as parallel counter architecture. There is some nana seconds delay is there even though it s a negligible amount only. Those delays can be further reduced by reducing the sizes of the transistor we are using in this circuit. Or by reducing the nana meter technology also we can reduce the constraints. The Layout design of the proposed new flip- flop is shown in the figure11 the area of that is mentioned at the downside of the layout. The Power consumption characteristics also mentioned in figure 12. Fig10 output waveform of CDMFF parallel counter Table1: comparison of existing parallel counter with proposed parallel counter Circuit Technique Using D flip flop Using CDMFF Power Consumption 1.023mW 0.136mW V.CONCLUSION The proposed architecture design using control data
mapping flip flop shows the power consumption in above table of existing parallel counter with CDMFF, the power is reduced drastically from 1.023mW to 0.136mw., the counter frequency is greatly improved by reducing the transistor count 14T and with 7 clocked transistors and it is useful in advanced circuit design techniques.. In future it can be very suitable for System On Chip SOC applications which will lead us to a brighter tomorrow with low power consumption and Counter circuits are used in digital systems for many purposes. They may count the number of occurrences of certain events, generate timing intervals for control of various tasks in a system, keep track of time elapsed between specific events, and so on. This can be much suitable for application of battery oriented operation for less power and area. REFERENCES [1] S. Abdel-Hafeez, S. Harb, and W. Eisenstadt, High speed digital CMOS divide-by-n frequency divider, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2008, pp. 592 595. [2] Peiyi Zhao, Jason McNeely, WeidongKuang, Nan Wang, and Design of Sequential Elements for Low PowerClocking System IEEE Transaction May 2011 [3] H. Kawaguchi and T. Sakurai, A reduced clockswing flip-flop (RCSFF) for 63% power reduction, IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 807 811, May 1998 [4] M. Alioto, R. Mita, and G. Palumbo, Design of high-speed power-efficient MOS current-mode logic frequency dividers, IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 11, pp. 1165 1169, Nov. 2006. [5] A. Chandrakasan, W. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuits, 1st ed. Piscataway, NJ: IEEE Press, 2001. [6] G. Gerosa, A 2.2W, 80 MHz superscalar RISC microprocessor, IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1440 1454, Dec. 1994. [7] B. Nikolic, V. G. Oklobzija, V. Stojanovic, W. Jia, J. K. Chiu, and M. M. Leung, Improved sense-amplifierbased flip-flop: Design and measurements, IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 876 883, Jun. 2000. [8] K. Yamamoto and M. Fujishima, 4.3 GHz 44 uw CMOS frequency divider, in Proc. IEEE Int. Solid- State Circuits Conf., 2004, pp. 104 105. [9] J. Tschanz, S. Narendra, Z. P. Chen, S. Borkar,M. Sachdev, and V. De, Comparative delay and energy of single edge-triggered & dual edge triggered pulsed flipflops for high-performance microprocessors, in Proc. ISPLED, Huntington Beach, CA, Aug. 2001, pp. 207 212