igital IC-esign Overview Chapter 7 Sequential Logic Static es Registers Clocking ynamic es Registers -C 2 MOS -ORA -TSPC Sequential Logic versus Register Logic Registers es Flip-flops : Level Sensitive Clk Register: Edge Triggered Clk Register State Clk Clk Comb. Logic State Comb. Logic State Comb. Logic State on ata on Clock Edge 1
Clock on-idealities Clock on-idealities Clock skew Spatial variation in temporally equivalent clock edges Both skew and jitter affects the cycle time Skew might lead to race through the registers Clock jitter Temporal variations in consecutive edges of the clock signal Same clock at two different parts of the chip t skew t jitter Clock on-idealities - Feedthrough Example Clock System V (Always on) Φ V Clock feedthrough Global Clock Module 1 A B C Φ 2,5 1,5 0,5-0,5 Φ 0 0,5 1 Time, ns System Clock f SYS = f M Phase Locked Loop M f Enable 2 Enable 3 Local Clock Signals Module 2 Module 3 ata eskew Coupling in dynamic devices can lift the output Clock feedthrough On-Chip Clock Generation Clock Gating Clocked Modules 2
es es s with Memory S SR-latch (00 not allowed) JK-latch (all inputs allowed) Static Positive Feedback ynamic R -latch most important in CMOS sequential Circuits. -latch realized with a "0" "1" Often in SP ASICs with continuous refresh relatively small number of transistors "1" "0" Capacitive Storage Static 1 Weak inv. Static 2 8 Transistor -latch using weak devices Weak inv. Positive Feedback 8 Transistor -latch using transmission gates 3
Static 3 SRAM (Cross-Coupled verters) Word Select 10 Transistor -latch using clocked inverters Open during read/write ynamic es Charge Sharing -latch using capacitor storage Good esign Charge sharing when the inner transistors switch The parasitic capacitance is often enough ischarged during high Φ 4
Race Problem Register: Master-Slave es =1 X Signal race when the latch is open 1 2 1 The Master- Slave register is not signal transparent 2 X ing the Functionality of the Logic Serial Scan-based Two Modes A long pipelined chain with combinatorial logic Scan in (serial) An enormous amount of test vectors will be needed Feedback makes the problem even worse Re egister Re egister Re egister Parallel in Register Register Register Scan out (serial) Parallel out patterns in parallel? ormal mode - -bit wide registers Scan mode - serial shift registers 5
Scan Register Based Serial-Parallel Register Serial Serial I0 I1 I2 I3 Scan Scan OUT0 OUT1 OUT2 OUT3 TEST cycles =normal =scan 1 cycle Φ1 Φ2 Scan chain of clock cycles in test sequence MUX or Pass Transistors ormal mode Parallel Scan mode Serial and Parallel Parallel put Logic Parallel put Scan Register Based Scan in a atapath serial cycles 1 cycle to evaluate logic serial cycles A B [1] [0] SCAI [2] [3] Com mbinational Logic Com mbinational Logic Com mbinational Logic + [4] COMP COMPI Partial Scan [5] SCAOUT OUT 6
Clocking Two-Phase Clocking True single phase clocking (TSPC) on-overlapping Overlapping Two phase Pseudo four phase, safe and slow Ext. 0 1 1 0 1 0 1 0 2 1 Ext. 2 1 Overlapping 1 1 on-overlapping 2 2 on-overlap Overlap Pseudo Four-Phase Clocking Single-Phase Clocking Safe and Slow Large Clock Bus Two phases but only one clock wire Ext. 1 1 1 2 (Reg) (Reg) (Reg) (Reg) 2 2 1 2 Clock Wire 7
Static Registers ynamic Register: C 2 MOS 1 2 1 1 1 2 2 2 1 2 p Four clock phases 1 2 C 2 MOS: Pipelining C 2 MOS: Overlapping Clock oninverting logic oninverting logic =1 =0 Overlapping clock allowed if non-inverting logic Transparent register if inverting logic 8
C 2 MOS: Overlapping Clock ORA (O RAce) =1 =0 P PU P PU Module: Precharge on =0 Module: Precharge on =1 Combines np-logic and C 2 MOS True Single Phase Clocking (TSPC) True Single Phase Clocking (TSPC) -Block P-Block -Block P-Block P P From P-Blocks P From other -Blocks PU To -Blocks 9
TSPC Reliability TSPC Reliability X The clock edge must be sharp to avoid transparency when the signal comes from the previous block P P P P OK P P X Both -MOS are conducting X 10