Intel Q3GM ES 32 nm CPU (from Core i5 660)

Intel Q3GM ES Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com

Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 1.7 Brief Comparison to Intel 45 nm Process Technology 2 Device Overview 2.1 Package and Die 2.2 CPU (8PWSCA Die Markings) Die Features 3 Layout Feature Analysis 3.1 Overview 3.2 Selected Metallization and Via Layout Features 3.3 Selected Gate and Diffusion Level Layout Features 4 CPU (8PWSCA Die Markings) Die Process Analysis 4.1 General Structure 4.2 Dielectrics 4.3 Metals 4.4 Vias and Contacts 4.5 Transistor Overview 4.6 PMOS Transistors 4.7 NMOS Transistors 4.8 Selected Transistor Gate Metal Features 4.9 Isolation 4.10 Wells and Substrate 5 SRAM Analysis 5.1 Overview and Schematic 5.2 L3 Cache (High Density) SRAM Plan-View Analysis 5.3 L3 Cache (High Density) SRAM Cross-Sectional Analysis 5.4 Plan View L1 and L2 Cache SRAM Analysis

Structural Analysis 6 Materials Analysis 6.1 Overview 6.2 Dielectrics 6.3 Metals 6.4 PMOS Transistors 6.5 NMOS Transistors 7 Critical Dimensions 7.1 Die Utilization 7.2 Package, Die and Standard Logic Cell Size 7.3 Dielectrics 7.4 Metals 7.5 Vias and Contacts 7.6 Transistors 7.7 Isolation 7.8 Wells and Substrate 7.9 L3 Cache SRAM 8 References 9 Statement of Measurement Uncertainty and Scope Variation About Chipworks

Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Package Edge 2.1.4 Package and Lid 2.1.5 Package X-Ray 2.1.6 Package X-Ray CPU Die 2.1.7 Solder Bump Array 2.1.8 CPU Die Photograph (8PWSCA Die Markings) 2.1.9 8PWSCA Die Markings 2.1.10 8PWSCA Die Markings (RDL Removed) 2.1.11 8PWSCA Die Photograph (RDL Removed) 2.1.12 Metal 1 CPU Die Photograph 2.1.13 Analysis Sites 2.1.14 8PIRCV (GPU) Die Photograph 2.1.15 8PIRCV (GPU) Die Markings 2.2.1 CPU Die Corner A 2.2.2 CPU Die Corner B 2.2.3 CPU Die Corner C 2.2.4 CPU Die Corner D 2.2.5 SEM of CPU Die Corner (Passivation Removed) 2.2.6 High Density Bump Via Windows (on CPU) 2.2.7 CPU Die Utilization Analysis 2.2.8 CPU Standard Logic Cell Size 3 Layout Feature Analysis 3.2.1 Metal 6 and Via 6s 3.2.2 Metal 5 and Via 5s 3.2.3 Minimum Pitch Via 5s 3.2.4 Metal 4 and Via 4s 3.2.5 Metal 3 and Via 3s 3.2.6 Metal 2 and Via 2s 3.2.7 Metal 1 Pitch 3.2.8 Metal 1 and Via 1s (A) 3.2.9 Metal 1 and Via 1s (B) 3.2.10 Metal 1 Routing and Via 1s 3.2.11 Metal 1 Line End Uniformity (A) 3.2.12 Metal 1 Line End Uniformity (B) 3.3.1 Contacted Gate Pitch 3.3.2 Multiple Width Gate Metal 3.3.3 General Gate and Local Interconnect Layout 3.3.4 Gate End Uniformity 3.3.5 Diffusion Level Layout (A)

Overview 1-2 3.3.6 Diffusion Level Layout (B) 3.3.7 Diffusion Level Layout (C) 4 CPU (8PWSCA Die Markings) Die Process Analysis 4.1.1 CPU Die (8PWSCA Die Markings) Thickness 4.1.2 General Die Structure 4.1.3 Die Edge 4.1.4 Detail of Die Edge 4.2.1 Passivation 4.2.2 TEM of ILD 8 4.2.3 ILD 1 ILD 7 Overview (Die Seal) 4.2.4 TEM of ILD 7 4.2.5 TEM of ILD 6 4.2.6 TEM of ILD 5 4.2.7 TEM of ILD 4 4.2.8 TEM of ILD 3 4.2.9 TEM of ILD 2 4.2.10 TEM of ILD 1 4.2.11 TEM of PMD 4.3.1 Metal 9 Thickness 4.3.2 TEM of Metal 9 Seed Layer 4.3.3 TEM of Metal 8 4.3.4 TEM of Metal 8 Liner 4.3.5 TEM of Metal 7 4.3.6 TEM of Metal 6 4.3.7 TEM of Metal 5 4.3.8 TEM of Metal 4 4.3.9 TEM of Metal 3 4.3.10 TEM of Metal 2 4.3.11 TEM of Metal 1 4.3.12 TEM of Metal 1 Liner 4.4.1 Minimum Pitch Via 8s 4.4.2 Via 8 Profile 4.4.3 TEM of Via 8 Liner 4.4.4 TEM Minimum Pitch Via 7s 4.4.5 TEM of Via 7 4.4.6 TEM of Via 6s 4.4.7 TEM of Via 5 4.4.8 TEM of Via 4 4.4.9 TEM of Via 3 4.4.10 TEM of Via 2 4.4.11 TEM of Via 1 4.4.12 TEM of Via 0 and Metal 0 Local Interconnect 4.4.13 TEM of Metal 0 Local Interconnect Strap 4.4.14 TEM Detail of Metal 0 Local Interconnect Strap 4.4.15 TEM of Metal 0 Gate Contact

Overview 1-3 4.4.16 TEM of Contact 4.4.17 TEM of Contact to N + Diffusion 4.4.18 TEM of Contact to P + Diffusion 4.4.19 TEM of Contact Over STI 4.4.20 TEM Detail of Contact Over STI 4.6.1 PMOS Gate Diagram 4.6.2 TEM Overview of PMOS Metal Gates 4.6.3 TEM of PMOS Gates and SiGe Thickness 4.6.4 TEM of PMOS Gates and SiGe Width 4.6.5 Dark Field TEM of SiGe 4.6.6 TEM of PMOS S/D Region 4.6.7 TEM of PMOS Gate Dielectric and Work Function Metal 4.6.8 TEM of PMOS Gate Fill 4.6.9 TEM of Minimum Gate Length PMOS 4.6.10 TEM of PMOS (A) 4.6.11 TEM of PMOS (B) 4.6.12 TEM of PMOS (C) 4.6.13 TEM of Dummy Gate Metal (PMOS) 4.7.1 TEM of NMOS Gate Diagram 4.7.2 TEM Overview of NMOS Metal Gates 4.7.3 TEM of NMOS Gate Dielectric and Work Function Metal 4.7.4 TEM of NMOS Gate Fill 4.7.5 Dark Field TEM of Wide NMOS Gate 4.7.6 TEM of NMOS S/D Region 4.7.7 TEM of Wide NMOS Gate 4.7.8 TEM of Overview of NMOS Gates 4.7.9 TEM of NMOS (A) 4.7.10 TEM of NMOS (B) 4.7.11 TEM of NMOS (C) 4.8.1 TEM of NMOS Gate Wrap 4.8.2 TEM of PMOS/NMOS Transition 4.8.3 TEM of PMOS/NMOS Transition Detail 4.8.4 Gate End-to-End Space 4.9.1 TEM of Minimum Width STI 4.9.2 TEM of Gate Metal Over STI 4.10.1 SRP of Epi and Substrate 4.10.2 SIMS of Substrate 4.10.3 SCM of Substrate Die Edge 4.10.4 SCM of N and P-Wells, Epi, and Substrate Logic Region 4.10.5 SCM of N-Well/P-Well Boundary 4.10.6 SCM of N-Well

Overview 1-4 5 SRAM Analysis 5.1.1 6T SRAM Schematic 5.2.1 L3 Cache SRAM at Metal 3 5.2.2 L3 Cache SRAM at Metal 2 5.2.3 L3 Cache SRAM at Metal 1 5.2.4 L3 Cache SRAM at Gate Level 5.2.5 L3 Cache SRAM at Gate Metal 0 TEM 5.2.6 L3 Cache SRAM at Gate, Metal 0 Levels TEM 5.2.7 L3 Cache SRAM at Gate, W/TiN Contact, and Diffusion Levels TEM 5.2.8 L3 Cache SRAM at Diffusion Level 5.3.1 L3 Cache NMOS Pull-Down and Access Transistors 5.3.2 L3 Cache NMOS Pull-Down and Access Transistor 5.3.3 L3 Cache PMOS Pull-Up Transistors 5.3.4 L3 Cache PMOS Pull-Up Transistor 5.3.5 PMOS Pull-Up Transistor Butt Contacts 5.3.6 PMOS Pull-Up Transistor Butt Contact 5.3.7 NMOS Pull-Down and Access Transistor Offset Contacts 5.3.8 NMOS Pull-Down and Access Transistor Offset Contact 5.3.9 L3 Cache Parallel to Metal Gate 5.3.10 L3 Cache NMOS Pull-Down and PMOS Pull-Up Gate Widths 5.3.11 L3 Cache NMOS Access Gate Widths 5.3.12 L3 Cache NMOS Access Gate Widths with Bitline Contacts 5.3.13 V SS and Bitline Contacts 5.4.1 L1 Cache at Gate Level 5.4.2 L2 Cache at Gate Level 6 Materials Analysis 6.2.1 TEM-EDS Spectrum of Passivation 6.2.2 TEM-EDS Spectrum of ILD 8-2 6.2.3 TEM-EDS Spectrum of ILD 8-1 6.2.4 TEM-EDS Spectrum of ILD 7-2 6.2.5 TEM-EDS Spectrum of ILD 7-1 6.2.6 TEM-EDS Spectrum of ILD 6-2 6.2.7 TEM-EDS Spectrum of ILD 6-1 6.2.8 TEM-EDS Spectrum of ILD 5-2 6.2.9 TEM-EDS Spectrum of ILD 5-1 6.2.10 TEM-EDS Spectrum of ILD 4-2 6.2.11 TEM-EDS Spectrum of ILD 4-1 6.2.12 TEM-EDS Spectrum of ILD 3-2 6.2.13 TEM-EDS Spectrum of ILD 3-1 6.2.14 TEM-EDS Spectrum of ILD 2-2 6.2.15 TEM-EDS Spectrum of ILD 2-1 6.2.16 TEM-EDS Spectrum of ILD 1-2 6.2.17 TEM-EDS Spectrum of ILD 1-1 6.2.18 TEM-EDS Spectrum of PMD 4 6.2.19 TEM-EDS Spectrum of PMD 3

Overview 1-5 6.2.20 TEM-EDS Spectrum of PMD 2 6.2.21 TEM-EDS Spectrum of PMD 1 6.2.22 TEM-EDS Spectrum of STI Fill 6.3.1 TEM-EDS Spectrum of Metal 9 Bulk 6.3.2 TEM-EDS Spectrum of Metal 9 Seed Layer 6.3.3 TEM-EDS Spectrum of Metal 7 Liner 6.3.4 Copper Dopant Survey Site A 6.3.5 Copper Dopant Survey Site B 6.3.6 Copper Dopant Survey Site C 6.3.7 Copper Dopant Survey Site D 6.3.8 Long Count TEM-EDS Spectrum of Metal 3 Body 6.3.9 TEM-EDS Spectrum of Metal 1 Liner 6.4.1 PMOS Gate Diagram 6.4.2 TEM-EDS Spectrum of Gate Cap 6.4.3 TEM-EDS Spectrum of Bulk Gate Fill 6.4.4 TEM-EDS Spectrum of Barrier to NMOS Work Function Tuning Metal 6.4.5 TEM-EDS Spectrum of NMOS Work Function Tuning Metal 6.4.6 TEM-EDS Spectrum of Barrier to PMOS Work Function Metal 6.4.7 TEM-EDS Spectrum of Etch Stop Liner (from PMOS) 6.4.8 TEM-EDS Spectrum of PMOS Work Function Metal 6.4.9 TEM-EDS Spectrum of High-k Gate Dielectric 6.4.10 TEM-EELS of Gate Oxide 6.4.11 TEM-EELS of PMOS Gate Stack 6.4.12 TEM-EDS Spectrum of Channel Region 6.4.13 TEM-EDS Spectrum of PMOS S/D esige 6.4.14 TEM-EDS Line Scan Through esige 6.4.15 TEM-EDS Spectrum of PMOS S/D Silicide 6.5.1 NMOS Gate Diagram 6.5.2 TEM-EDS Spectrum of Residual Etch Stop Liner in NMOS 6.5.3 TEM-EDS of NMOS Gate Sidewall 6.5.4 TEM-EELS Profile of NMOS Gate Stack 6.5.5 TEM-EDS Spectrum of NMOS S/D Silicide 6.5.6 TEM-EELS Profile Through NMOS S/D Region

Overview 1-6 1.2 List of Tables 1 Overview 1.4.1 Available Companion Reports on Intel 32 nm 1.4.2 Device Identification 1.5.1 8PWSCA Die Summary 1.6.1 8PWSCA Die Process Summary 1.7.1 Comparison of Intel 45 nm Process to 32 nm Process 2 Device Overview 2.2.1 CPU Die Utilization 2.2.2 CPU Package, Die, and Standard Logic Cell Size 4 CPU (8PWSCA Die Markings) Die Process Analysis 4.2.1 Dielectric Thicknesses 4.3.1 Metallization Vertical Dimensions 4.3.2 Metallization Horizontal Dimensions 4.4.1 Via and Contact Dimensions 4.5.1 Transistor Horizontal Dimensions 4.5.2 Transistor Vertical Dimensions 4.9.1 STI Critical Dimensions 4.10.1 Die Thickness and Well Depths 5 SRAM Analysis 5.1.1 L3 Cache SRAM Transistor Dimensions 7 Critical Dimensions 7.1.1 Die Utilization 7.2.1 Package, Die, and Standard Logic Cell Size 7.3.1 Dielectric Thicknesses 7.4.1 Metallization Vertical Dimensions 7.4.2 Metallization Horizontal Dimensions 7.5.1 Via and Contact Dimensions 7.6.1 Transistor Horizontal Dimensions 7.6.2 Transistor Vertical Dimensions 7.7.1 STI Critical Dimensions 7.8.1 Die Thickness and Well Depths 7.9.1 L3 Cache SRAM Transistor Dimensions

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