Solid-State Electronics 47 (2003) 49 53 www.elsevier.com/locate/sse Short Communication Electron mobility in MOSFETs with ultrathin RTCVD silicon nitride/oxynitride stacked gate dielectrics K.J. Yang a, *, T.-J. King a,c.hu a, S. Levy b,, H.N. Al-Shareef c a Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA b STEAG CVD Systems, Inc., San Jose, CA 9534, USA c International SEMATECH, Austin, TX 7874, USA Received 2 May 200; accepted 7 July 2002 Abstract Effective electron mobility has been studied in MOSFETs with ultrathin silicon nitride/oxynitride stacked gate dielectrics formed by rapid thermal chemical vapor deposition. The mobility in these devices is degraded compared to those with SiO 2 (the universal mobility curve). Quantitative analysis suggests that the degradation is due to coulombic scattering from both bulk charges in the dielectric and interface trapped charges. Finally, after investigating the impact of process parameters on mobility, it is concluded that interfacial oxynitride grown at higher pressure in nitric oxide is advantageous for achieving thinner effective stack thicknesses and for preserving electron mobility. Ó 2002 Elsevier Science Ltd. All rights reserved. Keywords: Charge scattering; Silicon nitride; Electron mobility; RTCVD. Introduction As lateral device dimensions of MOSFETs are scaled down, the effective thickness of the gate dielectric must also be reduced in order to maintain the gateõs control of the potential in the channel. Direct tunneling leakage current will likely limit the scaling of SiO 2 gate dielectric thickness to.5 nm, depending on the acceptable leakage current and supply voltage V dd, which are dictated by the application. In order to scale the gate dielectric beyond the limit for SiO 2, alternative gate dielectrics must be developed. Although recent literature on alternative gate dielectrics for MOSFETs has focussed on high-j materials such as hafnium oxides and silicates, silicon nitride has the obvious advantage of being a familiar material to the * Corresponding author. Fax: +-707-28-59. E-mail address: kjyang@fermi.eecs.berkeley.edu (K.J. Yang). Now with Cypress Semiconductor Corporation, San Jose, CA 9534, USA. semiconductor industry which is thermally stable with polysilicon as the gate material. As a result, silicon nitride is expected to be the first viable post-sio 2 gate dielectric material. It has been demonstrated that pure silicon nitride deposited directly on silicon results in an interface with poor electrical quality [] due to defect formation related to bonding coordination of the two materials [2]. Recently, other researchers have utilized an oxynitride interfacial layer [3,4] between the silicon substrate and silicon nitride dielectric to alleviate this problem. For a sufficiently thick SiO 2 interfacial layer or reduced nitrogen content at the interface, bonding constraint theory predicts a low density of interfacial defects (i.e. dangling bonds) [2] and thus excellent electrical quality. Such a stacked gate dielectric gives the combined benefits of an excellent SiO 2 -like interface while reducing direct tunneling leakage current and boron penetration, due to the silicon nitride layer. In this work, we perform quantitative analysis of mobility degradation in MOSFETs with such silicon nitride/oxynitride stacked gate dielectrics prepared by rapid thermal chemical vapor deposition (RTCVD). 0038-0/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S0038-0(02)00309-X
50 K.J. Yang et al. / Solid-State Electronics 47 (2003) 49 53 2. Device fabrication The n-channel devices used in these experiments were fabricated on p-type ( 0 0) epitaxial silicon wafers using a standard n þ poly-si gate process. Following LOCOS isolation, anti-punchthrough and threshold voltage adjustment implants were performed through 20 nm sacrificial oxide. Following RCA and in situ dry cleaning, the gate dielectrics were formed using a 4-step process [5]. First, the oxynitride interfacial layer was grown in NO at 800 C for 0 s at a pressure of either or 00 Torr. Next, silicon nitride was deposited by RTCVD with a flow ratio SiH 4 /NH 3 of /40 at either 750 or 800 C for 30 s. Post-deposition annealing was performed in 500 Torr NH 3 at 900 C for 30 s. This anneal has been shown to significantly reduce the leakage current in ultra thin nitride films [5]. Finally, the dielectric stack was oxidized in N 2 O at 500 Torr for 30 s to reduce the electron traps in the Si 3 N 4 layer [4]. This step also plays a critical role in controlling the final thickness of the stack layer. The temperature in this step was varied from 750 to 900 C. The splits in gate-dielectric growth conditions are summarized in Table. After dielectric stack formation, undoped polysilicon was deposited as the gate material, implanted with phosphorus, and activated. After gate etch, arsenic was implanted in the source/drain extension regions; following TEOS spacer formation, arsenic was implanted to form the source/drain. Following TiSi formation, fabrication of transistors was completed through first layer metalization, including sintering in forming gas. It has been shown by experiment that electron mobility in the strong inversion regime can be described by a universal function [9] which depends only on the effective vertical field E eff experienced by the carriers and which is independent of the oxide thickness, channel impurity profile, and body bias. In addition, a universal mobility model has been developed [0] which expresses the effective vertical field as a unique function of only the macroscopic parameters V g, V t, and T ox per se. Fig. shows the measured mobility data plotted against E eff for comparison with the universal mobility model, where E eff has been computed using [0] E eff ¼ V g þ V t þ 2a 6T ox ; ðþ where V g is the gate voltage, V t is the threshold voltage, a is the sum of the flatband voltage and the surface potential in the substrate at V g ¼ V t, and T ox is the oxide thickness from capacitance measured in inversion. Using MathiessenÕs rule, the contributions of different scattering mechanisms (coulombic, phonon, and surface-roughness) can be combined l ¼ þ þ : l coul l ph l sr ð2þ The universal mobility model approximately represents phonon and typical roughness scattering. There- 3. Mobility measurement Effective electron mobility of long-channel (20 20 lm) n-mosfets was determined [6] by measuring (on the same device) both the gate-to-channel capacitance [7] and drain current as functions of gate voltage. Drain current data measured at drain voltages from 20 to 50 mv were used to estimate the limit of (I d =V d )as V d! 0 [8]. This extrapolation allows for more accurate extraction of mobility at low vertical electric field, which is of particular interest in this work. Table Gate-dielectric growth conditions Wafer NO (Torr) CVD ( C) NH 3 ( C) N 2 O( C) A 750 900 900 B 00 750 900 900 2A 800 900 850 2B 00 800 900 850 3A 750 900 800 3B 00 750 900 800 Fig.. The dependence of the effective mobility l eff of inversion-layer electrons on the effective vertical electric field E eff for a variety of growth conditions. The mobility is more severely degraded in the low-field regime and approaches the universal curve at higher fields. Samples whose interfacial oxynitride layer was grown at 00 Torr in nitric oxide (filled symbols) have higher mobility than those whose interface was grown at Torr (open symbols). All samples received 900 C NH 3 anneal. Measurements were performed on large devices (L=W ¼ 20=20 lm).
K.J. Yang et al. / Solid-State Electronics 47 (2003) 49 53 5 fore, the deviation from the universal mobility curve can be assumed to be a combination of coulombic and excess surface-roughness scattering. Typically, coulombic scattering dominates in the low-field regime while surface-roughness scattering becomes significant in the high-field regime. In addition, l coul is expected to increase with increasing inversion charge, due to screening of charged scattering centers []. l sr, on the other hand, is expected to decrease with increasing vertical field. Examining the l eff ðe eff Þ curves in Fig., significant degradation is occurring in the low-field regime, which indicates that coulombic scattering is the dominant mechanism reducing the carrier mobility. Neglecting the contribution of excess surface-roughness scattering in this low-field regime, the coulombic component of the mobility can be extracted by using the following equation: ¼ l coul l : l univ ð3þ Fig. 2 shows the dependence of the coulombic mobility l coul as a function of inversion charge density Q inv for a variety of gate-dielectric growth conditions. Two different behaviors are observed. Samples with higher mobility in the unscreened limit (dashed lines) have coulombic mobility which is a function of Q 0:6 inv while the other samples (solid lines) demonstrate coulombic mobility which is a function of Qinv :0. Linear screening of charged scattering centers has often been reported in the past (see, for example, [,2]). However, it has been suggested that screening of interface charges is sub-linear [2] due to the increased scattering as the electron distribution shifts towards the interface and therefore closer to the scattering centers. In contrast, linear screening suggests that the distance between the carriers and the scattering centers does not change significantly with increasing bias. One possible physical explanation regarding the origin of linearly screened scattering centers could be that the charges at the nitride oxynitride (interdielectric) interface or in the bulk of the dielectric are far away from the oxynitride silicon interface compared with the modulation of the distance of the carriers from the oxynitride silicon interface. 4. Coulombic mobility model We propose a model for l coul which combines these components according to MathiessenÕs rule ¼ þ ¼ l coul l bulk l int b þ Q inv c Q 0:6 inv ; ð4þ where b and c relate to scattering by charges in the bulk of the dielectric and by those near the oxynitride silicon interface, respectively. This model has been successfully applied to fit the measured data with only b and c as fitting parameters, as shown in Fig. 3. The sample represented by solid circles did not follow a simple powerlaw dependence in Fig. 2. As a result, the model does not provide a good fit to the data for this sample in Fig. 3. The mobility degradation mechanism in this sample requires further investigation. In addition, the model for the sample with the highest mobility deviates from the experimental data as the measured mobility approaches the theoretical universal mobility curve. µ Fig. 2. The dependence of the coulombic mobility as a function of inversion charge density for a variety of growth conditions. Two different behaviors are observed. Samples with higher mobility in the unscreened limit (- - - -) have coulombic mobility which is a function of Qinv 0:6 while the other samples ( ) exhibit coulombic mobility which is a function of Q :0 inv. Fig. 3. The dependence of the effective mobility l eff of inversion-layer electrons on the effective vertical electric field E eff can be modeled using the universal mobility model [0] and a new model for coulombic mobility which uses two fitting parameters, b and c.
52 K.J. Yang et al. / Solid-State Electronics 47 (2003) 49 53 Table 2 Electrical properties Wafer CET (nm) Coulomb mobility (cm 2 /V s) A 3.62 67 B 3.6 277 2A 3.35 47 2B 3.0 4 3A 3.08 77 3B 2.60 72 Fig. 4. Relative contribution of the linearly screened (l bulk ) and sub-linearly screened (l int ) components of coulombic mobility at Q inv ¼ lc/cm 2 as a function of the dielectric thickness extracted from capacitance measured at V g ¼ 2 V. Smaller values on the graph indicate the more dominant component. Although the l bulk term is the dominant term for thicker dielectrics, as the effective thickness is decreased, the relative contribution of the l int component generally increases. Fig. 4 shows the relative contribution of the linearly screened (l bulk ) and sub-linearly screened (l int ) components of coulombic mobility at Q inv ¼ lc/cm 2 as a function of the capacitance-equivalent thickness (CET). CET is the effective SiO 2 -equivalent thickness, extracted from capacitance measured at V g ¼ 2 V. Smaller values on the graph indicate the more dominant scattering component. Although the l bulk term is the dominant term for thicker dielectrics, as the effective thickness is decreased, the relative contribution of the l int component generally increases. As a result, the screening of the charged scattering centers by the inversion charge is reduced as the oxide thickness is reduced. 5. Effects of process conditions Table 2 summarizes the electrical properties of the samples with dielectrics grown under different conditions. CET was extracted as described in the previous section. The coulomb mobility (l coul ) was measured at Q inv ¼ lc/cm 2. Those samples whose interfacial oxynitride layers were grown in nitric oxide at 00 Torr (B-group) have thinner CET than those whose interfacial layers were grown at Torr (A-group). In addition, samples B and 2B have significantly higher effective electron mobility than samples A and 2A. A previous study [3] examined the effect of varying the pressure of a rapid thermal treatment at 050 C for 80 s in a nitric oxide ambient. XPS analysis revealed that for low pressure (0.75 Torr), Si 3 N 4 was the dominant compound in the film, and the nitrogen was located mainly near the dielectric-silicon interface. Increasing the pressure was shown to result in a more SiO 2 -like film. It is expected that a more SiO 2 -like film at the dielectricsilicon interface will result in higher mobility [2]. It has also been observed [4,5] that the incubation time after which nitride deposition commences is greater for deposition on SiO 2 than on Si which has been cleaned in situ with HF vapor. We hypothesize that the deposited nitride is thinner for an interfacial layer grown at 00 Torr because the incubation time is greater for deposition on a SiO 2 -like layer than for deposition on a Si 3 N 4 -like layer grown at Torr. 6. Conclusion The effective electron mobility for oxynitride/nitride stacked gate dielectrics has been examined. The mobility is shown to be degraded by coulombic scattering from interface charges and bulk dielectric charges probably located at the silicon oxynitride/nitride interface. In this study, those samples which had their interfacial oxynitride layers grown at 00 Torr in nitric oxide yielded thinner effective stack thicknesses and higher mobility than those whose interfacial layers were grown at Torr. It is suggested that these benefits are due to the formation of an interfacial dielectric with a more SiO 2 -like character which shifts the charged scattering centers away from the silicon interface. Acknowledgements This work was supported by the Semiconductor Research Corporation under contract 98-BC-66.06, the University of California Semiconductor Manufacturing Alliance for Research and Training (UC-SMART) under contract SM-98-0, and the National Defense Science and Engineering Graduate (NDSEG) fellowship.
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