MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations Yee-Chia Yeo, Member, IEEE, Tsu-Jae King, Senior Member, IEEE, and Chenming Hu, Fellow, IEEE Abstract In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high- gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies. Index Terms Direct tunneling, gate-leakage current, highgate dielectrics, MOSFETs. I. INTRODUCTION REDUCING the gate dielectric thickness raises the MOSFET drain current or allows the supply voltage to be reduced while maintaining an acceptable drain current and facilitates the reduction of gate length by the suppression of short-channel effects. Aggressive scaling of CMOS technology in recent years has reduced the silicon dioxide (SiO ) gate dielectric thickness below 20 Å (see Fig. 1) [1]. Major causes for concern in further reduction of the SiO thickness include increased poly-silicon (poly-si) gate depletion, gate dopant penetration into the channel region, and high direct-tunneling gate-leakage current, which leads to questions regarding dielectric integrity, reliability, and stand-by power consumption. The increased gate-leakage current is a well-recognized challenge to continued MOSFET scaling [2], [3]. As a result, there is immense interest in alternative gate dielectrics with higher relative permittivities [1] [3]. The equivalent SiO thickness of a gate dielectric with relative permittivity and a physical thickness can be written as (, where is the relative permittivity of SiO. For a given equivalent SiO thickness, using a high- gate dielectric with a physical thickness larger by a Manuscript received August 1, 2002; revised December 3, The work of Y.-C. Yeo was supported by the NUS OGS Award, Singapore, and the IEEE Electron Devices Society Graduate Student Fellowship Award. The review of this paper was arranged by Editor R. Singh The authors are with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA USA ( [email protected]). Digital Object Identifier /TED Fig. 1. Scaling trend of the MOSFET gate dielectric thickness. The projected range of equivalent SiO thickness t (left axis) for high-performance logic applications taken from the latest update of the ITRS [1] is plotted using bars. The supply voltages are also indicated. Assuming the most conservative t suggested by ITRS, i.e., the largest value for each bar, the gate-leakage current density through SiO (right axis) is calculated and plotted as the solid line. Even with conservative t scaling, excessive gate leakage prohibits continued gate-dielectric scaling using SiO, and prompts the search for an alternative gate dielectric. factor of compared with SiO, achieves significant suppression of the direct-tunneling gate current and therefore results in considerable reduction in power consumption. Many materials systems are currently under consideration as potential replacements for SiO, which has been in use for more than three decades. Gate dielectrics such as silicon nitride (Si N ) or oxynitride (SiO N ) [4] [10], zirconium oxide (ZrO ) [11], hafnium oxide (HfO ) [12] [14], aluminum oxide (Al O ) [15], and lanthalum oxide (La O ) [15] have been actively investigated. However, replacing SiO with an alternative gate dielectric is not as simple and straightforward as it may appear. A systematic consideration of the required properties of gate dielectrics reveals a number of key guidelines for selecting an alternative gate dielectric. Basic material properties such as dielectric permittivity, band gap, band alignment with respect to silicon, thermodynamic stability, film morphology and uniformity, interface quality, and reliability are particularly important [2], [16], [17]. In addition, process integration issues, such as process compatibility and compatibility with the current, or expected materials such as metal gates to be used in future CMOS devices, must also be taken into account [18], /03$ IEEE

2 1028 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 [19]. At present, many dielectrics appear favorable in some of these aspects, but very few materials are promising with respect to all of these guidelines. Impressive progress has been made in recent years, resulting in the demonstration of alternative gate dielectrics with equivalent SiO thicknesses in the sub-10-å regime [7], [15]. While a lot of experimental work on these dielectrics has been performed [4] [15], little has been done with their potential scalability, taking into consideration specifications such as supply voltage and off-state gate-leakage current as given in the International Technology Roadmap for Semiconductors (ITRS) [1]. Since the search for a suitable dielectric candidate involves immense research efforts, and the key motivation for replacing SiO with high- materials is leakage reduction, it is important to ensure that the selected material is highly scalable and usable for many future generations of technology. We have recently presented an accurate direct-tunneling model for the Si N gate dielectric [8] and projected its scaling limits for high-performance and low-power applications based on the 1999 ITRS [20]. In this paper, we extend a similar analysis to other promising high- gate dielectrics, such as HfO,AlO, and La O using specifications in the updated ITRS [1]. Accurate models for the direct-tunneling current through these high- gate dielectrics are presented, and important material parameters such as the tunneling effective mass are extracted for the first time. We also introduce a gate dielectric figure-of-merit based on the direct-tunneling model for comparing the relative advantages of the various gate dielectrics. The scaling limits of high- gate dielectrics are then explored based on their direct-tunneling characteristics and the gate-leakage requirements for future CMOS technology generations. We also provide guidelines for the selection of gate dielectrics to satisfy the off-state leakage current requirements in high-performance and low-power applications. II. DIRECT TUNNELING GATE CURRENT A. Theoretical Model The direct-tunneling gate-current density in CMOS transistors can be accurately modeled by a semi-empirical equation [8], [21], given by is similar to the direct-tunneling model presented in [22] which is based on the Wentzel Kramers Brillouin (WKB) approximation [23] and its assumed independent and elastic electron processes with a one-band parabolic dispersion relation [24], [25]. The empirical correction factor constitutes the major difference between the models in [21] and [22]. In (2), is a fitting parameter, and is the conduction band offset (used for ) or valence band offset (used for ) between Si and the gate dielectric. The exponential factor accounts for secondary effects such as the energy dependence of the densities of states at the electrode interface and effective masses in the dielectric, and affects the curvature of the tunneling current versus voltage characteristic. These effects were neglected in [22]. The factor in (2) ensures a zero at zero. represents the density of carriers in the inversion or accumulation layer in the injecting electrode, and can be written as where is equal to, is the Boltzmann s constant, is the absolute temperature, is the threshold voltage, is the flatband voltage, and is the effective gate voltage after accounting for the voltage drop across the poly-si gate depletion region. The rate of increase of the subthreshold carrier density with is dictated by ( where is the subthreshold swing), which is positive for N-MOS transistors and negative for P-MOS transistors. The effective gate voltage can be obtained by solving the Poisson equation in the poly-si gate under the depletion approximation, and can be shown to be given by [26] (2) (3) (4) where is the electronic charge, is the Planck s constant, is the dielectric permittivity, is the physical thickness of the gate dielectric, is the tunneling barrier height in ev, is the carrier effective mass in the dielectric, is the voltage across the dielectric, and is the electric field in the dielectric. The index indicates the dominant tunneling mechanism, such as electron tunneling from conduction band (ECB), and hole tunneling from valence band (HVB) [8], [21]. Equation (1) (1) where and are the dielectric constants of the gate dielectric and silicon, respectively, is the doping concentration in the poly-si gate, and is the surface potential of the silicon substrate. Equations (1) (4) predicts all the significant gate-tunneling current components, including electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence band (HVB) [21], and have been incorporated in the latest version of the widely used Berkeley Short-Channel IGFET Model (BISM) model [27]. For circuit design and simulation using the most advanced technology, it would be useful to account for the gate-leakage current using an accurate model. This paper presents one of the first efforts in

3 YEO et al.: MOSFET GATE LEAKAGE MODELING AND SELECTION GUIDE 1029 TABLE I TUNNELING BARRIER HEIGHTS 8,TUNNELING EFFECTIVE MASSES m, AND RELATIVE PERMITTIVITIES FOR SEVERAL GATE DIELECTRICS. TUNNELING EFFECTIVE MASSES ARE DERIVED FROM A FIT TO EXPERIMENTAL J V DATA USING A THEORETICAL MODEL a ECB: Direct tunneling of electron from Si conduction band. HVB: Direct tunneling of hole from Si valence band. b Theoretical calculation using band structures obtained by the tight-binding method [28]. c From [29]. d From [8]. e Atomic nitrogen concentration of the Remote Plasma Nitrided (RPN) oxide or RPN-SiON is 7.4% [10]. Barrier height is interpolated from those of SiO and Si N, and is deduced from t and physical dielectric thickness. fis a fitting parameter that accounts for secondary effects such as energy dependence of density of states and tunneling mass, and affects the curvature of the J V curve [21]. Fig. 2. Extraction of material parameters for (a) JVD Si N (JVD-Si N ), (b) HfO, (c) Al O, and (d) La O by fitting the direct-tunneling gate-current model (line) to experimental gate-current density J versus (symbols) gate voltage V data. Note that JVD-Si N contains 15% oxygen [4] and is actually N-rich SiO N. the extraction of material parameters of new gate dielectrics for device and circuit simulations, and for the evaluation of advanced technologies. B. Experimental Data and Extraction of Material Parameters Fig. 2 shows the excellent agreement between the model (lines) and experimental data (symbols) for Si N [8], HfO [12], Al O [15], and La O [15]. The tunneling barrier heights between the gate dielectrics and Si are taken from the literature [8], [28], and the main fitting parameter for each dielectric is the tunneling effective mass. The experimental data is taken from selected gate dielectrics with negligible interfacial layers ( 5 Å) compared to the total physical thickness of the gate dielectrics so that the accuracy of the material parameters extraction and model fit using (1) is not expected to be severely affected. Since the HfO,Al O, and La O samples have in the 4.8-to-10.4-Å range while also demonstrating significant gate leakage suppression, any interfacial layer, if present, would have properties closer to the stated dielectric than to silicon oxide. Table I summarizes the important material parameters obtained in this paper. These parameters are useful for accurate modeling of the direct-tunneling current in transistors and circuits and for projecting the scaling potential, i.e., scalability, of these gate dielectrics. This will be illustrated later. Furthermore, these parameters may also be used for the design and optimization of stacked or composite gate dielectrics in transistors [30]. Fig. 3. Extrapolation should be performed with a physics-based direct-tunneling-current model (solid lines). Extrapolation (dashed lines) of gate-current density based on experimental data (symbols) could give overly optimistic projections of the leakage current for high- dielectrics if data points from thick-gate dielectrics dominated by trap-assisted tunneling are included. An important graph to examine is the relationship between the gate-current density and the equivalent oxide thickness at a fixed inversion gate bias. It allows one to extrapolate the increase of with a reduction in. In Fig. 3, the plot at V is illustrated for SiO and HfO. For SiO, excellent agreement between the experimental data and the direct-tunneling model (solid line) is observed for the range of considered. For a high- gate dielectric such as HfO, the dominant leakage mechanism is usually trap-assisted tunneling when the physical thickness is large [29], [32]. Trap-assisted tunneling in thick HfO gate dielectric has been confirmed by the temperature dependence of the leakage current and can be well-modeled by Frenkel Poole conduction. For HfO, this is typically true for above 16 Å [29]. As the physical thickness decreases, direct tunneling becomes the more dominant mechanism. Therefore, extrapolation of experimental

4 1030 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 data on the plot should be done with caution (see Fig. 3). Accurate extrapolation of the gate-current density to very small should be performed with the direct-tunneling model, as illustrated by the solid lines in Fig. 3, and leakage data attributed to trap-assisted tunneling should be ignored. III. SCALABILITY OF GATE DIELECTRICS AND GATE LEAKAGE REQUIREMENT A. Gate Dielectric Figure-of-Merit An important observation is that high- gate dielectrics that are less leaky at a given also have a larger slope in the plot. This is explicated in Fig. 4 for six different gate dielectrics. The trend of converging for the various gate dielectrics in the limit that tends to zero has never been pointed out before. This observation will be quantitatively explained later, but can be intuitively understood. If all other material parameters such as barrier height and effective mass are the same, a dielectric with a higher permittivity will have a larger slope in the plot since the change in the physical thickness for a given change in is larger for the material with a higher permittivity. Fig. 4 indicates that the leakage reduction factor resulting from the replacement of SiO with high- gate dielectrics should become smaller as is scaled down, and that the benefit of high- gate dielectrics diminishes with decreasing. While the permittivity of a gate dielectric is an important parameter, it should also be noted that the direct-tunneling leakage for a given is not solely or exclusively determined by the value of. The tunneling barrier height and the tunneling effective mass also strongly affect the direct-tunneling characteristics, and they should be considered together with in determining the merits of a gate dielectric. A figure-of-merit that accounts for these factors should be considered when assessing a gate dielectric. In view of that, we consider the simplification of the exponent of the direct-tunneling equation (1) using a binomial expansion and neglecting higher order terms. The analysis leads to Fig. 4. Gate-current density J at a fixed-inversion gate bias as a function of the equivalent oxide thickness t for five different gate dielectrics. Solid lines are from the model, and high- gate dielectrics that are less leaky at a given t have a larger slope. The RPN-SiO N data is taken from [10] and contains 7.4% nitrogen. Extraction of gate dielectric scaling limits is also illustrated based on a maximum tolerable gate leakage J of 1 A/cm and the supply voltage V of 1 V. Data points for Al O and La O are not plotted as they were obtained at accumulation biases. which is of the form where is a constant, is a pre-exponential factor, and is entirely dependent on the essential material properties of the gate dielectric,, and. The exponent of (6) indicates that the attenuation of the leakage current at a given is determined by, i.e., a larger reduces more significantly. The simplification exercise just described reveals that, to the first order, the figure-of-merit can be expressed by As increases, and generally, but not always, decrease so that is not a simple function of, as depicted in Fig. 5. Nev- (5) (6) (7) Fig. 5. Material parameters (tunneling barrier height 8, tunneling effective mass m ) as a function of relative permittivity for a few gate dielectrics. The figure-of-merit, in units of (m.ev), is also plotted. ertheless, can be easily determined from the direct-tunneling characteristics for any given dielectric. It is evident from (6) and Fig. 4 that the slope of the plot is directly related to, implying that a dielectric with a higher also has a steeper slope. The figure-of-merit is also a useful quantity that can be directly related to the scaling limit of a gate dielectric. It should be noted that the figure-of-merit is determined to a greater degree of certainty than the extracted material parameters such as the tunneling effective mass. For example, when using the characteristic of a dielectric of a determined for parameter extraction, if a larger barrier height is assumed for the dielectric, the extracted tunneling effective mass would be smaller, and the figure-of-merit as computed using (7) would not be significantly changed. The important inputs

5 YEO et al.: MOSFET GATE LEAKAGE MODELING AND SELECTION GUIDE 1031 that determine the figure-of-merit are the gate-leakage current density versus voltage data and the corresponding equivalent silicon oxide thickness. B. Scaling Limit Projection To explore the scalability of a gate dielectric based on technology requirements [1], it is advantageous to define a scaling limit that is a function of the supply voltage and the maximum tolerable gate-current density. For a given and, we define the scaling limit of a gate dielectric,,tobe (8) It is the minimum below which the direct-tunneling gate current at exceeds. The dashed lines in Fig. 4 illustrate how the scaling limits are obtained for several gate dielectrics when or is specified to be 1.0 V, and the maximum tolerable gate-current density is 1 A/cm. The scaling limit values for the various gate dielectrics obtained in Fig. 4 are plotted (solid circles) as a function of the gate dielectric figure-of-merit in Fig. 6. The data points clearly show that a dielectric with a larger figure-of-merit has a lower scaling limit. Using the definition of outlined in (8) and the approximation for in (6), it follows that Fig. 6. At a fixed V, the figure-of-merit f, as well as the maximum tolerable leakage current J, determine the scaling limit of a gate dielectric. The data points (solid circles) are obtained from the J 0 t plot in Fig. 4, the solid lines are from (10). Therefore, for a fixed and, the scaling limit can be obtained from (9) to be (9) (10) Equation (10) illustrates the inverse relationship between and, and is plotted as solid lines in Fig. 6. Excellent agreement between (10), and the scaling limit data obtained from the direct tunneling model is observed, therefore validating the approximations made in (5) and (6). We may also keep fixed and vary to investigate the impact of a different specification on the scaling limit (see Fig. 6). Increasing pushes the scaling limits of gate dielectrics to lower or more aggressive values. Equation (10) indicates that a larger reduces logarithmically. When is increased from 1 to 1000 A/cm, the scaling limit of SiO is reduced by 6 Å, while that of La O is reduced by less than 2 Å. This shows that the scaling limit improvement with higher leakage tolerance is greater for SiO than for a high- dielectric. The reason is the smaller slope of the plot for SiO compared to that of a high- gate dielectric. The scaling limits can also be reduced if a lower supply voltage is used, but this reduction is less dramatic. Fig. 7 illustrates the versus relationship for a broad range of and for two different gate voltages. The versus plot can be employed for an analysis to obtain the gate dielectric figure-of-merit required to satisfy Fig. 7. Relationship between the scaling limit t and the figure-of-merit f is a function of both J and V. the specifications of a particular technology generation and application. Fig. 8(a) examines the gate dielectric figure-of-merit requirement for high-performance logic applications in the year 2007, where the projected microprocessor physical gate length is 25 nm, supply voltage is 0.7 V, and the range of is 6 11 Å [1]. At this technology node, the maximum tolerable gate dielectric leakage per unit device width for high-performance logic applications is 1 A/ m [1], which translates to a gate-current density of 4000 A/cm.Forconserva- tive gate dielectric scaling using the least aggressive for this technology and application, i.e., 11 Å [1], a gate dielectric with a figure-of-merit larger than 3.84 (indicated by label in Fig. 8) is required. In fact, silicon oxynitride SiO N

6 1032 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 Fig. 8. Analysis of the gate dielectric figure-of-merit requirement for the (a) high-performance and (b) low standby-power technologies in the year The gate voltage V is set to be equal to V. with a figure-of-merit between that of SiO and Si N, i.e.,, would meet the specifications of this technology generation and application for down to 6.4 Å. For below 6.4 Å, e.g., in adopting the most aggressive value of 6 Å suggested for this technology generation and application, a gate dielectric with a figure-of-merit of 7.04 (indicated by in Fig. 8) or larger must be used to sustain a leakage level of less than 4000 A/cm. Fig. 8(b) examines the gate dielectric figure-of-merit requirement for the low standby power technology in the year 2007, where the projected physical gate length is 32 nm, supply voltage is 1.1 V, and the recommended range of is Å [1]. It suggests that Si N is inadequate for satisfying the leakage requirement for low standby-power applications when the is below 16 Å, and that a gate dielectric such as HfO has to be introduced. Fig. 8 illustrates that the need for high- gate dielectrics such as HfO is more urgent for low standby-power applications compared to high-performance logic applications. Recently, promising results have been reported on the development of low standby-power CMOS technology using HfO gate dielectric [33]. Transistors with gate length down to 55 nm, HfO gate dielectric with electrical oxide thickness down to 15 Å, and off-state leakage current of 25 pa/ m were demonstrated [33]. High- gate dielectrics would probably be first introduced for low-power applications in a manufacturing process. Next, we perform a more complete evaluation of the scalability of various gate dielectrics by examining the gate-dielectric scaling limits as a function of the projected technology requirements. Fig. 9 plots as a function of the projected technology requirements for each year of technology introduction. In Fig. 9(a), the specification for high-performance logic applications is considered. For example, in the year 2004 where the gate length will be nm, 9 Å Å, and V, the maximum tolerable for high-performance logic applications is 0.1 A/ m, giving A/cm. With this specification, the scaling limits of SiO and jet-vapor-deposited (JVD)-Si N are 13.0 and 8.7 Å, respectively. This means that silicon oxynitride SiO N would meet the leakage requirement for this technology node even in the most aggressive (i.e., Å) scaling scenario. In fact, a gate dielectric with a would be sufficient to meet the specifications, e.g., an N/O stacked gate dielectric with an equivalent may be used. Note that the maximum tolerable for high-performance logic applications has been dramatically increased in the most recent revision of the roadmap [1], so that SiO N will meet the leakage requirement through This was not the case in earlier versions of the technology roadmap [20]. Increasing or concurs with the motivation to extend the use of SiO N gate dielectric due to its numerous advantages compared to other gate dielectric candidates, e.g., excellent process compatibility, resistance to boron penetration, enhanced hot-carrier reliability, resistance to oxidation, and high breakdown strength. Recently, transistors with 30-nm gate length and a 7-Å SiO N gate dielectric have been demonstrated with excellent electrical characteristics, suggesting that an SiO N gate dielectric can be used at least down to 7 Å for high-performance applications [7]. If higher leakage-current density can be tolerated, the scaling limit of an SiO N gate dielectric can be pushed well below 7 Å. However, it remains to be seen if circuits can be designed with transistors with off-state leakage in the order of 1 A/ m or higher. For the low operating power (LOP) applications, Fig. 9(b) indicates that jet-vapor-deposited (JVD)-Si N or SiO N will not be usable after 2005 if the most aggressive recommended in [1] is adopted. However, if conservative scaling is followed, SiO N gate dielectric will be usable through Considerable challenges in process technology and materials science are encountered in the introduction of an alternative gate dielectric, requiring years of research

7 YEO et al.: MOSFET GATE LEAKAGE MODELING AND SELECTION GUIDE 1033 (a) (b) (c) Fig. 9. Scaling limits (solid lines) of SiO, JVD-Si N, RPN-SiON (7.4% nitrogen by atomic concentration), HfO, Al O, and La O as a function of the technology specifications for (a) high-performance logic, (b) LOP logic, and (c) LSTP technologies. The top horizontal axis plots the off-state leakage I and gate length L specification for the corresponding years of technology introduction (bottom horizontal axis). Specifications of I, L, and V are obtained from the 2001 edition of the ITRS. For each year or L, the ITRS recommends that t lies between t (indicated by open circle) and t (indicated by solid circle), i.e., the gray region represents the recommended t. For a gate dielectric to be usable at a technology node, its scaling limit has to fall within or below the gray region. and development for the identification and qualification of a suitable material. Fig. 9(c) stresses the urgent need for a highgate dielectric for low standby power (LSTP) applications after 2007, and suggests looking beyond HfO and Al O, e.g., La O, for long-term utilization beyond 2010 in the most aggressive scaling scenario. It should be noted that other issues [2] such as dielectric reliability, interfacial quality, trapped charge density, effective mobility, and compatibility with metal gate materials should also be considered in the selection of a gate dielectric in addition to the figure-of-merit or gate-leakage requirement analysis presented in this paper. IV. CONCLUSION Gate-leakage reduction is the key motivation for the replacement of SiO with alternative gate dielectrics. Since the search for a suitable dielectric candidate involves immense research efforts, it is important to ensure that the selected material is highly scalable and usable for many future technology generations. In this paper, we introduced a figure-of-merit for comparing the relative advantages of the various gate dielectric candidates. Important material parameters such as the tunneling effective mass were extracted from the direct-tunneling char-

8 1034 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 acteristics. A method for predicting the scaling limits of gate dielectrics was presented, and the gate-dielectric scaling limits were calculated based on projected technology requirements. Guidelines for the selection of alternative gate dielectrics were provided. For high-performance and low-operating-power logic applications, Si N or SiO N will be usable through A high- gate dielectric has to be introduced by 2007 for low standby-power technologies. Our analysis suggests looking beyond HfO and Al O, e.g., La O, for long-term utilization beyond 2010 in the most aggressive gate dielectric scaling scenario. Further work may be done to include more gate dielectric materials in this analysis and extend this projection for stacked gate dielectrics. REFERENCES [1] International Technology Roadmap for Semiconductors. San Jose, CA, 2001: Semiconductor Industry Association. [2] G. D. Wilk, R. M. Wallace, and J. M. Anthony, High- gate dielectrics: Current status and materials properties considerations, J. Appl. Phys., vol. 89, no. 10, pp , May [3] H.-S. P. Wong, Beyond the conventional transistor, IBM J. Res. Develop., vol. 46, no. 2/3, pp , [4] T.-P. Ma, Making silicon nitride film a viable gate dielectric, IEEE Trans. Electron Devices, vol. 45, pp , Mar [5] X. Guo and T. P. Ma, Tunneling leakage current in oxynitride: Dependence on oxygen/nitrogen content, IEEE Electron Device Lett., vol. 19, pp , June [6] S. C. Song, H. F. Luan, Y. Y. Chen, M. Gardner, J. Fulford, M. Allen, and D. L. Kwong, Ultra thin (<20 Å) CVD Si N gate dielectric for deep-sub-micron CMOS devices, in IEDM Tech. Dig., 1998, pp [7] B. Yu, H. Wang, Q. Xiang, J. X. An, J. Jeon, and M.-R. Lin, Scaling toward 35 nm gate length CMOS, in Proc. VLSI Technol. Meeting, Kyoto, Japan, June 2001, pp [8] Y.-C. Yeo, Q. Lu, W.-C. Lee, T.-J. King, C. Hu, X. Wang, X. Guo, and T.-P. Ma, Direct tunneling gate-leakage current in transistors with ultra-thin silicon nitride gate dielectric, IEEE Electron Device Lett., vol. 21, pp , Nov [9] Q. Lu, Y. C. Yeo, K. Yang, R. Lin, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, D.-L. Kwong, X. Guo, Z. Luo, X. Wang, and T.-P. Ma, Two silicon nitride technologies for post-sio MOSFET gate dielectric, IEEE Electron Device Lett., vol. 22, pp , July [10] C.-H. Chen, Y.-K. Fang, S.-F. Ting, W.-T. Hsieh, C.-W. Yang, T.-H. Hsu, M.-C. Yu, T.-L. Lee, S.-C. Chang, C.-H. Yu, and M.-S. Liang, Downscaling limit of equivalent oxide thickness in formation of ultrathin gate dielectric by thermal-enhanced remote plasma nitridation, IEEE Trans. Electron Devices, vol. 49, pp , May [11] W.-J. Qi, R. Nieh, B. H. Lee, L. Kang, Y. Jeon, K. Onishi, T. Ngai, S. Banerjee, and J. C. Lee, MOSCAP and MOSFET characteristics using ZrO gate dielectric deposited directly on Si, in IEDM Tech. Dig., 1999, pp [12] S. J. Lee, H. F. Luan, W. P. Bai, C. H. Lee, T. S. Jeon, Y. Senaki, D. Roberts, and D. L. Kwong, High quality ultra thin CVD HfO gate stack with poly-si gate electrode, in IEDM Tech. Dig., Dec. 2000, pp [13] L. Kang, K. Onishi, Y. Jeon, B. H. Lee, C. Kang, W.-J. Qi, R. Nieh, S. Gopalan, R. Choi, and J. C. Lee, MOSFET devices with polysilicon on single-layer HfO high-k dielectrics, in IEDM Tech. Dig., 2000, pp [14] J. M. Hergenrother et al., 50 nm vertical replacement-gate nmosfet s with ALD HfO and Al O gate dielectrics, in IEDM Tech. Dig., Dec. 2001, pp [15] A. Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen, High quality La O and Al O gate dielectrics with EOT 5 10 angstroms, in Proc. Symp. VLSI Technol., 2000, pp [16] K. Hubbard and D. Schlom, Thermodynamic stability of binary oxides in contact with silicon, J. Mater. Res., vol. 11, p. 2757, [17] J. Robertson and C. W. Chen, Schottky barrier heights of tantalum oxide, barium strontium titanate, lead titanate, and strontium bismuth tantalate, Appl. Phys. Lett., vol. 74, no. 8, pp , Feb [18] Y.-C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T.-J. King, C. Hu, S. C. Song, H. F. Luan, and D.-L. Kwong, Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric, IEEE Electron Device Lett., vol. 22, pp , May [19] Y.-C. Yeo, P. Ranade, T.-J. King, and C. Hu, Effects of high- gate dielectric materials on metal and silicon gate workfunctions, IEEE Electron Device Lett, vol. 23, pp , June [20] International Technology Roadmap for Semiconductors. San Jose, CA: Semiconductor Industry Assoc., [21] W.-C. Lee and C. Hu, Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling, IEEE Trans. Electron Devices, vol. 48, pp , July [22] K. F. Schuegraf and C. Hu, Hole injection SiO breakdown model for very low voltage lifetime extrapolation, IEEE Trans. Electron Devices, vol. 41, pp , May [23] E. Merzbacher, Quantum Mechanics. New York: Wiley, [24] N. G. Tarr, D. L. Pulfrey, and D. S. Camporese, An analytic model for the MIS tunnel junction, IEEE Trans. Electron Devices, vol. ED-30, pp , Dec [25] W. A. Harrison, Tunneling from an independent particle point of view, Phys. Rev., vol. 123, no. 1, pp , July [26] W. Liu et al.. (pp. 2 33, 1999) BSIM3v3.2 MOSFET Model Users manual. [Online]. Available: doc/. [27] C. Hu, BSIM model for circuit design using advanced technologies, in Symp. VLSI Circuits, June 2001, pp The latest version of the BSIM models, BSIM4, incorporates an accurate model for the direct tunneling gate current, and is available at [28] J. Robertson, Band offsets of wide-band-gap oxides and implications for future electronic devices, J. Vac. Sci. Tech. B, vol. 18, no. 3, pp , May/June [29] W. J. Zhu, T.-P. Ma, T. Tamagawa, J. Kim, and Y. Di, Current transport in metal/hafnium oxide/si structure, IEEE Electron Device Lett., vol. 23, pp , Feb [30] H. Y. Yu, Y. T. Hou, M. F. Li, and D. L. Kwong, Hole tunneling current through oxynitride/oxide stack and the stack optimization for p-mos- FETs, IEEE Electron Device Lett., vol. 23, pp , May [31] Z. Xu, M. Houssa, S. D. Gendt, and M. Heyns, Polarity effect on the temperature dependence of leakage current through HfO /SiO gate dielectric stacks, Appl. Phys. Lett., vol. 80, pp , Mar [32] M. Houssa, M. Tuominen, M. Naili, V. Afanas ev, A. Stesmans, S. Haukka, and M. M. Heyns, Trap-assisted tunneling in high permittivity gate dielectric stacks, J. Appl. Phys., vol. 87, no. 12, pp , June [33] S. Pidin, Y. Morisaki, Y. Sugita, T. Aoyama, K. Irino, T. Nakamura, and T. Sugii, Low standby power CMOS with HfO gate oxide for 100-nm generation, in Proc. Symp. VLSI Technol., June 2002, pp Yee-Chia Yeo (S 98 M 03) received the B.Eng (first class honors) and the M.Eng degrees from the National University of Singapore (NUS) and the M.S. and Ph.D degrees from the University of Cailfornia, Berkeley, all in electrical engineering. He had worked on optoelectronic devices at the British Telecommunications Laboratories, Martlesham Heath, U.K., and on strained quantum well lasers at NUS, Singapore. At Berkeley, his research was on sub-100 nm MOS transistor design and fabrication, strained channel transistors, alternative gate dielectrics, and dual-metal gate technology. He is currently with Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan R.O.C., where he works on exploratory technologies for silicon transistors. He has authored or co-authored one book chapter, more than 40 journal and conference papers, and one U.S. patent. Dr. Yeo was awarded the 1995 IEE Prize from the Institution of Electrical Engineers, U.K. In 1996, he received the Lee Kuan Yew Gold Medal and the Institution of Engineers, Singapore, Gold Medal. He also received the NUS Overseas Graduate Scholarship Award and the 2001 IEEE Electron Device Society Graduate Student Fellowship Award.

9 YEO et al.: MOSFET GATE LEAKAGE MODELING AND SELECTION GUIDE 1035 Tsu-Jae King (S 89 M 91 SM 01) received the B.S., M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA. At Stanford University, her research involved the seminal study of polycrystalline silicon-germanium films and their applications in metal-oxide-semiconductor technologies. She joined the Xerox Palo Alto Research Center, Palo Alto, CA, as a Member of Research Staff in 1992, to research and develop polycrystalline-silicon thin-film transistor technologies for high-performance flat-panel display and imaging applications. In August 1996, she joined the faculty of the University of California at Berkeley, where she is now an associate professor of electrical engineering and computer sciences and the director of the U.C. Berkeley Microfabrication Laboratory. Her research activities are presently in sub-50-nm Si devices and technology and thin-film materials and devices for integrated microsystems and large-area electronics. She has authored or co-authored over 150 publications and holds six U.S. patents. Chenming Hu (S 71 M 76 SM 83 F 90) received the B.S. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., and M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, CA. He is the Chief Technology Officer of Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu. He is on leave from the University of California, Berkeley. He leads the development of the industry standard MOSFET model for IC simulation, BSIM. He is a member of the editorial boards of the Journal of Semiconductor Science and Technology and of the Journal of Microelectronics Reliability. He has received UC Berkeley s highest honor for teaching the Distinguished Teaching Award, the Monie A. Ferst Award of Sigma Xi, the W.Y. Pan Foundation Award, and the DARPA Most Significant Technological Accomplishment Award for co-developing the FinFET transistor structure. Dr. Hu received the 2002 IEEE Solid State Circuits Award for the development of the industry standard MOSFET model for IC simulation, BSIM. He also received the 1997 IEEE Jack A. Morton Award for contributions to the physics of MOSFET reliability. He has authored or co-authored five books and over 700 research papers. He is a member of the U.S. National Academy of Engineering, a fellow of the Institute of Physics, and a Life Honorary Professor of the Chinese Academy of Science.