74HC374. Octal 3 State Non Inverting D Flip Flop. High Performance Silicon Gate CMOS

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1 7H37 Octal 3 State Non Inverting Flip Flop High Performance Silicon Gate MOS The 7H37 is identical in pinout to the LS37. The device inputs are compatible with standard MOS outputs; with pullup resistors, they are compatible with LSTTL outputs. ata meeting the setup time is clocked to the outputs with the rising edge of the clock. The Output Enable input does not affect the states of the flip flops, but when Output Enable is high, the outputs are forced to the high impedance state; thus, data may be stored even when the outputs are not enabled. The H37 is identical in function to the H57A which has the input pi on the opposite side of the package from the output. This device is similar in function to the H53A which has inverting outputs. TSSOP T SUFFIX ASE E MARKING IAGRAM H 37 ALYW Features Output rive apability: LSTTL Loads Outputs irectly Interface to MOS, NMOS, and TTL Operating oltage Range: to Low Input urrent:.0 A High Noise Immunity haracteristic of MOS evices In ompliance with the Requirements efined by JEE Standard No. 7A ES Performance: HBM 00 ; Machine Model 0 hip omplexity: 2 FETs or.5 Equivalent Gates This is a Pb Free evice H37 = Specific evice ode A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) ORERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. Semiconductor omponents Industries, LL, 07 March, 07 Rev. 0 Publication Order Number: 7H37/

2 7H37 PIN ASSIGNMENT ATA INPUTS LOK LOGI IAGRAM NONINERTING OUTPUTS OUTPUT ENABLE GN FUNTION TABLE LOK OUTPUT ENABLE PIN = PIN 0 = GN Inputs Output Output Enable lock L H H L L L L L,H, X No hange H X X Z X = don t care Z = high impedance ORERING INFORMATION evice Package Shipping 7H37TR2G TSSOP * 2500 Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BR0/. *This package is inherently Pb Free. 2

3 7H37 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol Parameter alue Unit Supply oltage (Referenced to GN) 0.5 to in Input oltage (Referenced to GN) 0.5 to out Output oltage (Referenced to GN) 0.5 to I in Input urrent, per Pin ± ma I out Output urrent, per Pin ±35 ma I Supply urrent, and GN Pi ±75 ma P Power issipation in Still Air, TSSOP Package 50 mw T stg Storage Temperature 5 to + 0 T L Lead Temperature, mm from ase for 0 Seconds (TSSOP Package) 20 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditio is not implied. Extended exposure to stresses above the Recommended Operating onditio may affect device reliability. erating TSSOP Package:. mw/ from 5 to 25 For high frequency or heavy load coideratio, see hapter 2 of the ON Semiconductor High Speed MOS ata Book (L2/). This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GN ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GN or ). Unused outputs must be left open. REOMMENE OPERATING ONITIONS Symbol Parameter Min Max Unit Supply oltage (Referenced to GN) in, out Input oltage, Output oltage (Referenced to GN) 0 T A Operating Temperature, All Package Types t r, t f Input Rise and Fall Time = (Figure ) = =

4 7H37 ELETRIAL HARATERISTIS (oltages Referenced to GN) Symbol Parameter Test onditio IH Minimum High Level Input oltage out = 0. or 0. I out A IL Maximum Low Level Input oltage out = 0. or 0. I out A OH OL Minimum High Level Output oltage Maximum Low Level Output oltage in = IH or IL I out A in = IH or IL in = IH or IL I out A in = IH or IL I out 2. ma I out ma I out 7. ma I out 2. ma I out ma I out 7. ma () Guaranteed Limit 55 to I in Maximum Input Leakage urrent in = or GN ±0. ±.0 ±.0 A I OZ I Maximum Three State Leakage urrent Maximum uiescent Supply urrent (per Package) Output in High Impedance State in = IL or IH out = or GN in = or GN I out = 0 A Unit ±0.5 ± ±0 A A NOTE: Information on typical parametric values can be found in hapter 2 of the ON Semiconductor High Speed MOS ata Book (L2/).

5 7H37 A ELETRIAL HARATERISTIS ( L = 50 pf, Input t r = t f = ) Symbol Parameter f max Maximum lock Frequency ( uty ycle) () Guaranteed Limit 55 to Unit MHz t PLH t PHL Maximum Propagation elay, Input lock to (Figures and 5) t PLZ t PHZ Maximum Propagation elay, Output Enable to (Figures 3 and ) t PLZ t PHZ Maximum Propagation elay, Output Enable to (Figures 3 and ) t TLH t THL Maximum Output Traition Time, Any Output (Figures and 5) in Maximum Input apacitance pf out Maximum Three State Output apacitance (Output in High Impedance State) pf NOTE: For propagation delays with loads other than 50 pf, and information on typical parametric values, see hapter 2 of the ON Semiconductor High Speed MOS ata Book (L2/). 25, = P Power issipation apacitance (Per Enabled Output)* 3 pf * Used to determine the no load dynamic power coumption: P = P 2 f + I. For load coideratio, see hapter 2 of the ON Semiconductor High Speed MOS ata Book (L2/). 5

6 7H37 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TIMING REUIREMENTS ( L = 50 pf, Input t r = t f = ) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit Symbol Parameter Figure () t su Minimum Setup Time, ata to lock 3 t h Minimum Hold Time, lock to ata 3 t w Minimum Pulse Width, lock t r, t f Maximum Input Rise and Fall Times 55 to Min Max Min Max Min Max Unit SWITHING WAEFORMS LOK 0% 0% 0% 0% t r t f t W t PLH t TLH /f max t PHL t THL GN OUTPUT ENABLE t PZH t PHZ t PZL t PLZ 0% 0% GN HIGH IMPEANE OL OH HIGH IMPEANE Figure. Figure 2. ALI ATA GN t su t h LOK GN Figure 3.

7 7H37 TEST IRUITS TEST POINT TEST POINT EIE UNER TEST OUTPUT L * EIE UNER TEST OUTPUT k L * ONNET TO WHEN TESTING t PLZ AN t PZL. ONNET TO GN WHEN TESTING t PHZ AN t PZH. *Includes all probe and jig capacitance Figure. *Includes all probe and jig capacitance Figure lock Output Enable Figure. Expanded Logic iagram 7

8 7H37 PAKAGE IMENSIONS TSSOP ASE E 02 ISSUE 0. (0.00) T L 0. (0.00) T U 2X L/2 PIN IENT U S S 0 (0.00) T SEATING PLANE X K REF (0.00) M T U S S 0 A G H B U J J K K ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ SETION N N N 0.25 (0.00) M N F ETAIL E ETAIL E W NOTES:. IMENSIONING AN TOLERANING PER ANSI YM, ONTROLLING IMENSION: MILLIMETER. 3. IMENSION A OES NOT INLUE MOL FLASH, PROTRUSIONS OR GATE BURRS. MOL FLASH OR GATE BURRS SHALL NOT EXEE 0. (0.00) PER SIE.. IMENSION B OES NOT INLUE INTERLEA FLASH OR PROTRUSION. INTERLEA FLASH OR PROTRUSION SHALL NOT EXEE 0.25 (0.00) PER SIE. 5. IMENSION K OES NOT INLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.0 (0.003) TOTAL IN EXESS OF THE K IMENSION AT MAXIMUM MATERIAL ONITION.. TERMINAL NUMBERS ARE SHOWN FOR REFERENE ONLY. 7. IMENSION A AN B ARE TO BE ETERMINE AT ATUM PLANE W. MILLIMETERS INHES IM MIN MAX MIN MAX A B F G 0.5 BS 0.02 BS H J J K K L.0 BS BS M 0 0 SOLERING FOOTPRINT* PITH X 0.3 X.2 IMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/.

9 7H37 ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution enter for ON Semiconductor P.O. Box 53, enver, olorado 027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada [email protected] N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative 7H373/