NCP3420. MOSFET Driver with Dual Outputs for Synchronous Buck Converters

Transcription

1 MOSFET Driver with Dual Outputs for Synchronous Buck onverters The NP3420 is a single Phase 2 V MOSFET gate driver optimized to drive the gates of both high side and low side power MOSFETs in a synchronous buck converter. The high side and low side driver is capable of driving a 00 pf load with a propagation delay and a 20 traition time. With a wide operating voltage range, high or low side MOSFET gate drive voltage can be optimized for the best efficiency. Internal adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate VBST voltages as high as 35 V, with traient voltages as high as 40 V. Both gate outputs can be driven low by applying a low logic level to the Output Disable () pin. An Undervoltage Lockout function eures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the I with overtemperature protection. Features Thermal Shutdown for System Protection Internal Pulldown Resistor Suppresses Traient Turn On of Either MOSFET Anti ross onduction Protection ircuitry One Input Signal ontrols Both the Upper and Lower Gate Outputs Output Disable ontrol Tur Off Both MOSFETs omplies with VRM0.x and VRM.x Specificatio Undervoltage Lockout Thermally Enhanced Package Available These are Pb Free Devices SO D SUFFIX ASE 75 A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package PIN ONNETIONS BST IN V BST IN V DFN MN SUFFIX ASE 506BJ MARKING DIAGRAMS 3420 ALYW 3420 ALYW SWN PGND SWN PGND (Top View) ORDERING INFORMATION Device Package Shipping NP3420DR2G NP3420MNR2G SO (Pb Free) DFN (Pb Free) 2500 Tape & Reel 00 Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD0/D. Semiconductor omponents Industries, LL, 2009 December, 2009 Rev. 3 Publication Order Number: NP3420/D

2 3 V TSD BST UVLO IN 2 FALLING EDGE DELAY MONITOR 7 SWN FALLING EDGE DELAY MONITOR START STOP MIN OFF TIMER NON OVERLAP TIMERS 4 5 V 6 PGND Figure. Block Diagram PIN DESRIPTION SO DFN Symbol Description BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pi holds this bootstrap voltage for the high side MOSFET as it is switched. The recommended capacitor value is between 00 nf and.0 F. An external diode is required with the NP IN Logic Level Input. This pin has primary control of the drive outputs. 3 3 Output Disable. When low, normal operation is disabled forcing and low. 4 4 V Input Supply. A.0 F ceramic capacitor should be connected from this pin to PGND. 5 5 Output drive for the lower MOSFET. 6 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET. 7 7 SWN Switch Node. onnect to the source of the upper MOSFET. Output drive for the upper MOSFET. 2

3 MAXIMUM RATINGS Rating Value Unit Operating Ambient Temperature, T A 0 to 5 Operating Junction Temperature, T J (Note ) 0 to 50 Package Thermal Resistance: SO Junction to ase, R J Junction to Ambient, R JA (2 Layer Board) Package Thermal Resistance: DFN (Note 2) Junction to ase, R J (From die to exposed pad) Junction to Ambient, R JA /W /W /W /W Storage Temperature Range, T S 65 to 50 Lead Temperature Soldering (0 sec): Reflow (SMD styles only) Pb Free (Note 3) 260 peak JEDE Moisture Seitivity Level SO (260 peak profile) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditio is not implied. Extended exposure to stresses above the Recommended Operating onditio may affect device reliability.. Internally limited by thermal shutdown, 50 min layer board, in 2 u, oz thickness seconds minimum above 237. NOTE: This device is ESD seitive. Use standard ESD precautio when handling. MAXIMUM RATINGS Pin Symbol Pin Name V MAX V MIN V Main Supply Voltage Input 5 V 0.3 V PGND Ground 0 V 0 V BST Bootstrap Supply Voltage Input 35 V wrt/pgnd 40 V 50 wrt/pgnd 5 V wrt/sw 0.3 V wrt/sw SW Switching Node (Bootstrap Supply Return) 35 V D 40 V < V D 0 V < 200 High Side Driver Output BST V 35 V 50 wrt/pgnd 5 V wrt/sw 0.3 V wrt/sw 2.0 V < 200 wrt/sw Low Side Driver Output V V 0.3 V D 5.0 V < 200 IN and ontrol Input 6.5 V 0.3 V Output Disable 6.5 V 0.3 V NOTE: All voltages are with respect to PGND except where noted. 3

4 ELETRIAL HARATERISTIS (Note 4) (V = 2 V, T A = 0 to +5, T J = 0 to +25 unless otherwise noted.) haracteristic Symbol ondition Min Typ Max Unit Supply Supply Voltage Range V V Supply urrent I SYS BST = 2 V, IN = 0 V ma Input Input Voltage High V _HI 2.0 V Input Voltage Low V _LO 0. V Hysteresis 400 mv Input urrent No internal pull up or pull down resistors A Propagation Delay Time t pdl.0 t pdh.0 PWM Input Input Voltage High V PWM_HI 2.0 V Input Voltage Low V PWM_LO 0. V Hysteresis 500 mv Input urrent No internal pull up or pull down resistors A High Side Driver Output Resistance, Sourcing urrent V BST V SW = 2 V (Note 6). 3.0 Output Resistance, Sinking urrent V BST V SW = 2 V (Note 6) SW Pulldown Resitance SW to PGND 0 55 k Output Resistance, Unbiased BST SW = 0 V 0 55 k Traition Times Propagation Delay (Note 5) t r t f t pdh t pdl V BST V SW = 2 V, LOAD = 3.0 nf (See Figure 3) V BST V SW = 2 V, LOAD = 3.0 nf (See Figure 3) Low Side Driver Output Resistance, Sourcing urrent V = 2 V (Note 6). 3.0 Output Resistance, Sinking urrent V PGND = 2 V (Note 6) Output Resistance, Unbiased V = PGND 0 55 k Timeout Delay SW = 0 5 Traition Times Propagation Delay (Note 5) t r t f t pdh t pdl V BST V SW = 2 V, LOAD = 3.0 nf (See Figure 3) V BST V SW = 2 V, LOAD = 3.0 nf (Note 6, t pdh Only) (See Figure 3) Undervoltage Lockout UVLO Startup V UVLO Shutdown V Hysteresis V Thermal Shutdown Over Temperature Protection (Note 6) Hysteresis (Note 6) All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality ontrol (SQ). 5. For propagation delays, t pdh refers to the specified signal going high; t pdl refers to it going low. 6. GBD: Guaranteed by design; not tested in production. Specificatio subject to change without notice

5 V _HI V _LO t pdl t pdh or 0% Figure 2. Output Disable Timing Diagram V PWM_HI IN V PWM_LO t pdl t f 2V 0% 0% t pdh t r t pdl t f t r SW 0% 2V 0% t pdh SW Figure 3. Nonoverlap Timing Diagram 5

6 APPLIATIONS INFORMATION Theory of Operation The NP3420 are single phase MOSFET drivers designed for driving two N channel MOSFETs in a synchronous buck converter topology. The NP3420 will operate from 5 V or 2 V, but have been optimized for high current multi phase buck regulators that convert 2 V rail directly to the core voltage required by complex logic chips. A single PWM input signal is all that is required to properly drive the high side and the low side MOSFETs. Each driver is capable of driving a 3.3 nf load at frequencies up to MHz. Low Side Driver The low side driver is designed to drive a ground referenced low RDS(on) N hannel MOSFET. The voltage rail for the low side driver is internally connected to the V supply and PGND. High Side Driver The high side driver is designed to drive a floating low RDS(on) N channel MOSFET. The gate voltage for the high side driver is developed by a bootstrap circuit referenced to Switch Node (SW) pin. The bootstrap circuit is comprised of an external diode, and an external bootstrap capacitor. When the NP3420 are starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to V through the bootstrap diode See Figure 4. When the PWM input goes high, the high side driver will begin to turn on the high side MOSFET using the stored charge of the bootstrap capacitor. As the high side MOSFET tur on, the SW pin will rise. When the high side MOSFET is fully on, the switch node will be at 2 V, and the BST pin will be at 2 V plus the charge of the bootstrap capacitor (approaching 24 V). The bootstrap capacitor is recharged when the switch node goes low during the next cycle. Safety Timer and Overlap Protection ircuit It is very important that MOSFETs in a synchronous buck regulator do not both conduct at the same time. Excessive shoot through or cross conduction can damage the MOSFETs, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. The NP3420 prevent cross conduction by monitoring the status of the external mosfets and applying the appropriate amount of dead time or the time between the turn off of one MOSFET and the turn on of the other MOSFET. When the PWM input pin goes high, will go low after a propagation delay (tpdl). The time it takes for the low side MOSFET to turn off (tf) is dependent on the total charge on the low side MOSFET gate. The NP3420 monitor the gate voltage of both MOSFETs and the switchnode voltage to determine the conduction status of the MOSFETs. Once the low side MOSFET is turned off an internal timer will delay (tpdh) the turn on of the high side MOSFET Likewise, when the PWM input pin goes low, will go low after the propagation delay (tpd). The time to turn off the high side MOSFET (tf) is dependent on the total gate charge of the high side MOSFET. A timer will be triggered once the high side mosfet has stopped conducting, to delay (tpdh) the turn on of the low side MOSFET Power Supply Decoupling The NP3420 can source and sink relatively large currents to the gate pi of the external MOSFETs. In order to maintain a cotant and stable supply voltage (V ) a low ESR capacitor should be placed near the power and ground pi. A F to 4.7 F multi layer ceramic capacitor (ML) is usually sufficient. Input Pi The PWM input and the Output Disable pi of the NP3420 have internal protection for Electro Static Discharge (ESD), but in normal operation they present a relatively high input impedance. If the PWM controller does not have internal pull down resistors, they should be added externally to eure that the driver outputs do not go high before the controller has reached its under voltage lockout threshold. The NP53 controller does include a passive internal pull down resistor on the drive on output pin. Bootstrap ircuit The bootstrap circuit uses a charge storage capacitor (BST) and the internal (or an external) diode. Selection of these components can be done after the high side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: BST Q GATE VBST where QGATE is the total gate charge of the high side MOSFET, and VBST is the voltage droop allowed on the high side MOSFET drive. For example, a NTD60N03 has a total gate charge of about n. For an allowed droop of 0 mv, the required bootstrap capacitance is 00 nf. A good quality ceramic capacitor should be used. The bootstrap diode must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on SW. The average forward current can be estimated by: IF(AVG) QGATE fmax where fmax is the maximum switching frequency of the controller. The peak surge current rating should be checked in circuit, since this is dependent on the source impedance of the 2 V supply and the ESR of BST. 6

7 2 V 2 V Output Enable PWM in NP3420 Vcc BST IN PGND SW Vout Figure 4. NP3420 Example ircuit 7

8 PAKAGE DIMENSIONS DFN 3x3, 0.5P ASE 506BJ 0 ISSUE O PIN REFERENE 2X X 0.0 2X NOTE D ÇÇÇ ÇÇÇ ÇÇÇ TOP VIEW DETAIL B SIDE VIEW A B E (A3) A A L SEATING PLANE EDGE OF PAKAGE L DETAIL A OPTIONAL ONSTRUTION L DETAIL A OPTIONAL ONSTRUTION NOTES:. DIMENSIONS AND TOLERANING PER ASME Y4.5M, ONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0. MM FROM TERMINAL. 4. OPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D 3.00 BS D E 3.00 BS E e 0.50 BS K 0.20 L L SOLDERMASK DEFINED MOUNTING FOOTPRINT X L X K D2 4 DETAIL A E2 EXPOSED u ÉÉ ÉÉ DETAIL B OPTIONAL ONSTRUTION MOLD MPD 3..5 X e 5 BOTTOM VIEW X b A B NOTE X 0.63 PITH DIMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

9 PAKAGE DIMENSIONS SOI D SUFFIX ASE ISSUE AJ X B Y A 5 4 S 0.25 (0.00) M Y M K NOTES:. DIMENSIONING AND TOLERANING PER ANSI Y4.5M, ONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXESS OF THE D DIMENSION AT MAXIMUM MATERIAL ONDITION THRU ARE OBSOLETE. NEW STANDARD IS Z H G D 0.25 (0.00) M Z Y S X S SEATING PLANE 0.0 (0.004) N X M J MILLIMETERS INHES DIM MIN MAX MIN MAX A B D G.27 BS BS H J K M 0 0 N S SOLDERING FOOTPRINT* SALE 6: mm inches *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, LL (SILL). SILL reserves the right to make changes without further notice to any products herein. SILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SILL data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SILL does not convey any licee under its patent rights nor the rights of others. SILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SILL product could create a situation where personal injury or death may occur. Should Buyer purchase or use SILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold SILL and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SILL was negligent regarding the design or manufacture of the part. SILL is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution enter for ON Semiconductor P.O. Box 563, Denver, olorado 027 USA Phone: or Toll Free USA/anada Fax: or Toll Free USA/anada [email protected] N. American Technical Support: Toll Free USA/anada Europe, Middle East and Africa Technical Support: Phone: Japan ustomer Focus enter Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NP3420/D