MC10EP446, MC100EP V/5 V 8 Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter

Transcription

1 MC1EP446, MC1EP V/5 V 8 Bit CMOS/ECL/TTL ata Input Parallel/Serial Converter escription The MC1/1EP446 is an integrated 8 bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit to 7. The parallel input pins 7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal clock data rate using the CKSEL pin. Control pins are provided to reset () and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip flops are triggered on the rising edge for and the multiplexers are switched on the falling edge of, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, V BB pin is provided for single ended input condition. The 1 Series devices contain temperature compensation network. Features 3.2 Gb/s Typical ata Rate Capability ifferential Clock and Serial Outputs V BB Output for Single-ended Input Applications Asynchronous ata Reset () PECL Mode Operating Range: = 3. V to 5.5 V with V EE = V NECL Mode Operating Range: = V with V EE = 3. V to 5.5 V Open Input efault State Safety Clamp on Inputs Parallel Interface Can Support PECL, TTL or CMOS These evices are Pb Free and are RoHS Compliant LFP 32 FA SUFFIX CASE 873A 1 32 FN32 MN SUFFIX CASE 488AM MARKING IAGRAM* MCxxx EP446 AWLYYWWG xxx = 1 or 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AN82/. ORERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. 1 MCxxx EP446 AWLYYWW Semiconductor Components Industries, LLC, 214 June, 214 Rev Publication Order Number: MC1EP446/

2 MC1EP446, MC1EP V EE P V EF P V EE V BB CKSEL V CF MC1EP446 MC1EP446 V EE S OUT Exposed Pad (EP) S OUT V BB1 CKEN CKEN V EE CKSEL V BB1 CKEN CKEN V EE V EE V CF P V EF P S OUT S OUT V BB2 Warning: All and V EE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. LFP 32 Pinout (Top View) Figure 2. FN 32 Pinout (Top View) Table 1. PIN ESCRIPTION PIN * 7* S OUT, S OUT *, * P, P *, ** CKSEL* CKEN*, CKEN* V CF V EF V BB1, V BB2 V EE FUNCTION ECL, CMOS, or TTL Parallel ata Input ECL ifferential Serial ata Output ECL ifferential Clock Input ECL ifferential Parallel Clock Output ECL Conversion Synchronizing ifferential Input (Reset)*** ECL Clock Input Selector ECL Clock Enable ifferential Input ECL, CMOS, or TTL Input Selector ECL Reference Mode Connection Reference Voltage Output Positive Supply Negative Supply * Pins will default LOW when left open. **Pins will default HIGH when left open. ***The rising edge of will asynchronously reset the internal circuitry. The falling edge of the followed by the falling edge of initiates the conversion process synchronously on the next rising edge of. 2

3 MC1EP446, MC1EP446 Table 2. TRUTH TABLE Pin CKSEL S OUT : P = 8:1 : S OUT = 1:1 S OUT HIGH Function S OUT : P = 8:1 : S OUT = 1:2 S OUT LOW CKEN Synchronously isables Normal Parallel to Serial Conversion Synchronously Enables Normal Parallel to Serial Conversion Asynchronously Resets Internal Flip Flops* Synchronous Enable *The rising edge of will asynchronously reset the internal circuitry. The falling edge of the followed by the falling edge of initiates the conversion process synchronously on the next rising edge of. Table 3. INPUT VOLTAGE LEVEL SELECTION TABLE Input Function ECL Mode CMOS Mode TTL Mode* Connect To V CF Pin V EF Pin No Connect 1.5 V 1 mv *For TTL Mode, if no external voltage can be provided, the reference voltage can be provided by connecting the appropriate resistor between V CF and V EE pins. Table 4. ATA INPUT OPERATING VOLTAGE TABLE Power Supply (,V EE ) ata Inputs ( [:7]) CMOS TTL PECL NECL PECL N/A NECL N/A N/A N/A Power Supply Resistor Value 1% (Tolerance) 3.3 V 1.5 k 5. V 5 3

4 MC1EP446, MC1EP446 MUX 2:1 4 2 MUX 2:1 C R MUX 2:1 6 MUX 2:1 S OUT S OUT 1 MUX 2:1 5 MUX 2:1 3 MUX 2: CKEN CKEN 2 MUX 2:1 Control Logic P P C R CKSEL V EE V BB V CF V EF Figure 3. Logic iagram 4

5 MC1EP446, MC1EP446 Table 5. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ES Protection Human Body Model Machine Model Charged evice Model Value 75 k 37.5 k > 2 kv > 1 V > 2 kv Moisture Sensitivity, Indefinite Time Out of rypack (Note 1) Pb Pkg Pb Free Pkg LFP 32 FN 32 Level 2 Level 2 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 in Transistor Count Meets or exceeds JEEC Spec EIA/JES78 IC Latchup Test 1. For additional information, see Application Note AN83/. 962 evices Table 6. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit PECL Mode Power Supply V EE = V 6 V V EE NECL Mode Power Supply = V 6 V V I PECL Mode Input Voltage NECL Mode Input Voltage V EE = V = V I out Output Current Continuous Surge V I 6 V I V EE V ma I BB V BB Sink/Source ±.5 ma T A Operating Temperature Range 4 to +85 C T stg Storage Temperature Range 65 to +15 C JA Thermal Resistance (Junction to Ambient) lfpm 5 lfpm LFP 32 LFP 32 JC Thermal Resistance (Junction to Case) Standard Board LFP to 17 C/W JA Thermal Resistance (Junction to Ambient) lfpm 5 lfpm FN 32 FN 32 JC Thermal Resistance (Junction to Case) 2S2P FN C/W T sol Wave Solder Pb Free <2 to 3 26 C 265 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected C/W C/W 5

6 MC1EP446, MC1EP446 Table 7. 1EP C CHARACTERISTICS, PECL = 3.3 V, V EE = V (Note 2) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 3) mv V OL Output LOW Voltage (Note 3) mv V IH V IL Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) CMOS PECL TTL CMOS PECL TTL V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 4) V I IH Input HIGH Current A I IL Input LOW Current (All Except, ), NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with. V EE can vary +.3 V to 2.2 V. 3. All loading with 5 to 2. V. 4. V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit mv mv A 6

7 MC1EP446, MC1EP446 Table 8. 1EP C CHARACTERISTICS, PECL = 5. V, V EE = V (Note 5) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 6) mv V OL Output LOW Voltage (Note 6) mv V IH V IL Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) CMOS PECL TTL CMOS PECL TTL V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 7) V I IH Input HIGH Current A I IL Input LOW Current (All Except, ), NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with. V EE can vary +2. V to.5 V. 6. All loading with 5 to 2. V. 7. V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit mv mv A 7

8 MC1EP446, MC1EP446 Table 9. 1EP C CHARACTERISTICS, NECL = V, V EE = 5.5 V to 3. V (Note 8) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 9) mv V OL Output LOW Voltage (Note 9) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 1) V EE +2.. V EE +2.. V EE +2.. V I IH Input HIGH Current A Unit I IL Input LOW Current (All Except, ), A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with. 9. All loading with 5 to 2. V. 1.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. Table 1. 1EP C CHARACTERISTICS, PECL = 3.3 V, V EE = V (Note 11) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 12) mv V OL Output LOW Voltage (Note 12) mv V IH V IL Input HIGH Voltage (Single Ended) CMOS PECL TTL Input LOW Voltage (Single Ended) CMOS PECL TTL V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 13) V I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with. V EE can vary +.3 V to 2.2 V. 12.All loading with 5 to 2. V. 13.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit mv mv 8

9 MC1EP446, MC1EP446 Table 11. 1EP C CHARACTERISTICS, PECL = 5. V, V EE = V (Note 14) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 15) mv V OL Output LOW Voltage (Note 15) mv V IH V IL Input HIGH Voltage (Single Ended) CMOS PECL TTL Input LOW Voltage (Single Ended) CMOS PECL TTL V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 16) V I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14.Input and output parameters vary 1:1 with. V EE can vary +2. V to.5 V. 15.All loading with 5 to 2. V. 16.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit mv mv Table 12. 1EP C CHARACTERISTICS, NECL = V, V EE = 5.5 V to 3. V (Note 17) Symbol Characteristic 4 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max I EE Power Supply Current ma V OH Output HIGH Voltage (Note 18) mv V OL Output LOW Voltage (Note 18) mv V IH Input HIGH Voltage (Single Ended) mv V IL Input LOW Voltage (Single Ended) mv V BB Output Voltage Reference mv V IHCMR Input HIGH Voltage Common Mode Range (ifferential Configuration) (Note 19) V EE +2.. V EE +2.. V EE +2.. V I IH Input HIGH Current A I IL Input LOW Current A NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 17.Input and output parameters vary 1:1 with. 18.All loading with 5 to 2. V. 19.V IHCMR min varies 1:1 with V EE, V IHCMR max varies 1:1 with. The V IHCMR range is referenced to the most positive side of the differential input signal. Unit 9

10 MC1EP446, MC1EP446 Table 13. AC CHARACTERISTICS = V; V EE = 3. V to 5.5 V or = 3. V to 5.5 V; V EE = V (Note 2) 4 C 25 C 85 C Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit f max Maximum Frequency (Figure 15) CKSEL High CKSEL Low GHz t PLH, t PHL Propagation elay to Output ifferential CKSEL = TO S OUT, TO P ps CKSEL = 1 TO S OUT, TO P ps t S Setup Time to + (Figure 4) to (Figure 5) CKEN+ to (Figure 6) t h Hold Time to + (Figure 4) to to CKEN (Figure 6) t pw Minimum Pulse Width (Note 22) ata ( 7) CKEN t JITTER Random Clock Jitter (RMS) f max Typ < 1.2 < 1.2 < 1 ps 45 ps ps ps V PP Input ifferential Voltage Swing (Note 21) mv t r Output Rise/Fall Times S OUT t f (2% 8%) ps NOTE: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 5 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2.Measured using a 75 mv source, 5% duty cycle clock source. All loading with 5 to 2. V. 21.V PP (min) is the minimum input swing for which AC parameters are guaranteed. 22.The minimum pulse width is valid only if the setup and hold times are respected. 1

11 MC1EP446, MC1EP446 ata Setup Time t s ata Valid t h + Figure 4. Setup and Hold Time for ata t s CKEN t S t h Figure 5. Setup Time for Figure 6. Setup and Hold Time for CKEN 11

12 MC1EP446, MC1EP446 APPLICATION INFORMATION The MC1/1EP446 is an integrated 8:1 parallel to serial converter. An attribute for EP446 is that the parallel inputs 7 (Pins 17 24) can be configured to accept either CMOS, ECL, or TTL level signals by a combination of interconnects between V EF (Pin 27) and V CF (Pin 26) pins. For CMOS input levels, leave V EF and V CF open. For ECL operation, short V CF and V EF (Pins 26 and 27). For TTL operation, connect a 1.5 V supply reference to V CF and leave the V EF pin open. The 1.5 V reference voltage to V CF pin can be accomplished by placing a 1.5 k or 5 between V CF and V EE for 3.3 V or 5. V power supplies, respectively. Note: all pins requiring ECL voltage inputs must have a 5 terminating resistor to V TT (V TT = 2. V). The CKSEL input (Pin 2) is provided to enable the user to select the serial data rate output between internal clock data rate or twice the internal clock data rate. For CKSEL LOW operation, the time from when the parallel data is latched to when the data is seen on the S OUT is on the falling edge of the 7 th clock cycle plus internal propagation delay (Figure 7). Note the P switches on the falling edge of. Number of Clock Cycles from ata Latch to SOUT SOUT ata Latched ata Latched ata Latched ata Latched CKSEL P Figure 7. Timing iagram 1:8 Parallel to Serial Conversion with CKSEL LOW 12

13 MC1EP446, MC1EP446 Similarly, for CKSEL HIGH operation, the time from when the parallel data is latched to when the data is seen on the S OUT is on the rising edge of the 14 th clock cycle plus internal propagation delay (Figure 8). Furthermore, the P switches on the rising edge of. Number of Clock Cycles from ata Latch to SOUT ata Latched ata Latched ata Latched SOUT CKSEL P Figure 8. Timing iagram 1:8 Parallel to Serial Conversion with CKSEL HIGH 13

14 MC1EP446, MC1EP446 The device also features a differential input (Pins 29 and 3), which asynchronously reset all internal flip flops and clock circuitry on the rising edge of. The release of is a synchronous process, which ensures that no runt serial data bits are generated. The falling edge of the followed by a falling edge of initiates the start of the conversion process on the next rising edge of (Figures 9 and 1). As shown in the figures below, the device will start to latch the parallel input data after the a falling edge of, followed by the falling edge, on the next rising of edge of for CKSEL LOW (Asynchronous RESET) (Synchronous ENABLE) Number of Clock Cycles from ata Latch to SOUT SOUT ata Latched ata Latched ata Latched ata Latched CKSEL P Figure 9. Timing iagram 1:8 Parallel to Serial Conversion with CKSEL LOW and Figure 1. Synchronous Release of for CKSEL LOW 14

15 MC1EP446, MC1EP446 For CKSEL HIGH, as shown in the timing diagrams below, the device will start to latch the parallel input data after the falling edge of, followed by the falling edge, on the second rising edge of (Figures 11 and 12). (Synchronous ENABLE) Number of Clock Cycles from ata Latch to SOUT (Asynchronous RESET) ata Latched ata Latched 1 ata Latched SOUT CKSEL P Figure 11. Timing iagram 1:8 Parallel to Serial Conversion with CKSEL HIGH and Figure 12. Synchronous Release of for CKSEL HIGH 15

16 MC1EP446, MC1EP446 The differential synchronous CKEN inputs (Pins 6 and 7), disable the internal clock circuitry. The synchronous CKEN will suspend all of the device activities and prevent runt pulses from being generated. The rising edge of CKEN followed by the falling edge of will suspend all activities. The falling edge of CKEN followed by the falling edge of will resume all activities (Figure 13). Internal Clock isabled Internal Clock Enabled CKEN SOUT P CKSEL Figure 13. Timing iagram with CKEN with CKSEL HIGH The differential P output (Pins 14 and 15) is a word framer and can help the user synchronize the serial data output, S OUT (Pins 11 and 12), in their applications. Furthermore, P can be used as a trigger for input parallel data (Figure 14). An internally generated voltage supply, the V BB pin, is available to this device only. For single ended input conditions, the unused differential input is connected to V BB as a switching reference voltage. V BB may also rebias AC coupled inputs. When used, decouple V BB and via a.1 F capacitor and limit current sourcing or sinking to.5 ma. When not used, V BB should be left open. Also, both outputs of the differential pair must be terminated (5 to V TT ) even if only one output is used. RESET Pattern Generator ata Format Logic (FPGA, ASIC) EP446 TRIGGER PARALLEL ATA OUTPUT PARALLEL ATA INPUT P S OUT SERIAL ATA Figure 14. P as Trigger Application 16

17 MC1EP446, MC1EP446 V OUTpp (mv) CKSEL Low CKSEL High INPUT CLOCK FREUENCY (MHz) Figure 15. Typical V OUTPP versus Input Clock Frequency, 25C Figure 16. SOUT System Jitter Measurement (Condition: 3.4 GHz input frequency, CKSEL HIGH, BEOFE32 bit pattern on SOUT 17

18 MC1EP446, MC1EP446 river evice Z o = 5 Z o = 5 Receiver evice 5 5 V TT V TT = 2. V Figure 17. Typical Termination for Output river and evice Evaluation (See Application Note AN82/ Termination of ECL Logic evices.) ORERING INFORMATION MC1EP446FAG MC1EP446FAR2G MC1EP446MNG MC1EP446MNG MC1EP446FAG MC1EP446FAR2G MC1EP446MNR4G MC1EP446MNR4G evice Package Shipping LFP 32 (Pb Free) FN 32 (Pb Free) LFP 32 (Pb Free) FN 32 (Pb Free) 25 Units / Tray 2 / Tape & Reel 74 Units / Rail 74 Units / Rail 25 Units / Tray 2 / Tape & Reel 1 / Tape & Reel 1 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BR811/. Resource Reference of Application Notes AN145/ ECL Clock istribution Techniques AN146/ esigning with PECL (ECL at +5. V) AN153/ ECLinPS I/O SPiCE Modeling Kit AN154/ Metastability and the ECLinPS Family AN1568/ Interfacing Between LVS and ECL AN1672/ The ECL Translator Guide AN81/ Odd Number Counters esign AN82/ Marking and ate Codes AN82/ Termination of ECL Logic evices AN866/ Interfacing with ECLinPS AN89/ AC Characteristics of ECL evices 18

19 MC1EP446, MC1EP446 PACKAGE IMENSIONS A1 32 A 25 4X 32 LEA LFP CASE 873A 2 ISSUE C.2 (.8) AB T-U Z T, U, Z T 1 U P AE B 9 SEATING PLANE B1 AB AC 8 9 S1 G S ETAIL Y Z.1 (.4) AC 17 4X V1 V.2 (.8) AC T-U Z ETAIL A C E 8X M ETAIL Y AE R BASE METAL N ÉÉ ÉÉ F ÉÉ J.2 (.8) M AC T-U Z SECTION AE AE H W ETAIL A X K GAUGE PLANE.25 (.1) NOTES: 1. IMENSIONING AN TOLERANCING PER ANSI Y14.5M, CONTROLLING IMENSION: MILLIMETER. 3. ATUM PLANE AB IS LOCATE AT BOTTOM OF LEA AN IS COINCIENT WITH THE LEA WHERE THE LEA EXITS THE PLASTIC BOY AT THE BOTTOM OF THE PARTING LINE. 4. ATUMS T, U, AN Z TO BE ETERMINE AT ATUM PLANE AB. 5. IMENSIONS S AN V TO BE ETERMINE AT SEATING PLANE AC. 6. IMENSIONS A AN B O NOT INCLUE MOL PROTRUSION. ALLOWABLE PROTRUSION IS.25 (.1) PER SIE. IMENSIONS A AN B O INCLUE MOL MISMATCH AN ARE ETERMINE AT ATUM PLANE AB. 7. IMENSION OES NOT INCLUE AMBAR PROTRUSION. AMBAR PROTRUSION SHALL NOT CAUSE THE IMENSION TO EXCEE.52 (.2). 8. MINIMUM SOLER PLATE THICKNESS SHALL BE.76 (.3). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM EPICTION. MILLIMETERS INCHES IM MIN MAX MIN MAX A 7. BSC.276 BSC A1 3.5 BSC.138 BSC B 7. BSC.276 BSC B1 3.5 BSC.138 BSC C E F G.8 BSC.31 BSC H J K M 12 REF 12 REF N P.4 BSC.16 BSC R S 9. BSC.354 BSC S1 4.5 BSC.177 BSC V 9. BSC.354 BSC V1 4.5 BSC.177 BSC W.2 REF.8 REF X 1. REF.39 REF 19

20 MC1EP446, MC1EP446 PACKAGE IMENSIONS FN32 5x5,.5P CASE 488AM ISSUE A PIN ONE LOCATION NOTE 4.15 C 32X L.15 C.1 C.8 C ETAIL A 8 É É 9 TOP VIEW ETAIL B SIE VIEW 2 17 K A B E A (A3) A1 E2 L1 SEATING C PLANE L ETAIL A ALTERNATE TERMINAL CONSTRUCTIONS EXPOSE Cu ÉÉÉ ÇÇÇ ÇÇÇ L MOL CMP ETAIL B ALTERNATE CONSTRUCTION NOTES: 1. IMENSIONS AN TOLERANCING PER ASME Y14.5M, CONTROLLING IMENSION: MILLIMETERS. 3. IMENSION b APPLIES TO PLATE TERMINAL AN IS MEASURE BETWEEN.15 AN.3MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSE PA AS WELL AS THE TERMINALS. MILLIMETERS IM MIN MAX A.8 1. A1.5 A3.2 REF b BSC E 5. BSC E e.5 BSC K.2 L.3.5 L1.15 RECOMMENE SOLERING FOOTPRINT* X e e/2 BOTTOM VIEW 32X b.1 M C A B.5 M C NOTE 3.5 PITCH X.3 IMENSION: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLERRM/. ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 5163, enver, Colorado 8217 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada [email protected] N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC1EP446/