NB2304A. 3.3 V Zero Delay Clock Buffer
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1 3.3 V Zero Delay Clock Buffer The NB304A is a versatile, 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. It is available in an pin package. The part has an on-chip PLL which locks to an input clock presented on the pin. The PLL feedback is required to be driven to pin, and can be obtained from one of the outputs. The input-to-output propagation delay is guaranteed to be less than 50 ps, and the output-to-output skew is guaranteed to be less than 00 ps. The NB304A has two Banks of two outputs each. Multiple NB304A devices can accept the same input clock and distribute it. In this case, the skew between the outputs of the two devices is guaranteed to be less than 500 ps. The NB304A is available in two different configurations (Refer to NB304A Configurations Table). The NB304AI is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. The NB304AIH is the high-drive version of the - and the rise and fall times on this device are much faster. The NB304AI allows the user to obtain, / X and X frequencies on each output Bank. The exact configuration and output frequencies depend on which output drives the feedback pin. Features Zero Input - Output Propagation Delay, Adjustable by Capacitive Load on Input Multiple Configurations - Refer to NB304A Configurations Table Input Frequency Range: 5 MHz to 33 MHz Multiple Low-Skew Outputs Output-Output Skew < 00 ps Device -Device Skew < 500 ps Two Banks of Four Outputs Less than 00 ps Cycle -to-cycle Jitter ( -, -H, -5H) Available in Space Saving, pin 50 mil SOIC Package 3.3 V Operation Advanced 0.35 m CMOS Technology Guaranteed Across and Industrial Temperature Ranges These are Pb-Free Devices XXXX A L Y W G SOIC - D SUFFIX CASE 75 MARKING DIAGRAM* = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb--Free Package *For additional marking information, refer to Application Note AND00/D. ORDERING INFORMATION Seedetailedorderingandshippinginformationinthepackage dimensions section on page 6 of this data sheet. XXXX ALYW G Semiconductor Components Industries, LLC, 00 October, 00 - Rev. 9 Publication Order Number: NB304A/D
2 PLL CLKA Extra Divider (--) CLKB Figure. Basic Block Diagram (see Figures and for device specific Block Diagrams) Table. CONFIGURATIONS Device Feedback From Bank A Frequency Bank B Frequency NB304AI Bank A or Bank B Reference Reference NB304AIH Bank A or Bank B Reference Reference NB304AI Bank A Reference Reference NB304AI Bank B X Reference Reference Table. PIN DESCRIPTION Pin # Pin Name Description CLKA 3 NB304A 7 6 CLKB (Note ) Input reference frequency, 5 V tolerant input. (Note ) Buffered clock output, Bank A. 3 CLKA (Note ) Buffered clock output, Bank A Ground. 5 (Note ) Buffered clock output, Bank B. Figure. Pin Configuration 6 CLKB (Note ) Buffered clock output, Bank B V supply. PLL feedback input.. Weak pulldown.. Weak pulldown on all outputs.
3 Table 3. MAXIMUM RATINGS Parameter Min Max Unit Supply Voltage to Ground Potential V DC Input Voltage (Except ) V DC Input Voltage () V Storage Temperature C Maximum Soldering Temperature (0 sec) 60 C Junction Temperature 50 C Static Discharge Voltage (per MIL--STD--3, Method 305) > 000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. OPERATING CONDITIONS Parameter Description Min Max Unit Supply Voltage V T A Operating Temperature (Ambient Temperature) Industrial C C L Load Capacitance, 5 MHz to 00 MHz 30 pf C L Load Capacitance, from 00 MHz to 33 MHz 5 pf C IN Input Capacitance (Note 3) 7 pf 3. Applies to both Clock and. Table 5. ELECTRICAL CHARACTERISTICS V CC = 3.0 V to 3.6 V, = 0 V, T A =--40 C to+5 C Parameter Description Test Conditions Min Max Unit V IL Input LOW Voltage 0. V V IH Input HIGH Voltage.0 V I IL Input LOW Current V IN =0V 50.0 ma I IH Input HIGH Current V IN = 00.0 ma V OL Output LOW Voltage I OL = ma (--, --) I OL =ma(--h) V OH Output HIGH Voltage I OH = -- ma (--, --) I OH =--ma(--h) I DD Supply Current Unloaded outputs 00 MHz Select inputs at or 0.4 V.4 V 45 ma Unloaded outputs, 66 MHz (--, --) 35 Unloaded outputs, 33 MHz (--, --) 0 3
4 Table 6. SWITCHING CHARACTERISTICS V CC = 3.0 V to 3.6 V, = 0 V, T A =--40 C to+5 C (All parameters are specified with loaded outputs) Parameter Description Test Conditions Min Typ Max Unit t Output Frequency (all devices) (--, --) MHz t Duty Cycle = (t /t ) * 00 (all devices) Measured at.4 V, F OUT MHz Measured at.4 V, F OUT 50 MHz % t 3 Output Rise Time (--, --) Measured between 0. V and.0 V.50 ns Measured between 0. V and.0 V.50 Output Rise Time (--H) Measured between 0. V and.0 V.50 t 4 Output Fall Time (--, --) Measured between.0 V and 0. V.50 ns Measured between.0 V and 0. V.50 Output Fall Time (--H) Measured between.0 V and 0. V.5 t 5 t 6 Output--to--Output Skew on same Bank (--, --) Output--to--Output Skew (--H) Output Bank A--to--Output Bank B skew (--) Output Bank A--to--Output Bank B skew (--) Delay, Rising Edge to Rising Edge All outputs equally loaded 00 ps All outputs equally loaded 00 All outputs equally loaded 00 All outputs equally loaded 400 Measured at / 0 50 ps t 7 Device--to--Device Skew Measured at / on the pins of the device t Output Slew Rate Measured between 0. V and.0 V using Test Circuit # ps V/ns t J Cycle--to--Cycle Jitter (--, --H) 0 ps 00 Measured at 33.3 MHz, loaded outputs, 00 Cycle--to--Cycle Jitter (--) 400 ps 30 t LOCK PLL Lock Time Stable power supply, valid clock presented on and pins.0 ms 4
5 Zero Delay and Skew Control For applications requiring zero input-output delay, all outputs must be equally loaded. INPUT TO CLKA/CLKB DELAY (ps) To close the feedback loop of the NB304A, the pin can be driven from any of the four available output pins. The output driving the pin will be driving a total load of 7 pf plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input output delay. This is shown in Figure 3. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use Figure 3 to calculate loading differences between the feedback output and remaining outputs. For zero output-output skew, be sure to load outputs equally LOAD DIFFERENCE: LOAD -- CLKA/CLKB LOAD (pf) Figure 3. Input to CLKA/CLKB Delay vs. Difference in Loading between Pin and CLKA/CLKB Pins SWITCHING WAVEFORMS t t.4 V.4 V.4 V.0 V 0. V.0 V 0. V 0V 3.3 V t 3 t 4 Figure 4. Duty Cycle Timing Figure 5. All Outputs Rise/Fall Time.4 V INPUT.4 V t 5 t 6 Figure 6. Output - Output Skew Figure 7. Input - Output Propagation Delay _Device _Device t 7 Figure. Device - Device Skew 5
6 TEST CIRCUITS S C LOAD S kω kω 0 pf Figure 9. Test Circuit # Figure 0. Test Circuit # For parameter t (output slew rate) on -H devices BLOCK DIAGRAMS CLKA CLKA PLL PLL CLKB CLKB Figure. NB304AI and NB304AIH Figure. NB304AI ORDERING INFORMATION Device Marking Operating Range Package Shipping Availability NB304AIDG 4I Industrial & NB304AIDRG 4I Industrial & NB304AIHDG 4IH Industrial & NB304AIHDRG 4IH Industrial & NB304AIDG 4I Industrial & NB304AIDRG 4I Industrial & 9 Units / Rail 500 Tape & Reel 9 Units / Rail 500 Tape & Reel 9 Units / Rail 500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD0/D. 6
7 PACKAGE DIMENSIONS - Y - B - X - A 5 4 S 0.5 (0.00) M Y M SOIC - NB CASE ISSUE AJ K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, 9.. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.7 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU ARE OBSOLETE. NEW STANDARD IS Z - H G D C 0.5 (0.00) M Z Y S X S SEATING PLANE 0.0 (0.004) N X45_ M SOLDERING FOOTPRINT* J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.7 BSC BSC H J K M 0 0 N S SCALE 6: mm inches *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 07 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NB304A/D
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