NCV8184. Micropower 70 ma Low Dropout Tracking Regulator/Line Driver
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1 Micropower 7 ma Low Dropout Tracking Regulator/Line Driver The NCV884 is a monolithic integrated low dropout tracking voltage regulator designed to provide an adjustable buffered output voltage that closely tracks (±3. mv) the reference input. The part can be used in automotive applications with remote sensors, or any situation where it is necessary to isolate the output of your regulator. The NCV884 also enables the user to bestow a quick upgrade to their module when added current is needed, and the existing regulator cannot provide. The versatility of this part also enables it to be used as a highside driver. Features 7 ma Source Capability Output Tracks within ±3. mv Low Input Voltage Tracking Performance (Works Down to V REF = 2. V) Low Dropout (.35 V 5 ma) Low Quiescent Current Thermal Shutdown Wide Operating Range Internally Fused Leads in SOIC8 Package NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ Qualified and PPAP Capable These Devices are PbFree and are RoHS Compliant Adj SOIC8 D SUFFIX CASE 75 DPAK 5LEAD DT SUFFIX CASE 75AA PIN CONNECTIONS AND MARKING DIAGRAMS NC SOIC8 EP PD SUFFIX CASE 75AC Adj 884 ALYW AYWW V REF /ENABLE NC NC V REF /ENABLE Adj V REF /ENABLE + BIAS Thermal Shutdown Current Limit & Saturation Sense 884G ALYWW Pin Tab, Adj 5. V REF /ENABLE 884 = Device Code A = Assembly Location L = Wafer Lot Y = Year W, WW = Work Week or G = PbFree Package Figure. Block Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 22 October, 22 Rev. 27 Publication Order Number: NCV884/D
2 MAXIMUM RATINGS Rating Value Unit Storage Temperature 65 to 5 C Supply Voltage Range (Continuous) 5 to 45 V Supply Voltage Operating Range 4. to 42 V Peak Transient Voltage ( = 4 V, Load Dump Transient = 3 V) 45 V Voltage Range (, Adj) 3. to 45 V Voltage Range (V REF /ENABLE).3 to 45 V Maximum Junction Temperature 5 C ESD Capability Human Body Model Machine Model Charge Device Model Lead Temperature Soldering: Reflow: (SMD styles only) (Note ) 24 peak 26 peak (PbFree) (Note 2) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. 6 second maximum above 83 C C / + C Allowable Conditions, applies to both Pb and PbFree devices. THERMAL CHARACTERISTICS See Package Thermal Data Section (Page 8) ELECTRICAL CHARACTERISTICS ( = 4 V; V REF /ENABLE > 2. V; 4 C < T J < +5 C; C OUT =. F; I OUT =. ma; Adj = ; C OUTESR =., unless otherwise specified.) Parameter Test Conditions Min Typ Max Unit REGULATOR OUTPUT V REF /ENABLE Tracking Error Dropout Voltage ( ) 5.7 V 26 V, A I OUT 6 ma 2. V V REF /ENABLE ( 6 mv) I OUT = A I OUT = 5. ma I OUT = 6 ma kv V V C mv Line Regulation 5.7 V 26 V, V REF /ENABLE = 5. V 3. mv Load Regulation A I OUT 6 ma, V REF /ENABLE = 5. V 3. mv Adj Input Bias Current V REF /ENABLE = 5. V.2 6. A Current Limit = 4 V, V REF = 5. V, = 9% of V REF (Note 3) ma Quiescent Current (I IN I OUT ) = 2 V, I OUT = 6 ma = 2 V, I OUT = A = 2 V, V REF /ENABLE = V Ripple Rejection f = 2 Hz, I OUT = 6 ma, 6. V 26 V 6 db Thermal Shutdown Guaranteed by Design C V REF /ENABLE Enable Voltage.8 2. V Input Bias Current V REF /ENABLE = 5. V.2 3. A 3. connected to Adj lead. PACKAGE PIN DESCRIPTION Package Lead Number SOIC8 EPAD SOIC8 DPAK, 5LEAD Lead Symbol Function 8 8 Battery supply input voltage. 2 Regulated output. 3, EPAD 2, 3, 6, 7 Tab, 3 Ground Adj Adjust lead, noninverting input V REF /ENABLE Reference voltage and ENABLE input. 2, 6, 7 NC No Connection. PCB traces allowed mv mv mv ma A A 2
3 TYPICAL PERFORMANCE CHARACTERISTICS.4.3 I OUT = 5 ma..8 TRACKING ERROR (mv) TRACKING ERROR (mv) C +25 C 4 C TEMPERATURE ( C) OUTPUT CURRENT (ma) Figure 2. Tracking Error vs. Temperature Figure 3. Tracking Error vs. Output Current ESR ( ) = 5. V Unstable Region C2 = F C2 =. F Stable Region OUTPUT CURRENT (ma) ESR ( ) Unstable Region Data is for. F only. Capacitor values.5 F and above do not exhibit instability with low ESR. Stable Region C2 =. F = 5. V OUTPUT CURRENT (ma) Figure 4. Output Stability with Capacitor Change Figure 5. Output Stability with. F at Low ESR QUIESCENT CURRENT (ma) C +25 C 4 C OUTPUT CURRENT (ma) Figure 6. Quiescent Current vs. Output Current QUIESCENT CURRENT (ma) I OUT = 2 ma I OUT = ma V REF / ENABLE = 5. V INPUT VOLTAGE (V) Figure 7. Quiescent Current vs. Input Voltage 3
4 TYPICAL PERFORMANCE CHARACTERISTICS.5 6 DROPOUT VOLTAGE (V) C 4 C +25 C OUTPUT VOLTAGE (V) C +25 C OUTPUT CURRENT (ma) 4 C V REF /ENABLE = 5. V INPUT VOLTAGE (V) Figure 8. Dropout Voltage vs. Output Current Figure 9. Output Voltage vs. Input Voltage 7.7 OUTPUT VOLTAGE (V) REFERENCE CURRENT ( A) REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) Figure. Output Voltage vs. Reference Voltage Figure. Reference Current vs. Reference Voltage THERMAL RESISTANCE, JUNCTION TO AMBIENT, R JA, ( C/W) COPPER AREA (in 2 ) Figure 2. SOIC8, JA as a Function of the Pad Copper Area (2. oz. Cu Thickness), Board Material =.625 G/R4 4
5 CIRCUIT DESCRIPTION ENABLE Function By pulling the V REF /ENABLE lead below.8 V, (see Figure 6 or Figure 7), the IC is disabled and enters a sleep state where the device draws less than 2 A from supply. When the V REF /ENABLE lead is greater than 2. V, tracks the V REF /ENABLE lead normally. Output Voltage The output is capable of supplying 7 ma to the load while configured as a similar (Figure 3), lower (Figure 5), or higher (Figure 4) voltage as the reference lead. The Adj lead acts as the inverting terminal of the op amp and the V REF lead as the noninverting. The device can also be configured as a highside driver as displayed in Figure 8., 7 ma Loads C2** F NCV884 Adj V REF / ENABLE VOUT VREF C3*** nf C*. F 5. V Figure 3. Tracking Regulator at the Same Voltage B+, 7 ma Loads C2** F R F R A NCV884 Adj V REF / ENABLE C3*** nf VOUT VREF( R E RA ) C*. F V REF Figure 4. Tracking Regulator at Higher Voltages B+, 7 ma Loads C2** F NCV884 Adj V REF / ENABLE C3*** nf C*. F R R2 B+ V REF C2** F from MCU, 7 ma NCV884 Adj V REF / ENABLE C3*** nf C*. F R B+ V REF VOUT VREF( R2 R R2 ) Figure 5. Tracking Regulator at Lower Voltages Figure 6. Tracking Regulator with ENABLE Circuit 6. V4 V nf 7 ma To Load F (e.g. sensor) NCV85 NCV884 Adj V REF / ENABLE V REF (5. V) C*. F I/O C3*** nf C 7 ma NCV884 Adj V REF / ENABLE VOUT B VSAT C3*** nf B+ MCU Figure 7. Alternative ENABLE Circuit Figure 8. HighSide Driver * C is required if the regulator is far from the power source filter. In case of power supply generates voltage ripple (e.g. DC-DC converter) a passive low pass filter with C value at least F is required to suppress the ripple. The filter should be designed according to particular operating conditions and verified in the application. ** C2 is required for stability. *** C3 is recommended for EMC susceptibility 5
6 APPLICATION NOTES Short to Battery The NCV884 will survive a short to battery when hooked up the conventional way as shown in Figure 9. No damage to the part will occur. The part also endures a short to battery when powered by an isolated supply at a lower voltage as in Figure 2. In this case the NCV884 supply input voltage is set at 7. V when a short to battery (4 V typical) occurs on which normally runs at 5. V. The current into the device (ammeter in Figure 2) will draw additional current as displayed in Figure 2. Short to battery Loads C2** F 7 ma NCV884 B+ C*. F + Automotive Battery typically 4 V Adj V REF / ENABLE = V REF C3*** nf 5. V + 5. V Figure 9. Short to battery A Automotive Battery typically 4 V Loads C2** F 7 ma * C is required if the regulator is far from the power source filter. ** C2 is required for stability. *** C3 is recommended for EMC susceptibility. Adj Figure 2. NCV884 V REF / ENABLE = V REF B+ C*. F C3*** nf 7 V + 5. V + 5. V CURRENT (ma) VOLTAGE (V) Figure 2. Short to Battery Switched Application The NCV884 has been designed for use in systems where the reference voltage on the V REF /ENABLE pin is continuously on. Typically, the current into the V REF /ENABLE pin will be less than. A when the voltage on the pin (usually the ignition line) has been switched out ( can be at high impedance or at ground.) Reference Figure 22. Ignition Switch C2 F Adj NCV884 V REF / ENABLE <. A C. F V REF 5. V V BAT Figure 22. 6
7 External Capacitors The output capacitor for the NCV884 is required for stability. Without it, the regulator output will oscillate. Actual size and type may vary depending upon the application load and temperature range. Capacitor effective series resistance (ESR) is also a factor in the IC stability. Worstcase is determined at the minimum ambient temperature and maximum load expected. The output capacitor can be increased in size to any desired value above the minimum. One possible purpose of this would be to maintain the output voltage during brief conditions of negative input transients that might be characteristic of a particular system. The capacitor must also be rated at all ambient temperatures expected in the system. To maintain regulator stability down to 4 C, a capacitor rated at that temperature must be used. More information on capacitor selection for SMART REGULATOR s is available in the SMART REGULATOR application note, Compensation for Linear Regulators, document number SR3AN/D, available through our website at Calculating Power Dissipation in a Single Output Linear Regulator The maximum power dissipation for a single output regulator (Figure 23) is: PD(max) {VIN(max) VOUT(min)} IOUT(max) (eq. ) VIN(max)IQ where: (max) is the maximum input voltage, (min) is the minimum output voltage, I OUT(max) is the maximum output current, for the application,and I Q is the quiescent current the regulator consumes at I OUT(max). Once the value of PD(max) is known, the maximum permissible value of R JA can be calculated: R JA 5 C T A PD (eq. 2) The value of R JA can then be compared with those in the Package Thermal Data Section of the data sheet. Those packages with R JA s less than the calculated value in equation 2 will keep the die temperature below 5 C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heat sink will be required. I IN SMART REGULATOR Control Features I OUT Figure 23. Single Output Regulator with Key Performance Parameters Labeled Heatsinks I Q A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R JA: R JA R JC R CS R SA (eq. 3) where: R JC = the junctiontocase thermal resistance, R CS = the casetoheatsink thermal resistance, and R SA = the heatsinktoambient thermal resistance. R JC appears in the package section of the data sheet. Like R JA, it is a function of package type. R CS and R SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heatsink manufacturers. 7
8 PACKAGE THERMAL DATA Parameter SOIC8 Package Conditions Typical Value mm 2 Spreader Board 645 mm 2 Spreader Board oz 2 oz oz 2 oz JunctiontoPin 6 ( JL6, JL6 ) C/W JunctiontoAmbient (R JA, JA ) 5 35 C/W Units Package construction Without mold compound Figure 24. PCB Layout and Package Construction for Simulation 8
9 Table. SOIC8 THERMAL RC NETWORK MODELS* Copper Area ( oz thick) mm mm 2 mm mm 2 Cauer Network Foster Network mm mm 2 Units Tau Tau Units C_C Junction Gnd.5.5 Ws/C.E-6.E-6 sec C_C2 node Gnd Ws/C.E-5.E-5 sec C_C3 node2 Gnd.7.7 Ws/C.E-4.E-4 sec C_C4 node3 Gnd Ws/C.76E-4.76E-4 sec C_C5 node4 Gnd Ws/C.. sec C_C6 node5 Gnd Ws/C.8.8 sec C_C7 node6 Gnd Ws/C.5.5 sec C_C8 node7 Gnd Ws/C sec C_C9 node8 Gnd Ws/C sec C_C node9 Gnd Ws/C sec mm mm 2 R s R s R_R Junction node C/W C/W R_R2 node node C/W C/W R_R3 node2 node C/W C/W R_R4 node3 node C/W C/W R_R5 node4 node C/W C/W R_R6 node5 node C/W C/W R_R7 node6 node C/W C/W R_R8 node7 node C/W C/W R_R9 node8 node C/W C/W R_R node9 gnd C/W C/W *Bold face items in the tables above represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) n Ri e t tau i i 9
10 JA ( C/W) oz Cu 2. oz Cu COPPER HEAT SPREADER AREA (mm 2 ) Figure 25. SOIC8, JA as a Function of the Pad Copper Area, Board Material FR4 5% Duty Cycle R(t) ( C/W) 2% % 5% 2% Notes: P DM. % Single Pulse (. in pad PCB) Die Size = 2.8 x.55 x.4 5.% Active Area Duty Cycle, D = PULSE TIME (sec) Figure 26. SOIC8 Thermal Duty Cycle Curves on. in Spreader Test Board,. oz Cu t t 2 t t 2 Cu Area mm 2 R(t) ( C/W) Cu Area 645 mm PULSE TIME (sec) Figure 27. SOIC8 Single Pulse Heating Curve
11 PACKAGE THERMAL DATA Parameter SOIC8 EP Package Conditions Typical Value mm 2 Spreader Board 645 mm 2 Spreader Board oz 2 oz oz 2 oz JunctiontoBoard ( JB, JB ) C/W JunctiontoPin 6 (tab) ( JL6, JL6 ) C/W JunctiontoAmbient (R JA, JA ) C/W Units Package construction Without mold compound Figure 28. PCB Layout and Package Construction for Simulation
12 Table 2. SOIC8 EP THERMAL RC NETWORK MODELS* Drain Copper Area ( oz thick) mm mm 2 mm mm 2 (SPICE Deck Format) Cauer Network Foster Network mm mm 2 Units Tau Tau Units C_C Junction Gnd.5.5 Ws/C.E-6.E-6 sec C_C2 node Gnd Ws/C.E-5.E-5 sec C_C3 node2 Gnd.7.72 Ws/C.E-4.E-4 sec C_C4 node3 Gnd Ws/C.76E-4.76E-4 sec C_C5 node4 Gnd Ws/C.. sec C_C6 node5 Gnd Ws/C.8.8 sec C_C7 node6 Gnd Ws/C.5.5 sec C_C8 node7 Gnd Ws/C sec C_C9 node8 Gnd Ws/C sec C_C node9 Gnd Ws/C sec mm mm 2 R s R s R_R Junction node C/W C/W R_R2 node node C/W C/W R_R3 node2 node C/W C/W R_R4 node3 node C/W C/W R_R5 node4 node C/W C/W R_R6 node5 node C/W C/W R_R7 node6 node C/W C/W R_R8 node7 node C/W C/W R_R9 node8 node C/W C/W R_R node9 gnd C/W C/W *Bold face items in the tables above represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) n Ri e t tau i i 2
13 JA ( C/W) T J = 25 C 2. oz Cu 9 2. oz Cu COPPER HEAT SPREADER AREA (mm 2 ) Figure 29. SOIC 8 Exposed Pad, θ JA as a Function of the Pad Copper Area, Board Material FR4 5% Duty Cycle R(t) ( C/W) 2% % 5% 2% % Notes: P DM t t 2 Single Pulse t (. in pad PCB) Die Size = 2.8 x.55 x.4 5.% Active Area Duty Cycle, D = t PULSE TIME (sec) Figure 3. SOIC 8 Exposed Pad Thermal Duty Cycle Curves on. in Spreader Test Board,. oz Cu R(t) ( C/W) Cu Area mm 2 Cu Area 645 mm PULSE TIME (sec) Figure 3. SOIC 8 Exposed Pad Single Pulse Heating Curve 3
14 PACKAGE THERMAL DATA Parameter DPAK 5LEAD Package Conditions Typical Value mm 2 Spreader Board 645 mm 2 Spreader Board oz 2 oz oz 2 oz JunctiontoBoard-top ( JB, JB ) C/W JunctiontoPin 3 (tab) ( JL3, JL3 ) C/W JunctiontoAmbient (R JA, JA ) C/W Units Package construction Without mold compound Figure 32. PCB Layout and Package Construction for Simulation 4
15 Table 3. DPAK 5LEAD THERMAL RC NETWORK MODELS* Drain Copper Area ( oz thick) mm mm 2 mm mm 2 (SPICE Deck Format) Cauer Network Foster Network mm mm 2 Units Tau Tau Units C_C Junction Gnd.6.6 Ws/C.E-6.E-6 sec C_C2 node Gnd.6.6 Ws/C.E-5.E-5 sec C_C3 node2 Gnd Ws/C.E-4.E-4 sec C_C4 node3 Gnd Ws/C.76E-4.76E-4 sec C_C5 node4 Gnd Ws/C.. sec C_C6 node5 Gnd Ws/C.3.3 sec C_C7 node6 Gnd Ws/C sec C_C8 node7 Gnd Ws/C sec C_C9 node8 Gnd Ws/C sec C_C node9 Gnd Ws/C sec mm mm 2 R s R s R_R Junction node C/W C/W R_R2 node node C/W C/W R_R3 node2 node C/W C/W R_R4 node3 node C/W C/W R_R5 node4 node C/W C/W R_R6 node5 node C/W C/W R_R7 node6 node C/W C/W R_R8 node7 node C/W C/W R_R9 node8 node C/W C/W R_R node9 gnd C/W C/W *Bold face items in the tables above represent the package without the external thermal system. The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical tools (for instance, in a spreadsheet program), according to the following formula: R(t) n Ri e t tau i i 5
16 JA ( C/W) T J = 25 C 75. oz Cu oz Cu COPPER HEAT SPREADER AREA (mm 2 ) Figure 33. DPAK 5Lead, θ JA as a Function of the Pad Copper Area, Board Material FR4 R(t) ( C/W). 5% Duty Cycle 2% % 5% 2% % Single Pulse (. in pad PCB) Die Size = 2.8 x.55 x.4 5.% Active Area Notes: PULSE TIME (sec) P DM Figure 34. DPAK 5Lead Thermal Duty Cycle Curves on. in Spreader Test Board,. oz Cu t t 2 Duty Cycle, D = t t 2 Cu Area mm 2 Cu Area 645 mm 2 R(t) ( C/W) PULSE TIME (sec) Figure 35. DPAK 5Lead Single Pulse Heating Curve 6
17 Junction R R 2 R 3 R n C C 2 C 3 C n Time constants are not simple RC products. Amplitudes of mathematical solution are not the resistance values. Figure 36. Grounded Capacitor Thermal Network ( Cauer Ladder) Ambient (thermal ground) Junction R R 2 R 3 R n C C 2 C 3 C n Each rung is exactly characterized by its RCproduct time constant; Amplitudes are the resistances Figure 37. NonGrounded Capacitor Thermal Ladder ( Foster Ladder) Ambient (thermal ground) ORDERING INFORMATION NCV884DG Device Order Number Package Type Shipping SOIC8 (PbFree) 98 Units / Tube NCV884DR2G NCV884DTRKG NCV884PDG SOIC8 (PbFree) DPAK (PbFree) SOIC8 epad (PbFree) 25 / Tape & Reel 25 / Tape & Reel 98 Units / Tube NCV884PDR2G SOIC8 epad (PbFree) 25 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8/D. 7
18 PACKAGE DIMENSIONS X B Y 8 A 5 4 S.25 (.) M Y M SOIC8 NB CASE 757 ISSUE AK K NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION.5 (.6) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.27 (.5) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION THRU 756 ARE OBSOLETE. NEW STANDARD IS 757. Z H G D C.25 (.) M Z Y S X S SEATING PLANE. (.4) N X 45 M J MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D G.27 BSC.5 BSC H J K M 8 8 N S SOLDERING FOOTPRINT* SCALE 6: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 8
19 PACKAGE DIMENSIONS 2 X 8 X. SEATING PLANE C PIN ONE LOCATION. C E C D. A 8 D ÉÉ ÉÉ C 5 4 e B TOP VIEW SIDE VIEW 2 X A2 D E. C A-B EXPOSED PAD.2 2 X C 8 X b.25 C A-B D A A GAUGE PLANE.25 H SOIC8 EP CASE 75AC ISSUE B F BOTTOM VIEW L (L) DETAIL A G DETAIL A h A A END VIEW b c ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ (b) c SECTION AA NOTES:. DIMENSIONS AND TOLERANCING PER ASME Y4.5M, DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE.8 MM TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. MILLIMETERS DIM MIN MAX A A.. A b.3.5 b c.7.25 c.7.23 D 4.9 BSC E 6. BSC E 3.9 BSC e.27 BSC L.4.27 L.4 REF F G h SOLDERING FOOTPRINT* Exposed Pad SCALE 6: mm inches *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 9
20 PACKAGE DIMENSIONS DPAK 5, CENTER LEAD CROP CASE 75AA ISSUE A B C T SEATING PLANE NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. V S F R G L A K D 5 PL J H.3 (.5) M T E U R Z INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E F G.8 BSC 4.56 BSC H J K L.45 BSC.4 BSC R R S U.2.5 V Z SOLDERING FOOTPRINT* SCALE 4: mm inches.8.3 *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 827 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NCV884/D
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