DG401, DG403. Monolithic CMOS Analog Switches. Features. Applications. Pinouts. Ordering Information FN Data Sheet November 20, 2006

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1 DG4, DG43 Data Sheet November 2, 26 FN3284. Monolithic MOS Analog Switches The DG4 and DG43 monolithic MOS analog switches have TTL and MOS compatible digital inputs. These switches feature low analog ON resistance (<45Ω) and fast switch time (t ON <5ns). Low charge injection simplifies sample and hold applications. The improvements in the DG4, DG43 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older MOS technologies. The 44V maximum voltage range permits controlling 3V P-P signals. Power supplies may be single-ended from +5V to +34V, or split from ±5V to ±7V. The analog switches are bilateral, equally matched for A or bidirectional signals. The ON resistance variation with analog signals is quite low over a ±5V analog input range. The three different devices provide the equivalent of two SPST (DG4) or two SPDT (DG43) relay switch contacts with MOS or TTL level activation. The pinout is similar, permitting a standard layout to be used, choosing the switch function as needed. Pinouts D N N N N N N D 2 DG4 (6 LD SOI, TSSOP) TOP VIEW S 5 IN IN 2 9 S 2 Features ON Resistance (Max) Ω Low Power onsumption (P D ) <35μW Fast Switching Action - t ON (Max) ns - t OFF (Max) ns Low harge Injection DG4 Dual SPST; Same Pinout as HI-54 DG43 Dual SPDT; DG9, IH543, IH55, HI-55 TTL, MOS ompatible Single or Split Supply Operation Pb-Free Plus Anneal Available (RoHS ompliant) Applications Audio Switching Battery Operated Systems Data Acquisition Hi-Rel Systems Sample and Hold ircuits ommunication Systems Automatic Test Equipment Ordering Information PART PART TEMP. PKG. NUMBER* MARKING RANGE ( ) PAKAGE DWG. # DG4DY* DG4DY -4 to Ld SOI M6.5 DG4DYZ* (Note) DG4DVZ* (Note) DG4DYZ -4 to Ld SOI (Pb-free) DG4 DVZ -4 to Ld TSSOP (Pb-free) M6.5 M6.73 DG43DY* DG43DY -4 to Ld SOI M6.5 DG43 (6 LD SOI, TSSOP) TOP VIEW DG43DYZ* (Note) DG43DVZ* (Note) DG43DYZ -4 to Ld SOI (Pb-free) DG43 DVZ -4 to Ld TSSOP (Pb-free) M6.5 M6.73 D N D 3 S 3 S 4 D 4 N S IN IN 2 *Add -T suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IP/JEDE J STD-2. D S 2 NOTE: (N) No onnection. AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. opyright Intersil Americas Inc. 999, 22-24, 26. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 TRUTH TABLE DG4 DG43 LOGI SWITH SWITH, 2 SWITH 3, 4 OFF OFF ON ON ON OFF NOTE: Logic.8V. Logic 2.4V. Functional Diagrams DG4 DG S 6 D S 6 D S D 3 IN 5 IN 5 IN 2 IN 2 S D 2 S D 2 S D SWITHES SHOWN FOR LOGI INPUT Schematic Diagram SOURE V IN DRAIN 2 FN3284. November 2, 26

3 Absolute Maximum Ratings to V to V ( -.3V) to () +.3V Digital Inputs V S, V D (Note )..... () -2V to () + 2V or 3mA, Whichever Occurs First ontinuous urrent (Any Terminal) mA Peak urrent, S or D (Pulsed ms, % Duty ycle, Max).. ma Thermal Information Thermal Resistance (Typical, Note 2) θ JA ( /W) SOI Package TSSOP Package Maximum Junction Temperature (Plastic Package) Maximum Storage Temperature Range to +5 Maximum Lead Temperature (Soldering s) (SOI and TSSOP- Lead Tips Only) Operating onditions Temperature Range to +85 Voltage Range ±2V (Max) Input Low Voltage V (Max) Input High Voltage V (Min) Input Rise and Fall Time ns AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Signals on S X, D X, or IN X exceeding or will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test onditions: = +5V,, V IN = 2.4V,.8V (Note 3),, Unless Otherwise Specified PARAMETER DYNAMI HARATERISTIS TEST ONDITIONS TEMP ( ) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS Turn-ON Time, t ON R L = 3Ω, L = 35pF ns Turn-OFF Time, t OFF ns Break-Before-Make Time Delay (DG43), t D R L = 3Ω, L = 35pF ns harge Injection, Q (Figure 3) L = nf, V G = V, R G = Ω p OFF Isolation (Figure 4) R L = Ω, L = 5pF, f = MHz db rosstalk (hannel-to-hannel) (Figure 6) db Source OFF apacitance, S(OFF) f = MHz, V S = V D = V (Figure 7) pf Drain OFF apacitance, D(OFF) pf hannel ON apacitance, D(ON) + S(ON) pf DIGITAL INPUT HARATERISTIS Input urrent with V IN Low, I IL V IN Under Test =.8V, All Others = 2.4V Full -.5 μa Input urrent with V IN High, I IH V IN Under Test = 2.4V, All Others =.8V Full -.5 μa ANALOG SWITH HARATERISTIS Analog Signal Range, V ANALOG Full -5-5 V Drain-Source ON Resistance, r DS(ON) r DS(ON) Matching Between hannels, Δr DS(ON) = 3.5V, = -3.5V, I S = ma, V D = ±V = 6.5V, = -6.5V, I S = -ma, V D = 5,, -5V Ω Full Ω Ω Full Ω Source OFF Leakage urrent, I S(OFF) = 6.5V, = -6.5 V D = ±5.5V, V S = 5.5V na Full -5-5 na Drain OFF Leakage urrent, I D(OFF) na Full -5-5 na hannel ON Leakage urrent, I D(ON) +I S(ON) V± = ±6.5V, V D = V S = ±5.5V na Full - - na 3 FN3284. November 2, 26

4 Electrical Specifications Test onditions: = +5V,, V IN = 2.4V,.8V (Note 3),, Unless Otherwise Specified (ontinued) PARAMETER TEST ONDITIONS POWER SUPPLY HARATERISTIS Positive Supply urrent, I+ = 6.5V, = -6.5V, μa V IN = V or 5V Full μa Negative Supply urrent, I μa Full μa Logic Supply urrent, I L μa Full μa Ground urrent, I μa Full μa NOTES: 3. V IN = input voltage to perform proper function. 4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Test ircuits and Waveforms TEMP ( ) (NOTE 4) MIN (NOTE 5) TYP (NOTE 4) MAX UNITS LOGI INPUT 3V V 5% t r < 2ns t f < 2ns 5V +5V R L = 3Ω L = 35pF t OFF D V SWITH O S SWITH INPUT V INPUT S IN V O 9% 9% SWITH R LOGI L L OUTPUT V INPUT t ON % SWITH INPUT -V S (NOTE 7) V -5V Repeat test for IN 2 and S 2. NOTES: For load conditions, see Specifications. L includes fixture and stray 6. Logic input waveform is inverted for switches that have the capacitance. R opposite logic sense. L V O = V S R L + r DS( ON) 7. V S = V for t ON, V S = -V for t OFF. FIGURE A. MEASUREMENT POINTS FIGURE B. TEST IRUIT FIGURE. SWITHING TIMES 4 FN3284. November 2, 26

5 Test ircuits and Waveforms (ontinued) LOGI INPUT SWITH OUTPUT (V O ) SWITH OUTPUT (V O2 ) 3V V V S V V S2 V t D 9% t D 9% V S = V V S2 = V LOGI INPUT IN 5V +5V V -5V L includes fixture and stray capacitance. D D 2 R L = 3Ω L = 35pF R L2 V O2 R L L2 V O L FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME FIGURE 2B. TEST IRUIT 5V +5V SWITH OUTPUT V O ΔV O R G D V O IN X ON OFF ON V G L Q = ΔV O x L FIGURE 3A. MEASUREMENT POINTS FIGURE 3. HARGE INJETION V -5V FIGURE 3B. TEST IRUIT +5V +5V +5V +5V SIGNAL GENERATOR V S SIGNAL GENERATOR V S IN X V, 2.4V IN X V, 2.4V ANALYZER R L V D -5V ANALYZER R L V D -5V FIGURE 4. OFF ISOLATION TEST IRUIT FIGURE 5. INSERTION LOSS TEST IRUIT 5 FN3284. November 2, 26

6 Test ircuits and Waveforms (ontinued) SIGNAL GENERATOR V S +5V +5V V D 5Ω +5V +5V V S V, 2.4V IN IN 2 V, 2.4V IMPEDANE ANALYZER IN X V, 2.4V AS REQUIRED ANALYZER V D2 V S2 N V D R L -5V -5V FIGURE 6. ROSSTALK TEST IRUIT FIGURE 7. APAITANES TEST IRUIT Application Information Dual Slope Integrators The DG43 is well suited to configure a selectable slope integrator. One control signal selects the timing capacitor or 2. Another one selects e IN or discharges the capacitor in preparation for the next integration cycle. +5V +5V Peak Detector A 3 acting as a comparator provides the logic drive for operating SW. The output of A 2 is fed back to A 3 and compared to the analog input e IN. If e IN > e OUT the output of A 3 is high keeping SW closed. This allows to charge up to the analog input voltage. When e IN goes below e OUT, A 3 goes negative, turning SW off. The system will therefore store the most positive analog input experienced. e IN S S 3 D D 2 e OUT RESET IN SW 2 TTL INTEGRATE/ RESET S 2 S 4 D 3 D A SW e IN R A e OUT IN 2 2 SOPE SELET DG43-5V + - A 3 DG4 FIGURE 8. DUAL SLOPE INTEGRATOR FIGURE 9. POSITIVE PEAK DETETOR 6 FN3284. November 2, 26

7 Typical Performance urves 4 8 T A = 2 3 T A = 25 6 V T (V) 4 DG43 SW3, 4 V T (V) (V) SUPPLY VOLTAGE (±V) FIGURE. INPUT SWITHING THRESHOLD vs LOGI SUPPLY VOLTAGE FIGURE. INPUT SWITHING THRESHOLD vs POWER SUPPLY VOLTAGE T A = 25 r DS(ON) (Ω) r DS(ON) (Ω) 4 3 = 2V, = -2V, = 2V, = -2V = 6V, = -6V = V, = -V = 22V, = -22V 5-4 FIGURE 2. r DS(ON) vs V D AND TEMPERATURE V D (V) V D (V) FIGURE 3. r DS(ON) vs V D AND POWER SUPPLY VOLTAGE r DS(ON) (Ω) = 7.5V = V = 2V = V T A = 25 = 2V = 22V Q (p) L = nf L = pf L = nf V D (V) V S (V) FIGURE 4. r DS(ON) vs V D AND SINGLE SUPPLY VOLTAGE FIGURE 5. HARGE INJETION vs SOURE VOLTAGE 7 FN3284. November 2, 26

8 Typical Performance urves (ontinued) LOSS (db) ,, V S = V RMS SEE INSERTION LOSS TEST SETUP (FIGURE 5) R L = 6Ω R L = 75Ω R L = 5Ω I S(OFF) (na) V D = ±4V TYPIAL K K M M FREQUENY (Hz) FIGURE 6. INSERTION LOSS vs FREQUENY TEMPERATURE ( ) FIGURE 7. I S(OFF) vs TEMPERATURE.. V D = ±4V.. V D = ±4V I D(OFF) (na)... TYPIAL I D(ON) + I S(ON) (na)... TYPIAL TEMPERATURE ( ) TEMPERATURE ( ) FIGURE 8. I D(OFF) vs TEMPERATURE FIGURE 9. I D(ON) + I S(ON) vs TEMPERATURE I S, I D (pa) WHEN V ANALOG EXEEDS POWER SUPPLY, SWITH SUBSTRATE DIODES BEGIN TO ONDUT I D(OFF), I S(OFF) I D(ON) + I S(ON) I+, I -, I L, (μa).... I- I+ I L ,, T A = 25 I D(OFF), V S = V I S(OFF), V D = V V S, V D (V).. I L I TEMPERATURE ( ) FIGURE 2. LEAKAGE URRENTS vs ANALOG VOLTAGE FIGURE 2. SUPPLY URRENT vs TEMPERATURE 8 FN3284. November 2, 26

9 Typical Performance urves (ontinued) V S (V) NOT MEASURABLE DUE TO APAITIVE FEEDTHROUGH t ON, t OFF (ns) V S = -V V S = V - -2 SEE BBM TEST SETUP (FIGURE 2) BREAK-BEFORE-MAKE TIME (ns) FIGURE 22. BREAK-BEFORE-MAKE vs ANALOG VOLTAGE 5 SEE BBM TEST SETUP (FIGURE 2) SUPPLY VOLTAGE (±V) FIGURE 23. BREAK-BEFORE-MAKE vs POWER SUPPLY VOLTAGE t ON, t OFF (ns) t ON, V S = V 8 t ON, V S = -V 2 t OFF, V S = V 6 t OFF, V S = -V V IN (V) 6 t ON, t OFF (ns) t ON, V S = V t OFF, V S = -V t ON, V S = -V t OFF, V S = V TEMPERATURE ( ) FIGURE 24. SWITHING TIME vs INPUT LOGI VOLTAGE (NOTE 8) FIGURE 25. SWITHING TIME vs TEMPERATURE (NOTE 8) t ON, t OFF (ns) V S = 5V t ON V S = -5V t ON V S = 5V t OFF V S = -5V t OFF t ON, t OFF (ns) = V = -5V = = -5V = -5V = V t ON t ON t ON = V V S = 5V SUPPLY VOLTAGE (±V) 6 3 t OFF POSITIVE SUPPLY (V) FIGURE 26. SWITHING TIME vs POWER SUPPLY VOLTAGE (NOTE 8) FIGURE 27. SWITHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8) 9 FN3284. November 2, 26

10 Typical Performance urves (ontinued) 3 27 V S = -5V t ON, t OFF (ns) = -5V t ON t ON = -5V t OFF t OFF POSITIVE SUPPLY (V) FIGURE 28. SWITHING TIME vs POSITIVE SUPPLY VOLTAGE (NOTE 8) NOTE: 8. Refer to Figure for test conditions. FN3284. November 2, 26

11 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA 2 3.5(.2) e D.(.4) M A M E -B- -Ab -- SEATING PLANE A B S E.25(.) M B A NOTES:. These package dimensions are within allowable dimensions of JEDE MO-53-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch).. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. (Angles in degrees) α GAUGE PLANE.(.4).25. A2 M L c M LEAD THIN SHRINK SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c D E e.26 BS.65 BS - E L N α Rev. 2/2 FN3284. November 2, 26

12 Small Outline Plastic Packages (SOI) N INDEX AREA 2 3 e D B.25(.) M A M E -B- -A- -- SEATING PLANE A B S H.25(.) M B A.(.4) NOTES:. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.24 inch).. ontrolling dimension: MILLIMETER. onverted inch dimensions are not necessarily exact. α L M h x 45 M6.5 (JEDE MS-2-A ISSUE ) 6 LEAD NARROW BODY SMALL OUTLINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B D E e.5 BS.27 BS - H h L N α Rev. 6/5 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see 2 FN3284. November 2, 26