Data Sheet January Features. Pinout. NUMBER OF BITS LINEARITY (INL, DNL) TEMP. RANGE ( o C) PACKAGE PKG. NO.

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1 TM AD753, Data Sheet January 00 FN305. 8Bit, 0Bit Multiplying D/A Converters The AD753 and are monolithic, low cost, high performance, 8bit and 0bit accurate, multiplying digitaltoanalog converter (DAC), in a pin DIP. Intersil s thin film resistors on CMOS circuitry provide 0bit resolution (8bit accuracy), with TTL/CMOS compatible operation. The AD753 and s accurate four quadrant multiplication, full input protection from damage due to static discharge by clamps to V and GND, and very low power dissipation make them very versatile converters. Low noise audio gain controls, motor speed controls, digitally controlled gain and digital attenuators are a few of the wide range of applications of the AD753 and. Functional Block Diagram Features 8Bit Linearity Low Gain and Linearity Temperature Coefficients Full Temperature Range Operation Static Discharge Input Protection TTL/CMOS Compatible Supply Range V to 5V Fast Settling Time at 5 o C ns (Max) Four Quadrant Multiplication Direct AD750 Equivalent Pinout AD753, (PDIP) TOP VIEW V IN 0kΩ 0kΩ 0kΩ 0kΩ I OUT (5) I OUT 5 V IN SPDT NMOS SWITCHES (3) I OUT () I OUT () GND BIT () BIT BIT 3 BIT BIT V /BIT 0 (NOTE) /BIT 9 (NOTE) BIT 8 BIT 7 BIT 0kΩ () BIT BIT 3 (5) () () NOTE: for AD753 only. NOTE: Switches shown for digital inputs High Ordering Information PART NUMBER NUMBER OF BITS LINEARITY (INL, DNL) TEMP. RANGE ( o C) PACKAGE PKG. NO. AD753JN 8 0.% (8Bit) 0 to 70 Ld PDIP E.3 JN 0 0.% (8Bit) 0 to 70 Ld PDIP E.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or 3773 Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00. All Rights Reserved

2 Absolute Maximum Ratings Supply Voltage (V to GND) V V ±5V Digital Input Voltage Range V to GND Output Voltage Compliance mV to V Operating Conditions Temperature Range o C to 70 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature o C to 50 o C Maximum Lead Temperature (Soldering 0s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V = 5V, V = 0V, = = 0V, Unless Otherwise Specified AD753 T A 5 o C T A MINMAX T A 5 o C T A MINMAX PARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX UNITS SYSTEM PERFORMAE Resolution Bits Nonlinearity 0V V 0V, = = 0V (Notes, 3, ) ±0. ±0. ±0. ±0. % of FSR Monotonicity Guaranteed Guaranteed Gain Error All Digital Inputs High (Note 3) ±.5 ±.8 ±. ±.8 % of FSR Nonlinearity Tempco 0V V 0V (Notes 3, ) ± ± ± ± ppm of FSR/ o C Gain Error Tempco ±0 ±0 ±0 ±0 ppm of FSR/ o C Output Leakage Current (Either Output) = = 0 ±50 ±00 ±50 ±00 na DYNAMIC CHARACTERISTICS Power Supply Rejection V =.0V to 5.0V (Note 3) ±0.0 ±0.03 ±0.005 ±0.008 % of FSR/% of V Output Current Settling Time Feedthrough Error EREE INPUTS Input Resistance (Pin 5) To 0.% of FSR, R L = 00Ω (Note ) V = 0V PP, 00kHz Sine Wave, All Digital Inputs Low (Note ) All Digital Inputs High I OUT at Ground (Note ) ns ±/ ± ±0.05 ± kω kω Temperature Coefficient ppm/ ο C

3 Electrical Specifications V = 5V, V = 0V, = = 0V, Unless Otherwise Specified (Continued) AD753 T A 5 o C T A MINMAX T A 5 o C T A MINMAX PARAMETER TEST CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX UNITS ANALOG OUTPUT Output Capacitance C OUT All Digital Inputs High (Note ) pf C OUT pf C OUT All Digital Inputs Low (Note ) pf C OUT pf DIGITAL INPUTS Low State Threshold, V IL V High State Threshold, V IH,,.. V Input Current (Low or High), I IL, I IH V IN = 0V or 5V ± ± ± ± µa Input Coding See Tables through 3 Binary/Offset Binary Binary/Offset Binary Input Capacitance (Note ) pf POWER SUPPLY CHARACTERISTICS Power Supply Voltage Range (Note ) 5 to 5 to V I All Digital Inputs High or Low (Excluding Ladder Network).5.5 ma. Full Scale Range (FSR) is 0V for unipolar and ±0V for bipolar modes. 3. Using internal feedback resistor,.. Guaranteed by design or characterization and not production tested. 5. Accuracy not guaranteed unless outputs at ground potential.. Accuracy is tested and guaranteed at V = 5V, only. Definition of Terms Nonlinearity: Error contributed by deviation of the DAC transfer function from a best straight line through the actual plot of transfer function. Normally expressed as a percentage of full scale range or in (sub)multiples of. Resolution: It is addressing the smallest distinct analog output change that a D/A converter can produce. It is commonly expressed as the number of converter bits. A converter with resolution of n bits can resolve output changes of N of the fullscale range, e.g., N V for a unipolar conversion. Resolution by no means implies linearity. Settling Time: Time required for the output of a DAC to settle to within specified error band around its final value (e.g., / ) for a given digital input change, i.e., all digital inputs LOW to HIGH and HIGH to LOW. Gain Error: The difference between actual and ideal analog output values at fullscale range, i.e., all digital inputs at HIGH state. It is expressed as a percentage of full scale range or in (sub)multiples of. Feedthrough Error: Error caused by capacitive coupling from V to I OUT with all digital inputs LOW. Output Capacitance: Capacitance from I OUT, and I OUT terminals to ground. Output Leakage Current: Current which appears on I OUT, terminal when all digital inputs are LOW or on I OUT terminal when all digital inputs are HIGH. For further information on the use of this device, see the following Application Notes: Application Notes NOTE # AN00 AN08 AN0 DESCRIPTION Principles of Data Acquisition and Conversion Do s and Don ts of Applying A/D Converters Interpretation of Data Conversion Accuracy Specifications 3

4 Detailed Description The AD753 and are monolithic multiplying D/A converters. A highly stable thin film RR resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voltage output applications. A simplified equivalent circuit of the DAC is shown in the Functional Diagram. The NMOS SPDT switches steer the ladder leg currents between I OUT and I OUT buses which must be held at ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduce offset (leakage) errors to a negligible level. The level shifter circuits are comprised of three inverters with positive feedback from the output of the second to the first, see Figure. This configuration results in TTL/CMOS compatible operation over the full military temperature range. With the ladder SPDT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the R ladder resistors and high accurate leg currents. V TTL/ CMOS INPUT 3 Typical Applications FIGURE. CMOS SWITCH Unipolar Binary Operation AD753 (8Bit DAC) The circuit configuration for operating the AD753 in unipolar mode is shown in Figure. With positive and negative V values the circuit is capable of Quadrant multiplication. The Digital Input Code/Analog Output Value table for unipolar mode is given in Table. 5 7 TO LADDER I OUT 8 9 I OUT DATA INPUTS TABLE. UNlPOLAR BINARY CODE AD753 DIGITAL INPUT ANALOG OUTPUT ( ) V V = = = ( )( V ) = ( V ). 5 Zero Offset Adjustment. Connect all digital inputs to GND.. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±mv (Max) at. Gain Adjustment ±0V 5V V R R 5 AD753/ OUT CR OUT 3 GND 7. R and R used only if gain adjustment is required. 8. CR protects AD753 and against negative transients. FIGURE. UNIPOLAR BINARY OPERATION. Connect all digital inputs to V.. Monitor for a V ( / 8 ) reading. 3. To increase, connect a series resistor, R, (0Ω to 50Ω) in the I OUT amplifier feedback loop.. To decrease, connect a series resistor, R, (0Ω to 50Ω) between the reference voltage and the V terminal. Unipolar Binary Operation (0Bit DAC) The circuit configuration for operating the in unipolar mode is shown in Figure. With positive and negative V values the circuit is capable of Quadrant multiplication. The Digital Input Code/Analog Output Value table for unipolar mode is given in Table.

5 TABLE. UNlPOLAR BINARY CODE DIGITAL INPUT Zero Offset Adjustment 5. Connect all digital inputs to GND.. Adjust the offset zero adjust trimpot of the output operational amplifier for 0V ±mv (Max) at. Gain Adjustment (NOTE 0) NOMINAL ANALOG OUTPUT V V = = as shown in Figure.. Nominal Full Scale for the circuit of Figure is given by: 03 FS =. 0. Nominal magnitude for the circuit of Figure is given by: = V. 0. Connect all digital inputs to V.. Monitor for a V ( / 0 ) reading. 3. To increase, connect a series resistor, R, (0Ω to 50Ω) in the I OUT amplifier feedback loop.. To decrease, connect a series resistor, R, (0Ω to 50Ω) between the reference voltage and the V terminal. Bipolar (Offset Binary) Operation AD753 The circuit configuration for operating the AD753 in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, FourQuadrant multiplication can be realized. The Digital Input Code/Analog Output Value table for bipolar mode is given in Table 3.) A Logic input at any digital input forces the corresponding ladder switch to steer the bit current to I OUT bus. A Logic 0 input forces the bit current to I OUT bus. For any code the I OUT and I OUT bus currents are complements of one another. The current amplifier at I OUT changes the polarity of I OUT current and the transconductance amplifier at I OUT output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, ( = Logic, all other bits = Logic 0 ), is corrected by using an external resistor, (0MΩ), from V to I OUT (Figure 3). TABLE 3. BlPOLAR (OFFSET BINARY) CODE AD753 DIGITAL INPUT ANALOG OUTPUT V V 7 8 V = ( )( V ) = ( V ). 8 Offset Adjustment. Adjust V to approximately 0V.. Connect all digital inputs to Logic. 3. Adjust I OUT amplifier offset adjust trimpot for 0V ±mv at I OUT amplifier output.. Connect (Bit ) to Logic and all other bits to Logic Adjust I OUT amplifier offset adjust trimpot for 0V ±mv at. Gain Adjustment. Connect all digital inputs to V.. Monitor for a V ( / 8 ) volts reading. 3. To increase, connect a series resistor, R, of up to 50Ω between and.. To decrease, connect a series resistor, R, of up to 50Ω between the reference voltage and the V terminal. Bipolar (Offset Binary) Operation The circuit configuration for operating the in the bipolar mode is given in Figure 3. Using offset binary digital input codes and positive and negative reference voltage values, Quadrant multiplication can be realized. The Digital Input Code/Analog Output Value table for bipolar mode is given in Table. A Logic input at any digital input forces the corresponding ladder switch to steer the bit current to I OUT bus. A Logic 0 input forces the bit current to I OUT bus. For any code the I OUT and I OUT bus currents are complements of one another. The current amplifier at I OUT changes the polarity of I OUT current and the transconductance amplifier at I OUT output sums the two currents. This configuration doubles the output range. The difference current resulting at zero offset binary code, ( = Logic, all other bits = Logic 0 ), is corrected by using an external resistor, (0MΩ), from V to I OUT. 5

6 ±0V 5V V R 5 R DATA INPUTS AD753/ 3 3 I OUT I OUT R 5K R3 5K CR R 0MΩ CR FIGURE 3. BIPOLAR OPERATION (QUADRANT MULTIPLICATION) TABLE. UNlPOLAR BINARY CODE DIGITAL INPUT (NOTE ) NOMINAL ANALOG OUTPUT V 5 5 V 5 0 V V V 5 5. as shown in Figure Nominal Full Scale for the circuit of Figure 3 is given by: 03 FSR = V. 5. Nominal magnitude for the circuit of Figure 3 is given by: = V. 5 Offset Adjustment 5. Adjust V to approximately 0V.. Connect all digital inputs to Logic. 7. Adjust I OUT amplifier offset adjust trimpot for 0V ±mv at I OUT amplifier output. 8. Connect (Bit ) to Logic and all other bits to Logic Adjust I OUT amplifier offset adjust trimpot for 0V ±mv at. Gain Adjustment. Connect all digital inputs to V.. Monitor for a V ( 9 ) volts reading. 3. To increase, connect a series resistor (R) of up to 50Ω between and.. To decrease, connect a series resistor (R) of up to 50Ω between the reference voltage and the V terminal.

7 ±0V BIPOLAR ANALOG INPUT V V DIGITAL INPUT MAGNITUDE BITS GND 0K OUT OUT 5K / IH50 0K SIGN BIT FIGURE. 0BIT AND SIGN MULTIPLYING DAC CALIBRATE 0K 5V V DD.8V () K.7K A 0K % 0K % SQUARE WAVE DIGITAL FREQUEY CONTROL WORD 5 AD753/ 3 3 OUT OUT C A TRIANGULAR WAVE FIGURE 5. PROGRAMMABLE FUTION GENERATOR V IN R FB 5V V BIT OUT DIGITAL AD753/ INPUT OUT D 3 5 BIT 8 (0) () V BIT DIGITAL INPUT D BIT 8 (0) () 5V 5 AD753/ 3 3 R R = V IN/D Where: Bit Bit D = Bit 8 0 D 55 5 FIGURE. DIVIDER (DIGITALLY CONTROLLED GAIN) R V V R D = OUT R R R R Bit Bit Where D = Bit D 55 5 FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET 7

8 Die Characteristics DIE DIMENSIONS 0 mils x 03 mils (55µm x µm) METALLIZATION Type: Pure Aluminum Thickness: 0 ±kå PASSIVATION Type: PSG/Nitride PSG: 7 ±.kå Nitride: 8 ±.kå PROCESS CMOS Metal Gate Metallization Mask Layout AD753, PIN 7 BIT PIN BIT 3 PIN 5 BIT PIN BIT () PIN 3 GND PIN 8 BIT 5 PIN I OUT PIN I OUT PIN 9 BIT PIN 0 BIT 7 PIN PIN BIT 8 () PIN 5 V (PIN, BIT 9, ) (PIN 3, BIT 0, ) PIN V 8

9 DualInLine Plastic Packages (PDIP) INDEX AREA N 3 N/ B A D E BASE PLANE A C A SEATING PLANE L C L D A e D A B e e C C B e B 0.00 (0.5) M C A BS. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.5M Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JE DEC seating plane gauge GS3. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum C. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.5mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ ) for E8.3, E.3, E8.3, E8.3, E. will have a B dimension of inch (0.7.mm). E E.3 (JEDEC MS00BB ISSUE D) LEAD DUALINLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , 0 C D D E E e 0.00 BSC.5 BSC e A BSC 7. BSC e B L N 9 Rev. 0 /93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERICA Intersil Corporation 7585 Irvine Center Drive Suite 00 Irvine, CA 98 TEL: (99) FAX: (99) 373 For information regarding Intersil Corporation and its products, see 9 Intersil Corporation 0 Palm Bay Rd. Palm Bay, FL 3905 TEL: (3) FAX: (3) 779 EUROPE Intersil Europe Sarl Ave. William Graisse, 3 00 Lausanne Switzerland TEL: 050 FAX: 0579 ASIA Intersil Corporation Unit 80 8/F Guangdong Water Building 83 Austin Road TST, Kowloon Hong Kong TEL: FAX: