ICL7660, ICL7660A. CMOS Voltage Converters. Features. Applications. Pinouts FN Data Sheet October 10, 2005

Transcription

1 ICL, ICLA Data Sheet October, FN. CMOS Voltage Converters The Intersil ICL and ICLA are monolithic CMOS power supply circuits which offer unique performance advantages over previously available devices. The ICL performs supply voltage conversions from positive to negative for an input range of.v to.v resulting in complementary output voltages of.v to.v and the ICLA does the same conversions with an input range of.v to.v resulting in complementary output voltages of.v to.v. Only noncritical external capacitors are needed for the charge pump and charge reservoir functions. The ICL and ICLA can also be connected to function as voltage doublers and will generate output voltages up to.v with a V input. Contained on the chip are a series DC supply regulator, RC oscillator, voltage level translator, and four output power MOS switches. A unique logic element senses the most negative voltage in the device and ensures that the output NChannel switch sourcesubstrate junctions are not forward biased. This assures latchup free operation. The oscillator, when unloaded, oscillates at a nominal frequency of khz for an input supply voltage of.v. This frequency can be lowered by the addition of an external capacitor to the OSC terminal, or the oscillator may be overdriven by an external clock. Features Simple Conversion of V Logic Supply to ±V Supplies Simple Voltage Multiplication ( = () nv IN ) Typical Open Circuit Voltage Conversion Efficiency 99.9% Typical Power Efficiency 9% Wide Operating Voltage Range ICL V to.v ICLA V to.v ICLA % Tested at V Easy to Use Requires Only External NonCritical Passive Components No External Diode Over Full Temp. and Voltage Range PbFree Plus Anneal Available (RoHS Compliant) Applications On Board Negative Supply for Dynamic RAMs Localized µprocessor ( Type) Negative Supplies Inexpensive Negative Supplies Data Acquisition Systems The LV terminal may be tied to GROUND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (.V to.v for the ICL and.v to.v for the ICLA), the LV pin is left floating to prevent device latchup. Pinouts ICL, ICLA ( LD PDIP, SOIC) TOP VIEW NC V CAP OSC GND LV CAP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 999,. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 ICL, ICLA Ordering Information PART NUMBER TEMP. RANGE ( C) PACKAGE PKG. DWG. # ICLCBA* CBA to Ld SOIC (N) M. ICLCBAZ* (See Note) CBAZ to Ld SOIC (N) (Pbfree) M. ICLCBAZA* (See Note) CBAZ to Ld SOIC (N) (Pbfree) M. ICLCPA CPA to Ld PDIP E. ICLCPAZ ( See Note) CPAZ to Ld PDIP** (Pbfree) E. ICLACBA* ACBA to Ld SOIC (N) M. ICLACBAZA* (See Note) ACBAZ to Ld SOIC (N) (Pbfree) M. ICLACPA ACPA to Ld PDIP E. ICLACPAZ (See Note) ACPAZ to Ld PDIP** (Pbfree) E. ICLAIBA* AIBA to Ld SOIC (N) M. ICLAIBAZA* (See Note) AIBAZ to Ld SOIC (N) (Pbfree) M. *Add T suffix to part number for tape and reel packaging. **Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD. FN. October,

3 ICL, ICLA C Absolute Maximum Ratings Supply Voltage ICL V ICLA V LV and OSC Input Voltage V to (V.V) for V <.V (Note ) (V.V) to (V.V) for V >.V Current into LV (Note ) µa for V >.V Output Short Duration (V SUPPLY.V) Continuous Operating Conditions Temperature Range ICLC, ICLAC C to C ICLAI C to C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( C/W) θ JC ( C/W) PDIP Package* N/A SOIC Package N/A Maximum Storage Temperature Range C to C Maximum Lead Temperature (Soldering, s) C (SOIC Lead Tips Only) *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications ICL and ICLA, V = V, T A = C, C OSC =, Test Circuit Figure Unless Otherwise Specified ICL ICLA PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Supply Current I R L = µa Supply Voltage Range Lo V L MIN T A MAX, R L = kω, LV to GND.... V Supply Voltage Range Hi V H MIN T A MAX, R L = kω, LV to Open.. V Output Source Resistance R OUT I OUT = ma, T A = C Ω I OUT = ma, C T A C Ω I OUT = ma, C T A C Ω I OUT = ma, C T A C Ω V = V, I OUT = ma, LV to GND C T A C V = V, I OUT = ma, LV to GND, C T A C Ω Ω Oscillator Frequency f OSC khz Power Efficiency P EF R L = kω % Voltage Conversion Efficiency EF R L = % Oscillator Impedance Z OSC V = V. MΩ V = V kω ICLA, V = V, T A = C, OSC = Free running, Test Circuit Figure, Unless Otherwise Specified Supply Current (Note ) I V = V, R L =, C µa C < T A < C µa C < T A < C µa Output Source Resistance R OUT V = V, I OUT = ma 9 Ω C < T A < C Ω C < T A < C Ω Oscillator Frequency (Note ) f OSC V = V (same as V conditions). khz C < T A < C. khz C < T A < C. khz FN. October,

4 ICL, ICLA Electrical Specifications ICL and ICLA, V = V, T A = C, C OSC =, Test Circuit Figure Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS ICL ICLA MIN TYP MAX MIN TYP MAX Voltage Conversion Efficiency EFF V = V, R L = 99 % T MIN < T A < T MAX 99 % Power Efficiency P EFF V = V, R L = kω 9 % T MIN < T A < T MAX 9 % NOTES:. Connecting any input terminal to voltages greater than V or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to power up of the ICL, ICLA.. Derate linearly above C by.mw/ C.. In the test circuit, there is no external capacitor applied to pin. However, when the device is plugged into a test socket, there is usually a very small but finite stray capacitance present, of the order of pf.. The Intersil ICLA can operate without an external diode over the full temperature and voltage range. This device will function in existing designs which incorporate an external diode with no degradation in overall circuit performance. UNITS Functional Block Diagram V RC OSCILLATOR VOLTAGE LEVEL TRANSLATOR CAP CAP OSC LV VOLTAGE REGULATOR LOGIC NETWORK Typical Performance Curves (Test Circuit of Figure ) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE RANGE (NO DIODE REQUIRED) OUTPUT SOURCE RESISTANCE (Ω) K T A = C TEMPERATURE ( C) FIGURE. OPERATING VOLTAGE AS A FUNCTION OF TEMPERATURE SUPPLY VOLTAGE (V) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF SUPPLY VOLTAGE FN. October,

5 ICL, ICLA Typical Performance Curves (Test Circuit of Figure ) (Continued) OUTPUT SOURCE RESISTANCE (Ω) I OUT = ma V = V V = V TEMPERATURE ( C) POWER CONVERSION EFFICIENCY (%) T A = C 9 9 I OUT = ma I OUT = ma V = V K K OSC. FREQUENCY f OSC (Hz) FIGURE. OUTPUT SOURCE RESISTANCE AS A FUNCTION OF TEMPERATURE FIGURE. POWER CONVERSION EFFICIENCY AS A FUNCTION OF OSC. FREQUENCY K OSCILLATOR FREQUENCY f OSC (Hz) K V = V T A = C. K C OSC (pf) OSCILLATOR FREQUENCY f OSC (khz) V = V TEMPERATURE ( C) FIGURE. FREQUENCY OF OSCILLATION AS A FUNCTION OF EXTERNAL OSC. CAPACITANCE FIGURE. UNLOADED OSCILLATOR FREQUENCY AS A FUNCTION OF TEMPERATURE OUTPUT VOLTAGE T A = C V = V SLOPE Ω LOAD CURRENT I L (ma) FIGURE. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT POWER CONVERSION EFFICIENCY (%) 9 P EFF I 9 T A = C V = V LOAD CURRENT I L (ma) FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT SUPPLY CURRENT I (ma) FN. October,

6 ICL, ICLA Typical Performance Curves (Test Circuit of Figure ) (Continued) OUTPUT VOLTAGE T A = C V = V SLOPE Ω LOAD CURRENT I L (ma) POWER CONVERSION EFFICIENCY (%) 9 I... P EFF T A = C V = V LOAD CURRENT I L (ma) SUPPLY CURRENT (ma) (NOTE ) FIGURE 9. OUTPUT VOLTAGE AS A FUNCTION OF OUTPUT CURRENT FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIENCY AS A FUNCTION OF LOAD CURRENT NOTE:. These curves include in the supply current that current fed directly into the load R L from the V (See Figure ). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL/ICLA, to the negative side of the load. Ideally, V IN, I S I L, so V IN x I S x I L. I S V (V) C µf ICL ICLA I L R L C OSC (NOTE) C µf NOTE: For large values of C OSC (>pf) the values of C and C should be increased to µf. FIGURE. ICL, ICLA TEST CIRCUIT Detailed Description The ICL and ICLA contain all the necessary circuitry to complete a negative voltage converter, with the exception of external capacitors which may be inexpensive µf polarized electrolytic types. The mode of operation of the device may be best understood by considering Figure, which shows an idealized negative voltage converter. Capacitor C is charged to a voltage, V, for the half cycle when switches S and S are closed. (Note: Switches S and S are open during this half cycle.) During the second half cycle of operation, switches S and S are closed, with S and S open, thereby shifting capacitor C negatively by V volts. Charge is then transferred from C to C such that the voltage on C is exactly V, assuming ideal switches and no load on C. The ICL approaches this ideal situation more closely than existing nonmechanical circuits. In the ICL and ICLA, the switches of Figure are MOS power switches; S is a PChannel device and S, S and S are NChannel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S and S must always remain reverse biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit startup, and under output short circuit conditions ( = V), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. This problem is eliminated in the ICL and ICLA by a logic network which senses the output voltage ( ) together with the level translators, and switches the substrates of S and S to the correct level to maintain necessary reverse bias. FN. October,

7 ICL, ICLA The voltage regulator portion of the ICL and ICLA is an integral part of the antilatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the LV pin should be connected to GROUND, disabling the regulator. For supply voltages greater than.v the LV terminal must be left open to insure latchup proof operation, and prevent device damage. V IN S S C S S Theoretical Power Efficiency Considerations = V IN FIGURE. IDEALIZED NEGATIVE VOLTAGE CONVERTER In theory a voltage converter can approach % efficiency if certain conditions are met.. The driver circuitry consumes minimal power.. The output switches have extremely low ON resistance and virtually no offset.. The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The ICL and ICLA approach these conditions for negative voltage conversion if large values of C and C are used. C ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: E = / C (V V ) where V and V are the voltages on C during the pump and transfer cycles. If the impedances of C and C are relatively high at the pump frequency (refer to Figure ) compared to the value of R L, there will be a substantial difference in the voltages V and V. Therefore it is not only desirable to make C as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C in order to achieve maximum efficiency of operation. Do s And Don ts. Do not exceed maximum supply voltages.. Do not connect LV terminal to GROUND for supply voltages greater than.v.. Do not short circuit the output to V supply for supply voltages above.v for extended periods, however, transient conditions including startup are okay.. When using polarized capacitors, the terminal of C must be connected to pin of the ICL and ICLA and the terminal of C must be connected to GROUND.. If the voltage supply driving the ICL and ICLA has a large source impedance (Ω Ω), then a.µf capacitor from pin to ground may be required to limit rate of rise of input voltage to less than V/µs.. User should insure that the output (pin ) does not go more positive than GND (pin ). Device latch up will occur under these conditions. A N9 or similar diode placed in parallel with C will prevent the device from latching up under these conditions. (Anode pin, Cathode pin ). V µf ICL ICLA V R O µf = V FIGURE A. CONFIGURATION FIGURE B. THEVENIN EQUIVALENT FIGURE. SIMPLE NEGATIVE CONVERTER FN. October,

8 ICL, ICLA t t B V (V) A FIGURE. OUTPUT RIPPLE V C ICL ICLA C ICL ICLA n R L C FIGURE. PARALLELING DEVICES V µf ICL ICLA µf ICL ICLA n µf µf = nv FIGURE. CASCADING DEVICES FOR INCREASED OUTPUT VOLTAGE Typical Applications Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICL and ICLA for generation of negative supply voltages. Figure shows typical connections to provide a negative supply negative (GND) for supply voltages below.v. The output characteristics of the circuit in Figure A can be approximated by an ideal voltage source in series with a resistance as shown in Figure B. The voltage source has a value of V. The output impedance (R O ) is a function of the ON resistance of the internal MOS switches (shown in Figure ), the switching frequency, the value of C and C, and the ESR (equivalent series resistance) of C and C. A good first order approximation for R O is: R O (R SW R SW ESR C ) (R SW R SW ESR C ) R O (R SW R SW ESR C ) (f PUMP ) (C) ESR C f OSC (f PUMP =, R SWX = MOSFET switch resistance) Combining the four R SWX terms as R SW, we see that: R O (R SW ) RSW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically Ω at C and V. Careful selection of C and C will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the /(f PUMP C ) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the /(f PUMP C) term, but may have the side effect of a net increase in output impedance when C > µf and there is no longer enough time to fully charge the capacitors (f PUMP ) (C) (ESR C ) ESR C FN. October,

9 ICL, ICLA every cycle. In a typical application where f OSC = khz and C = C = C = µf: R O () R O (ESR C ) Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of, a high value could potentially swamp out a low /(f PUMP C ) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as Ω. R O () R O/ (ESR C ) Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of, a high value could potentially swamp out a low /(f PUMP C ) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as Ω. Output Ripple ( ) ( ) ( ) ( ) (ESR C ) ESR C (ESR C ) ESR C ESR also affects the ripple voltage seen at the output. The total ripple is determined by voltages, A and B, as shown in Figure. Segment A is the voltage drop across the ESR of C at the instant it goes from being charged by C (current flow into C ) to being discharged through the load (current flowing out of C ). The magnitude of this current change is I OUT, hence the total drop is I OUT esr C V. Segment B is the voltage change across C during time t, the half of the cycle when C supplies current to the load. The drop at B is l OUT t/c V. The peaktopeak ripple voltage is the sum of these voltage drops: V RIPPLE [ (f PUMP ) (C) (ESR C ) ] I OUT Again, a low ESR capacitor will reset in a higher performance output. Paralleling Devices Any number of ICL and ICLA voltage converters may be paralleled to reduce output resistance. The reservoir capacitor, C, serves all devices while each device requires its own pump capacitor, C. The resultant output resistance would be approximately: R OUT = R OUT (of ICL/ICLA) n (number of devices) Cascading Devices The ICL and ICLA may be cascaded as shown to produced larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is devices for light loads. The output voltage is defined by: = n (V IN ), where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL and ICLA R OUT values. Changing the ICL/ICLA Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure. In order to prevent possible device latchup, a kω resistor must be used in series with the clock output. In a situation where the designer has generated the external clock frequency using TTL logic, the addition of a kω pullup resistor to V supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be / of the clock frequency. Output transitions occur on the positivegoing edge of the clock. µf ICL ICLA It is also possible to increase the conversion efficiency of the ICL and ICLA at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is shown in Figure. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C ) and reservoir (C ) capacitors; this is overcome by increasing the values of C and C by the same factor that the frequency has been reduced. For example, the addition of a pf capacitor between pin (OSC) and V will lower the oscillator frequency to khz from its nominal frequency of khz (a multiple of ), and thereby necessitate a corresponding increase in the value of C and C (from µf to µf). V kω µf FIGURE. EXTERNAL CLOCKING V CMOS GATE 9 FN. October,

10 ICL, ICLA C ICL ICLA V C OSC C C ICL ICLA V D D = (nv IN V FDX ) C = (V) (V FD ) (V FD ) FIGURE. LOWERING OSCILLATOR FREQUENCY Positive Voltage Doubling The ICL and ICLA may be employed to achieve positive voltage doubling using the circuit shown in Figure 9. In this application, the pump inverter switches of the ICL and ICLA are used to charge C to a voltage level of V V F (where V is the supply voltage and V F is the forward voltage drop of diode D ). On the transfer cycle, the voltage on C plus the supply voltage (V) is applied through diode D to capacitor C. The voltage thus created on C becomes (V) (VF) or twice the supply voltage minus the combined forward voltage drops of diodes D and D. The source impedance of the output ( ) will depend on the output current, but for V = V and an output current of ma it will be approximately Ω. ICL ICLA Combined Negative Voltage Conversion and Positive Supply Doubling Figure combines the functions shown in Figures and Figure 9 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating 9V and V from an existing V supply. In this instance capacitors C and C perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C and C are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin of the device. V D D C C FIGURE 9. POSITIVE VOLT DOUBLER = (V) (V F ) C FIGURE. COMBINED NEGATIVE VOLTAGE CONVERTER AND POSITIVE DOUBLER Voltage Splitting The bidirectional characteristics can also be used to split a higher supply in half, as shown in Figure. The combined load will be evenly shared between the two sides. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure, V can be converted (via., and.) to a nominal V, although with rather high series output resistance (~Ω). R L µf = V V µf R L µf Regulated Negative Voltage Supply ICL ICLA C FIGURE. SPLITTING A SUPPLY IN HALF In some cases, the output impedance of the ICL and ICLA can be a problem, particularly if the load current varies substantially. The circuit of Figure can be used to overcome this by controlling the input voltage, via an ICL lowpower CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICLs and ICLAs output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL and ICLA, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than Ω to a load of ma. V V FN. October,

11 ICL, ICLA Other Applications Further information on the operation and use of the ICL and ICLA may be found in AN Principals and Applications of the ICL and ICLA CMOS Voltage Converter. V K K K K ICL V Ω µf ICL9 µf ICL ICLA K K VOLTAGE ADJUST µf FIGURE. REGULATING THE OUTPUT VOLTAGE V LOGIC SUPPLY TTL DATA INPUT RS DATA OUTPUT V V µf ICL ICLA µf IH FIGURE. RS LEVELS FROM A SINGLE V SUPPLY All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN. October,