ICL8038. Precision Waveform Generator/Voltage Controlled Oscillator. Features. [ /Title (ICL80 38) /Subject. enertor/vo. tage. Ordering Information

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1 [ /Title (IL0 ) /Subject Preciion aveorm enertor/vo tage onrolled scilator) Autho () Keyords Interil orpoation, emionuctor, aveorm eneraor, oltge onrolled scillaor, precision, TM Precision Waveform Generator/Voltage ontrolled Oscillator The IL0 waveform generator is a monolithic integrated circuit capable of producing high accuracy sine, square, triangular, sawtooth and pulse waveforms with a minimum of external components. The frequency (or repetition rate) can be selected externally from 0.00Hz to more than 00kHz using either resistors or capacitors, and frequency modulation and sweeping can be accomplished with an external voltage. The IL0 is fabricated with advanced monolithic technology, using Schottky barrier diodes and thin film resistors, and the output is stable over a wide range of temperature and supply variations. These devices may be interfaced with phase locked loop circuitry to reduce temperature drift to less than 50ppm/ o. Ordering Information Pinout OBSOLETE PRODUT NO REOMMENDED REPLAEMENT contact our Technical Support enter at --INTERSIL or IL0 (PDIP, ERDIP) TOP VIEW Features IL0 File Number 4.4 Low Frequency Drift with Temperature ppm/ o Low Distortion % (Sine Wave Output) High Linearity % (Triangle Wave Output) Wide Frequency Range Hz to 00kHz Variable Duty ycle % to 9% High Level Outputs TTL to V Simultaneous Sine, Square, and Triangle Wave Outputs Easy to Use - Just a Handful of External omponents Required PART NUMBER STABILITY TEMP. RANGE ( o ) PAKAGE PKG. NO. IL0PD 50ppm/ o (Typ) 0 to 0 4 Ld PDIP E4. IL0JD 50ppm/ o (Typ) 0 to 0 4 Ld ERDIP F4. IL0BJD 0ppm/ o (Typ) 0 to 0 4 Ld ERDIP F4. IL0AJD 0ppm/ o (Typ) 0 to 0 4 Ld ERDIP F4. SINE WAVE ADJUST SINE WAVE OUT TRIANGLE OUT DUTY YLE 4 FREQUENY ADJUST 5 FM BIAS Data Sheet April 00 4 N N SINE WAVE ADJUST V- OR GND 9 TIMING APAITOR SQUARE WAVE OUT FM SWEEP INPUT Functional Diagram URRENT SOURE # URRENT SOURE # BUFFER I I OMPARATOR # OMPARATOR # FLIP-FLOP BUFFER SINE ONVERTER 9 V- OR GND AUTION: These devices are sensitive to electrostatic discharge; follow proper I Handling Procedures. --INTERSIL or -4-4 Intersil and Design is a trademark of Intersil Americas Inc. opyright Intersil Americas Inc. 00, All Rights Reserved

2 IL0 Absolute Maximum Ratings Supply Voltage (V- to ) V Input Voltage (Any Pin) V- to Input urrent (Pins 4 and 5) mA Output Sink urrent (Pins and 9) mA Operating onditions Temperature Range IL0A, IL0B, IL o to 0 o Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o /W) θ J ( o /W) ERDIP Package PDIP Package N/A Maximum Junction Temperature (eramic Package) o Maximum Junction Temperature (Plastic Package) o Maximum Storage Temperature Range o to 50 o Maximum Lead Temperature (Soldering s) o Die haracteristics Back Side Potential V- AUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation P board in free air. Electrical Specifications V SUPPLY = ±V or +0V, T A = 5 o, R L = kω, Test ircuit Unless Otherwise Specified PARAMETER SYMBOL TEST ONDITIONS IL0 IL0B IL0A MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Supply Voltage Operating Range V SUPPLY Single Supply V, V- Dual Supplies ±5 - ±5 ±5 - ±5 ±5 - ±5 V Supply urrent I SUPPLY V SUPPLY = ±V (Note ) ma FREQUENY HARATERISTIS (All Waveforms) Max. Frequency of Oscillation f MAX khz Sweep Frequency of FM Input f SWEEP khz Sweep FM Range (Note ) - 5: - - 5: - - 5: - FM Linearity : Ratio % Frequency Drift with Temperature (Note 5) Frequency Drift with Supply Voltage Δf/ΔV Over Supply Voltage Range OUTPUT HARATERISTIS Δf/ΔT 0 o to 0 o ppm/ o %/V Square Wave Leakage urrent I OLK V 9 = 0V μa Saturation Voltage V SAT I SINK = ma V Rise Time t R R L = 4.kΩ ns Fall Time t F R L = 4.kΩ ns Typical Duty ycle Adjust (Note ) ΔD % Triangle/Sawtooth/Ramp - Amplitude V TRIAN- GLE R TRI = 0kΩ xv SUPPLY Linearity % Output Impedance Z OUT I OUT = 5mA Ω

3 IL0 Electrical Specifications V SUPPLY = ±V or +0V, T A = 5 o, R L = kω, Test ircuit Unless Otherwise Specified (ontinued) PARAMETER SYMBOL TEST ONDITIONS IL0 IL0B IL0A MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Sine Wave Amplitude V SINE R SINE = 0kΩ xv SUPPLY THD THD R S = MΩ (Note 4) % THD Adjusted THD Use Figure % NOTES:. and currents not included.. V SUPPLY = 0V; and = kω, f khz nominal; can be extended 00 to. See Figures 5A and 5B. 4. kω connected between pins and, Triangle Duty ycle set at 50%. (Use and.) 5. Figure, pins and connected, V SUPPLY = ±V. See Typical urves for T.. vs V SUPPLY.. Not tested, typical value for design purposes only. Test onditions PARAMETER R L SW MEASURE Supply urrent kω kω kω.nf losed urrent Into Pin Sweep FM Range (Note ) kω kω kω.nf Open Frequency at Pin 9 Frequency Drift with Temperature kω kω kω.nf losed Frequency at Pin Frequency Drift with Supply Voltage (Note ) kω kω kω.nf losed Frequency at Pin 9 Output Amplitude (Note ) Sine kω kω kω.nf losed Pk-Pk Output at Pin Triangle kω kω kω.nf losed Pk-Pk Output at Pin Leakage urrent (Off) (Note 9) kω kω.nf losed urrent into Pin 9 Saturation Voltage (On) (Note 9) kω kω.nf losed Output (Low) at Pin 9 Rise and Fall Times (Note ) kω kω 4.kΩ.nF losed Waveform at Pin 9 Duty ycle Adjust (Note ) Max 50kΩ ~.kω kω.nf losed Waveform at Pin 9 Min ~5kΩ 50kΩ kω.nf losed Waveform at Pin 9 Triangle Waveform Linearity kω kω kω.nf losed Waveform at Pin Total Harmonic Distortion kω kω kω.nf losed Waveform at Pin NOTES:. The hi and lo frequencies can be obtained by connecting pin to pin (f HI ) and then connecting pin to pin (f LO ). Otherwise apply Sweep Voltage at pin ( / V SUPPLY +V) V SWEEP V SUPPLY where V SUPPLY is the total supply voltage. In Figure 5B, pin should vary between 5.V and V with respect to ground.. V 0V, or ±5V V SUPPLY ±5V. 9. Oscillation can be halted by forcing pin to +5V or -5V.. Output Amplitude is tested under static conditions by forcing pin to 5V then to -5V.. Not tested; for design purposes only.

4 IL0 Test ircuit K K R L K +V SW N.. IL0 R TRI 00pF K R SINE -V Detailed Schematic URRENT SOURES FIGURE. TEST IRUIT R 0K Q Q Q Q 4 Q R K R Q 9K 9 Q 0 Q 4 Q R 0 Q Q R.K R 4 40K Q 5 Q 4 Q Q 5 Q Q 9 Q Q Q R EXT B 5 4 R 4 0 R 0 R.K R 4 K R 5 40 Q 9 R 5 0 FLIP-FLOP R EXT A Q Q R 0 Q Q Q 4 EXT R 4.K R 4.K 5K R 4 4K OMPARATOR Q 5 Q Q Q Q 0 Q Q 9 Q Q R 4 K Q 5 Q Q Q40 R 4 K R 4 K K R 5K R 9 5K R 5K Q9 R 44 K BUFFEMPLIFIER R 9 00 Q 45 R 0 Q 44.K Q R 4 Q 4 K Q 4 R 5 R K K R K Q 49 R Q 50 K Q 5 R.K R 4 00 Q 5 R 9 K Q 5 Q 54 SINE ONVERTER Q 4 Q 4 R K R 0 K Q 55 Q 4 Q 5 R 45 K R K R 5.K R 00 R 4 5 R 5 0 R 00 R 0 R 5 R 9 00 R 40 5.K R EXT K Application Information (See Functional Diagram) An external capacitor is charged and discharged by two current sources. urrent source # is switched on and off by a flip-flop, while current source # is on continuously. Assuming that the flip-flop is in a state such that current source # is off, and the capacitor is charged with a current I, the voltage across the capacitor rises linearly with time. When this voltage reaches the level of comparator # (set at / of the supply voltage), the flip-flop is triggered, changes states, and releases current source #. This current source normally carries a current I, thus the capacitor is discharged with a net-current I and the voltage across it drops linearly with time. When it has reached the level of comparator # (set at / of the supply voltage), the flip-flop is triggered into its original state and the cycle starts again. Four waveforms are readily obtainable from this basic generator circuit. With the current sources set at I and I respectively, the charge and discharge times are equal. Thus a triangle waveform is created across the capacitor and the flip-flop produces a square wave. Both waveforms are fed to buffer stages and are available at pins and 9. 4

5 IL0 The levels of the current sources can, however, be selected over a wide range with two external resistors. Therefore, with the two currents set at values different from I and I, an asymmetrical sawtooth appears at Terminal and pulses with a duty cycle from less than % to greater than 99% are available at Terminal 9. The sine wave is created by feeding the triangle wave into a nonlinear network (sine converter). This network provides a decreasing shunt impedance as the potential of the triangle moves toward the two extremes. Waveform Timing The symmetry of all waveforms can be adjusted with the external timing resistors. Two possible ways to accomplish this are shown in Figure. Best results are obtained by keeping the timing resistors and separate (A). controls the rising portion of the triangle and sine wave and the state of the square wave. The magnitude of the triangle waveform is set at / V SUPPLY ; therefore the rising portion of the triangle is, t V / V SUPPLY = = = I 0. V SUPPLY 0. The falling portion of the triangle and sine wave and the 0 state of the square wave is: V /V R R SUPPLY A B t = = ( 0.) V = V SUPPLY SUPPLY 0.( R B ) R A Thus a 50% duty cycle is achieved when =. If the duty cycle is to be varied over a small range about 50% only, the connection shown in Figure B is slightly more convenient. A kω potentiometer may not allow the duty cycle to be adjusted through 50% on all devices. If a 50% duty cycle is required, a kω or 5kΩ potentiometer should be used. With two separate timing resistors, the frequency is given by: f = = t + t or, if = = R 0. f = (for Figure A) R FIGURE A. SQUARE WAVE DUTY YLE - 50% FIGURE B. SQUARE WAVE DUTY YLE - 0% FIGURE. PHASE RELATIONSHIP OF WAVEFORMS R L kω R L IL0 IL0 K 0K V- OR GND FIGURE A. FIGURE B. FIGURE. POSSIBLE ONNETIONS FOR THE EXTERNAL TIMING RESISTORS V- OR GND 5

6 IL0 Neither time nor frequency are dependent on supply voltage, even though none of the voltages are regulated inside the integrated circuit. This is due to the fact that both currents and thresholds are direct, linear functions of the supply voltage and thus their effects cancel. Reducing Distortion To minimize sine wave distortion the kω resistor between pins and is best made variable. With this arrangement distortion of less than % is achievable. To reduce this even further, two potentiometers can be connected as shown in Figure 4; this configuration allows a typical reduction of sine wave distortion close to 0.5%. kω IL0 Selecting, and For any given output frequency, there is a wide range of R combinations that will work, however certain constraints are placed upon the magnitude of the charging current for optimum performance. At the low end, currents of less than μa are undesirable because circuit leakages will contribute significant errors at high temperatures. At higher currents (I > 5mA), transistor betas and saturation voltages will contribute increasingly larger errors. Optimum performance will, therefore, be obtained with charging currents of μa to ma. If pins and are shorted together, the magnitude of the charging current due to can be calculated from: R and R are shown in the Detailed Schematic. A similar calculation holds for. The capacitor value should be chosen at the upper end of its possible range. R L 0kΩ kω FIGURE 4. ONNETION TO AHIEVE MINIMUM SINE WAVE DISTORTION R ( V-) 0.( V-) I = = ( R + R ) kω 0kΩ V- OR GND Waveform Out Level ontrol and Power Supplies The waveform generator can be operated either from a single power supply (V to 0V) or a dual power supply (±5V to ±5V). With a single power supply the average levels of the triangle and sine wave are at exactly one-half of the supply voltage, while the square wave alternates between and ground. A split power supply has the advantage that all waveforms move symmetrically about ground. The square wave output is not committed. A load resistor can be connected to a different power supply, as long as the applied voltage remains within the breakdown capability of the waveform generator (0V). In this way, the square wave output can be made TTL compatible (load resistor connected to +5V) while the waveform generator itself is powered from a much higher voltage. Frequency Modulation and Sweeping The frequency of the waveform generator is a direct function of the D voltage at Terminal (measured from ). By altering this voltage, frequency modulation is performed. For small deviations (e.g. ±%) the modulating signal can be applied directly to pin, merely providing D decoupling with a capacitor as shown in Figure 5A. An external resistor between pins and is not necessary, but it can be used to increase input impedance from about kω (pins and connected together), to about (R + kω). For larger FM deviations or for frequency sweeping, the modulating signal is applied between the positive supply voltage and pin (Figure 5B). In this way the entire bias for the current sources is created by the modulating signal, and a very large (e.g. 00:) sweep range is created (f = Minimum at V SWEEP = 0, i.e., Pin = ). are must be taken, however, to regulate the supply voltage; in this configuration the charge current is no longer a function of the supply voltage (yet the trigger thresholds still are) and thus the frequency becomes dependent on the supply voltage. The potential on Pin may be swept down from by ( / V SUPPLY - V). FM R IL0 K R L V- OR GND FIGURE 5A. ONNETIONS FOR FREQUENY MODULATION

7 IL0 SWEEP VOLTAGE R L 5K IL0 IL0 N94 K N49 N94 STROBE V- OR GND FIGURE 5B. ONNETIONS FOR FREQUENY SWEEP FIGURE 5. -5V 0K OFF ON +5V (+V) -5V (-V) Typical Applications The sine wave output has a relatively high output impedance (kω Typ). The circuit of Figure provides buffering, gain and amplitude adjustment. A simple op amp follower could also be used. FIGURE. STROBE TONE BURST GENERATOR To obtain a 00: Sweep Range on the IL0 the voltage across external resistors and must decrease to nearly zero. This requires that the highest voltage on control Pin exceed the voltage at the top of and by a few hundred mv. The ircuit of Figure achieves this by using a diode to lower the effective supply voltage on the IL0. The large resistor on pin 5 helps reduce duty cycle variations with sweep. 4 5 IL0 AMPLITUDE + 0K K 0K The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as shown in Figure. N45 DUTY YLE +V V- 0.μF K 4.K 4.K 5K FIGURE. SINE WAVE OUTPUT BUFFEMPLIFIERS With a dual supply voltage the external capacitor on Pin can be shorted to ground to halt the IL0 oscillation. Figure shows a FET switch, diode ANDed with an input strobe signal to allow the output to always start on the same slope. K FREQ. IL0 0K 5M 0.004μF DISTORTION 0K -V FIGURE. VARIABLE AUDIO OSILLATOR, 0Hz TO 0kHzY

8 IL0 V + R FM BIAS DUTY YLE FREQUENY ADJUST 4 5 V + TRIANGLE OUT SQUARE WAVE OUT 9 IL0 SINE WAVE OUT INPUT VO IN PHASE DETETOR AMPLIFIER DEMODULATED FM R SINE WAVE ADJ. LOW PASS FILTER TIMING AP. SINE WAVE ADJ. V-/GND FIGURE 9. WAVEFORM GENERATOR USED AS STABLE VO IN A PHASE-LOKED LOOP HIGH FREQUENY SYMMETRY N5A (.V) kω 500Ω 4.kΩ 4.kΩ MΩ kω 0kΩ 0kΩ,000pF +5V LOW FREQUENY SYMMETRY V IN P4 kω OFFSET kω IL0 FUNTION GENERATOR 0kΩ + 50μF 5V - +5V 4 + SINE WAVE OUTPUT,900pF SINE WAVE DISTORTION -5V FIGURE. LINEAR VOLTAGE ONTROLLED OSILLATOR Use in Phase Locked Loops Its high frequency stability makes the IL0 an ideal building block for a phase locked loop as shown in Figure 9. In this application the remaining functional blocks, the phase detector and the amplifier, can be formed by a number of available Is (e.g., M444, NE5). In order to match these building blocks to each other, two steps must be taken. First, two different supply voltages are used and the square wave output is returned to the supply of the phase detector. This assures that the VO input voltage will not exceed the capabilities of the phase detector. If a smaller VO signal is required, a simple resistive voltage divider is connected between pin 9 of the waveform generator and the VO input of the phase detector. Second, the D output level of the amplifier must be made compatible to the D level required at the FM input of the waveform generator (pin, 0.). The simplest solution here is to provide a voltage divider to (R, R as shown) if the amplifier has a lower output level, or to ground if its level is higher. The divider can be made part of the low-pass filter. This application not only provides for a free-running frequency with very low temperature drift, but is also has the unique feature of producing a large reconstituted sinewave signal with a frequency identical to that at the input. For further information, see Intersil Application Note AN0, Everything You Always Wanted to Know About the IL0.

9 IL0 Definition of Terms Supply Voltage (V SUPPLY ). The total supply voltage from to V-. Supply urrent. The supply current required from the power supply to operate the device, excluding load currents and the currents through and. Frequency Range. The frequency range at the square wave output through which circuit operation is guaranteed. Sweep FM Range. The ratio of maximum frequency to minimum frequency which can be obtained by applying a sweep voltage to pin. For correct operation, the sweep voltage should be within the range: ( / V SUPPLY + V) < V SWEEP < V SUPPLY FM Linearity. The percentage deviation from the best fit straight line on the control voltage versus output frequency curve. Output Amplitude. The peak-to-peak signal amplitude appearing at the outputs. Saturation Voltage. The output voltage at the collector of Q when this transistor is turned on. It is measured for a sink current of ma. Rise and Fall Times. The time required for the square wave output to change from % to 90%, or 90% to %, of its final value. Triangle Waveform Linearity. The percentage deviation from the best fit straight line on the rising and falling triangle waveform. Total Harmonic Distortion. The total harmonic distortion at the sine wave output. Typical Performance urves 0.0 SUPPLY URRENT (ma) 5-55 o 5 o 5 o NORMALIZED FREQUENY SUPPLY VOLTAGE (V) FIGURE. SUPPLY URRENT vs SUPPLY VOLTAGE SUPPLY VOLTAGE (V) FIGURE. FREQUENY vs SUPPLY VOLTAGE.0 00 NORMALIZED FREQUENY V 0V V V 0V 0V TIME (ns) o 5 o -55 o RISE TIME FALL TIME 5 o 5 o -55 o TEMPERATURE ( o ) FIGURE. FREQUENY vs TEMPERATURE LOAD RESISTANE (kω) FIGURE 4. SQUARE WAVE OUTPUT RISE/FALL TIME vs LOAD RESISTANE 9

10 IL0 Typical Performance urves (ontinued) SATURATION VOLTAGE o 5 o -55 o NORMALIZED PEAK OUTPUT VOLTAGE LOAD URRENT TO V - LOAD URRENT TO 5 o 5 o -55 o LOAD URRENT (ma) LOAD URRENT (ma) FIGURE 5. SQUARE WAVE SATURATION VOLTAGE vs LOAD URRENT FIGURE. TRIANGLE WAVE OUTPUT VOLTAGE vs LOAD URRENT..0 NORMALIZED OUTPUT VOLTAGE LINEARITY (%) K K 0K M K K 0K M FREQUENY (Hz) FREQUENY (Hz) FIGURE. TRIANGLE WAVE OUTPUT VOLTAGE vs FREQUENY FIGURE. TRIANGLE WAVE LINEARITY vs FREQUENY. NORMALIZED OUTPUT VOLTAGE DISTORTION (%) 4 UNADJUSTED ADJUSTED 0 K K 0K M FREQUENY (Hz) FIGURE 9. SINE WAVE OUTPUT VOLTAGE vs FREQUENY 0 0 K K 0K M FREQUENY (Hz) FIGURE 0. SINE WAVE DISTORTION vs FREQUENY

11 IL0 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -- -A- N N/ B D e D E NOTES:. ontrolling Dimensions: INH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.5M-9.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDE seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.0 inch (0.5mm).. E and e A are measured with the leads constrained to be perpendicular to datum --.. e B and e are measured at the lead tips with the leads unconstrained. e must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.0 inch (0.5mm). 9. N is the maximum number of terminal positions.. orner leads (, N, N/ and N/ + ) for E., E., E., E., E4. will have a B dimension of inch (0. -.4mm). -B- A 0.0 (0.5) M A A L B S A e E L e A e B E4. (JEDE MS-00-AA ISSUE D) 4 LEAD DUAL-IN-LINE PLASTI PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B D D E E e 0.0 BS.54 BS - e A 0.00 BS. BS e B L N Rev. 0 /9

12 IL0 eramic Dual-In-Line Frit Seal Packages (ERDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b A - B A - B S D A A e D S NOTES:. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. orner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b. 5. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane.. Measure dimension S at all four corners.. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y4.5M ontrolling dimension: INH. E L M c ea/ S D S aaa M A - B LEAD FINISH BASE METAL b M (b) SETION A-A -D- -A- Q -- A -Bα S ea c D S (c) F4. MIL-STD-5 GDIP-T4 (D-, ONFIGURATION A) 4 LEAD ERAMI DUAL-IN-LINE FRIT SEAL PAKAGE INHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e 0.0 BS.54 BS - ea 0.00 BS. BS - ea/ 0.50 BS. BS - L Q S α 90 o 5 o 90 o 5 o - aaa bbb ccc M , N 4 4 Rev. 0 4/94 All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil orporation s quality certifications can be viewed at website Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see web site Sales Office Headquarters NORTH AMERIA Intersil orporation 40 Palm Bay Rd., Mail Stop 5-04 Palm Bay, FL 905 TEL: () FAX: () 4-40 EUROPE Intersil SA Mercure enter 0, Rue de la Fusee 0 Brussels, Belgium TEL: ().4. FAX: () ASIA Intersil Ltd. F-, 9, Sec., hien-kuo North, Taipei, Taiwan 4 Republic of hina TEL: FAX: