CA3420. Features. 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifier. Applications. Functional Diagram. Ordering Information

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1 CA Data Sheet October, FN.9.MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifier The CA is an integrated circuit operational amplifier that combines PMOS transistors and bipolar transistors on a single monolithic chip. The CA BiMOS operational amplifier features gate protected PMOS transistors in the input circuit to provide very high input impedance, very low input currents (less than pa). The internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leakage current for every C increase in temperature. The CA operates at total supply voltages from V to V either single or dual supply. This operational amplifier is internally phase compensated to achieve stable operation in the unity gain follower configuration. Additionally, it has access terminals for a supplementary external capacitor if additional frequency rolloff is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common mode input voltage capability down to.v below the negative supply terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that can swing essentially from railtorail. The output driving current of.ma (Min) is provided by using nonlinear current mirrors. Features V Supply at µa Supply Current pa Input Current (Typ) (Essentially Constant to 8 C) RailtoRail Output Swing (Drive ±ma into kω Load) Pin Compatible with Operational Amplifiers PbFree Plus Anneal Available (RoHS Compliant) Applications ph Probe Amplifiers Picoammeters Electrometer (High Z) Instruments Portable Equipment Inaccessible Field Equipment BatteryDependent Equipment (Medical and Military) Functional Diagram X Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # CAE CAE to 8 Ld PDIP E8. MOS BIPOLAR MOS BIPOLAR CAEZ (Note) CAEZ to 8 Ld PDIP* (Pbfree) E8. X *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD. BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK Pinout HIGH GAIN (K) CA (PDIP) TOP VIEW OTA BUFFER (X) OFFSET NULL 8 STROBE INV. INPUT V NONINV. INPUT 6 OUTPUT V OFFSET NULL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.,. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 CA Absolute Maximum Ratings Supply Voltage (V to V) V Differential Input Voltage V DC Input Voltage (V 8V) to (V.V) Input Current ma Output Short Circuit Duration (Note ) Indefinite Operating Conditions Temperature Range C to C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( C/W) θ JC ( C/W) PDIP Package* N/A Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to C Maximum Lead Temperature (Soldering s) C *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Short circuit may be applied to ground or to either supply.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Typical Values Intended Only for Design Guidance, V SUPPLY = ±V, T A = C PARAMETER SYMBOL TEST CONDITIONS TYP UNITS Input Resistance R I TΩ Input Capacitance C I.9 pf Output Resistance R O Ω Equivalent Input Noise Voltage e N f = khz R S = Ω 6 nv/ Hz f = khz 8 nv/ Hz ShortCircuit Current Source I OM.6 ma To Opposite Supply Sink I OM. ma Gain Bandwidth Product f T. MHz Slew Rate SR. V/µs Transient Response Rise Time t R R L = kω, C L = pf. µs Overshoot OS % Current from Terminal 8 To V I 8 µa To V I 8 ma Electrical Specifications For Equipment Design, At V SUPPLY = ±V, T A = C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage V IO mv Input Offset Current (Note ) I IO. pa Input Current (Note ) I I pa Large Signal Voltage Gain A OL R L = kω kv/v 8 db Common Mode Rejection Ratio CMRR 6 8 µv/v 6 db Common Mode Input Voltage Range V lcr.. V V lcr. V Power Supply Rejection Ratio PSRR V IO / V µv/v 6 8 db Max Output Voltage V OM R L =.9.9 V V OM.8.9 V Supply Current I 6 µa Device Dissipation P D.. mw Input Offset Voltage Temperature Drift V lo / T µv/ C NOTE:. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. FN.9 October,

3 CA Electrical Specifications For Equipment Design, at V SUPPLY = ±V, T A = C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage V IO mv Input Offset Current (Note ) I IO. pa Input Current (Note ) I I. pa Large Signal Voltage Gain A OL R L = kω kv/v 8 db Common Mode Rejection Ratio CMRR µv/v 8 db Common Mode Input Voltage Range V lcr V V lcr. V Power Supply Rejection Ratio PSRR V IO / V µv/v 9 db Max Output Voltage V OM R L = V V OM V Supply Current I µa Device Dissipation P D 9 mw Input Offset Voltage Temperature Drift V lo / T µv/ C NOTE:. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. Typical Applications Picoammeter Circuit The exceptionally low input current (typically.pa) makes the CA highly suited for use in a picoammeter circuit. With only a single GΩ resistor, this circuit covers the range from ±.pa. Higher current ranges are possible with suitable switching techniques and current scaling resistors. Input transient protection is provided by the MΩ resistor in series with the input. Higher current ranges require that this resistor be reduced. The MΩ resistor connected to pin of the CA decouples the potentially high input capacitance often associated with lower current circuits and reduces the tendency for the circuit to oscillate under these conditions. High Input Resistance Voltmeter Advantage is taken of the high input impedance of the CA in a high input resistance DC voltmeter. Only two.v AA type penlite batteries power this exceedingly highinput resistance (>,,MΩ) DC voltmeter. Fullscale deflection is ±mv, ±mv, and ±mv. Higher voltage ranges are easily added with external input voltage attenuator networks. The meter is placed in series with the gain network, thus eliminating the meter temperature coefficient error term. Supply current in the standby position with the meter undeflected is µa. At fullscale deflection this current rises to 8µA. Carbonzinc battery life should be in excess of, hours. MΩ MΩ GΩ MΩ pf kω CA.V BATTERY RETURNS.V µa 6 M ±pa ±pa ±pa ±.pa kω FIGURE. PICOAMMETER CIRCUIT MΩ pf kω CA.V BATTERY RETURNS.V µa 6 M ±mv ±mv ±mv ±mv.kω.kω.kω, % kω Ω, % Ω, % 68Ω %.kω.kω, % kω Ω, % Ω, % 68Ω % FIGURE. HIGH INPUT RESISTANCE VOLTMETER FN.9 October,

4 CA Typical Performance Curves INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V) T A = C R L = kω SUPPLY VOLTAGE (V) V O V O V ICR V ICR FIGURE. OUTPUT VOLTAGE SWING AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q 9 (mv). T A = C V = V V = V V = V V = V V = V. LOAD (SOURCING) CURRENT (ma) FIGURE. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT OUTPUT STAGE TRANSISTOR SATURATION VOLTAGE, Q (mv). T A = C V = V V = V V = V V = V V = V. LOAD (SINKING) CURRENT (ma) FIGURE. OUTPUT VOLTAGE vs LOAD SINKING CURRENT EQUIVALENT INPUT NOISE VOLTAGE (nv/ Hz) V S = ±V V S = ±V V S = ±V FREQUENCY (Hz) T A = C FIGURE 6. INPUT NOISE VOLTAGE vs FREQUENCY 6 OPEN LOOP VOLTAGE GAIN (db) 8 6 T A = C V S = ±V R L = kω C L = pf 9 8 OPEN LOOP PHASE (DEGREES) FREQUENCY (Hz) 6 FIGURE. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE FN.9 October,

5 CA DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B C A N N/ B D e D E B A. (.) M C A A L B S NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum C.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E8., E6., E8., E8., E.6 will have a B dimension of.. inch (.6.mm). A e C E C L e A C e B E8. (JEDEC MSBA ISSUE D) 8 LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A.. A..9 A B B.... 8, C.8... D D.. E E e. BSC. BSC e A. BSC.6 BSC 6 e B..9 L N Rev. /9 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN.9 October,

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