LC 2 MOS 8-/16-Channel High Performance Analog Multiplexers ADG406/ADG407/ADG426

Transcription

1 LC 2 MOS 8-/16-Channel High Performance Analog Multiplexers AG406/AG407/AG426 FEATURES 44 V supply maximum ratings VSS to V analog signal range Low on resistance (80 Ω maximum) Low power Fast switching ton < 160 ns toff < 150 ns Break-before-make switching action APPLICATIONS Audio and video routing Automatic test equipment ata acquisition systems Battery powered systems Sample hold systems Communication systems Avionics PROUCT HIGHLIGHTS 1. Extended Signal Range. 2. The AG406/AG407/AG426 are fabricated on an enhanced LC 2 MOS process giving an increased signal range which extends to the supply rails. 3. Low Power issipation. 4. Low RON. 5. Single/ual Supply Operation. 6. Single Supply Operation. 7. For applications where the analog signal is unipolar, the AG406/AG407/AG426 can be operated from a single rail power supply. The parts are fully specified with a single +12 V power supply and remain functional with single supplies as low as +5 V. FUNCTIONAL BLOCK IAGRAMS 6 A S8A B S8B AG406 1 OF 16 ECOER A0 A1 A2 A3 Figure 1. AG407 1 OF 8 ECOER A0 A1 A2 Figure 2. AG A B WR ECOER/ LATCHES A0 A1 A2 A3 Figure Rev. B Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Fax: Analog evices, Inc. All rights reserved.

2 TABLE OF CONTTS Features... 1 Applications... 1 Product Highlights... 1 Functional Block iagrams... 1 Revision History... 2 General escription... 3 Specifications... 4 ual Supply... 4 Single Supply... 6 AG426 Timing iagrams...7 Absolute Maximum Ratings...8 ES Caution...8 Pin Configurations and Function escriptions...9 Typical Performance Characteristics Test Circuits Terminology Outline imensions Ordering Guide REVISION HISTORY 5/10 Rev. A to Rev. B Changes to Ordering Guide /09 Rev. 0 to Rev. A Updated Format... Universal Removed T Grade... Universal Added Table Added Table Added Table Updated Outline imensions Changes to Ordering Guide /94 Revision 0: Initial Version Rev. B Page 2 of 20

3 GERAL ESCRIPTION The AG406, AG407, and AG426 are monolithic CMOS analog multiplexers. The AG406 and AG426 switch one of sixteen inputs to a common output as determined by the 4-bit binary address lines: A0, A1, A2, and A3. The AG426 has on-chip address and control latches that facilitate microprocessor interfacing. The AG407 switches one of eight differential inputs to a common differential output as determined by the 3-bit binary address lines A0, A1 and A2. An input on all devices is used to enable or disable the device. When disabled, all channels are switched off. The AG406/AG407/AG426 are designed on an enhanced LC 2 MOS process that provides low power dissipation yet gives high switching speed and low on resistance. These features make the parts suitable for high speed data acquisition systems and audio signal switching. Low power dissipation makes the parts suitable for battery powered systems. Each channel conducts equally well in both directions when on and has an input signal range which extends to the supplies. In the off condition, signal levels up to the supplies are blocked. All channels exhibit breakbefore-make switching action preventing momentary shorting when switching channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs. Rev. B Page 3 of 20

4 SPECIFICATIONS UAL SUPPLY V = +15 V ± 10%, VSS = 15 V ± 10%, GN = 0 V, unless otherwise noted. Table 1. Parameter C 40 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range VSS to V V RON 50 Ω typ V = ±10 V, IS = 1 ma Ω max V = V, VSS = 13.5 V RON Match 4 Ω typ V = 0 V, IS = 1 ma LEAKAGE CURRTS V = V, VSS = 16.5 V Source Off Leakage IS (Off) ±0.5 ±20 na max V = ±10 V, VS = +10 V, see Figure 26 rain Off Leakage I (Off) V = ±10 V, VS = +10 V; see Figure 27 AG406, AG426 ±1 ±20 na max AG407 ±1 ±20 na max Channel On Leakage I, IS (On) VS = V = ±10 V; see Figure 28 AG406, AG426 ±1 ±20 na max AG407 ±1 ±20 na max IGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH ±1 μa max VIN = 0 or V CIN, igital Input Capacitance 8 pf typ f = 1 MHz YNAMIC CHARACTERISTICS 2 ttransition 120 ns typ RL = 300 Ω, CL = 35 pf; V1 = ±10 V, V2 = +10 V; see Figure ns max Break Before Make elay, top ns min RL = 300 Ω, CL = 35 pf; VS = +5 V, see Figure 30 ton (, WR) ns typ RL = 300 Ω, CL = 35 pf; VS = 5 V, see Figure ns max toff (, ) ns typ RL = 300 Ω, CL = 35 pf; VS = 5 V, see Figure ns max AG426 Only tw, Write Pulse Width 100 ns min ts, Address, Enable Setup Time 100 ns min th, Address, Enable Hold Time 10 ns min t, Reset Pulse Width 100 ns min VS = +5 V Charge Injection 8 pc typ VS = 0 V, = 0 Ω, CL = 1 nf; See Figure 34 Off Isolation 75 db typ RL = 1 k Ω, f = 100 khz; V = 0 V, see Figure 35 Channel-to-Channel Crosstalk 85 db typ RL = 1 k Ω, f = 100 khz, see Figure 36 CS (Off) 5 pf typ f = 1 MHz C (Off) f = 1 MHz AG406, AG pf typ AG pf typ C, CS (On) f = 1 MHz AG406, AG pf typ AG pf typ Rev. B Page 4 of 20

5 Parameter C 40 C to +85 C Unit Test Conditions/Comments POWER REQUIREMTS V = V, VSS = 16.5 V I 1 μa typ VIN = 0 V, V = 0 V 5 μa max ISS 1 μa typ 5 μa max I 100 μa typ VIN = 0 V, V = 2.4 V μa max ISS 1 μa typ 5 μa max 1 Temperature ranges is 40 C to +85 C. 2 Guaranteed by design, not subject to production test. Rev. B Page 5 of 20

6 SINGLE SUPPLY V = +12 V ± 10%, VSS = 0 V, GN = 0 V, unless otherwise noted. Table 2. Parameter C 40 C to +85 C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 to V V RON 90 Ω typ V = +3 V, +8.5 V, IS = 1 ma; Ω max V = V LEAKAGE CURRTS V = V Source Off Leakage IS (Off) ±0.5 ±20 na max V = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 26 rain Off Leakage I (Off) V = 8 V/0.1 V, VS = 0.1 V/8 V; see Figure 27 AG406, AG426 ±1 ±20 na max AG407 ±1 ±20 na max Channel On Leakage I, IS (On) VS = V = 8 V/0.1 V, see Figure 28 AG406, AG426 ±1 ±20 na max AG407 ±1 ±20 na max IGITAL INPUTS Input High Voltage, VINH 2.4 V min Input Low Voltage, VINL 0.8 V max Input Current IINL or IINH ±1 μa max VIN = 0 or V CIN, igital Input Capacitance 8 pf typ f = 1 MHz YNAMIC CHARACTERISTICS 2 ttransition 180 ns typ RL = 300 Ω, CL = 35 pf; V1 = 8 V/0 V, V2 = 0 V/8 V; see Figure ns max Break Before Make elay, top 10 ns typ RL = 300 Ω, CL = 35 pf; VS = 5 V, see Figure 30 ton (, WR) 180 ns typ RL = 300 Ω, CL = 35 pf; ns max VS = +5 V, see Figure 31 toff (, ) 135 ns typ RL = 300 Ω, CL = 35 pf; VS = 5 V, see Figure ns max AG426 Only tw, Write Pulse Width 100 ns min ts, Address, Enable Setup Time 100 ns min th, Address, Enable Hold Time 10 ns min t, Reset Pulse Width 100 ns min VS = +5 V Charge Injection 5 pc typ VS = 6 V, = 0 Ω, CL = 1 nf; see Figure 34 Off Isolation 75 db typ RL = 1 kω, f = 100 khz; see Figure 35 Channel-to-Channel Crosstalk 85 db typ RL = 1 kω, f = 100 khz; see Figure 36 CS (Off) 8 pf typ f = 1 MHz C (Off) f = 1 MHz AG406, AG pf typ AG pf typ f = 1 MHz C, CS (On) AG406, AG pf typ AG pf typ POWER REQUIREMTS V = V I 1 μa typ VIN = 0 V, V = 0 V 5 μa max I 100 μa typ VIN = 0 V, V = 2.4 V μa max 1 Temperature range is 40 C to +85 C. 2 Guaranteed by design, not subject to production test. Rev. B Page 6 of 20

7 AG426 TIMING IAGRAMS 3V WR 50% 50% 0V t W 3V 0V 50% 50% t W 3V A0, A1, A2, (A3) 0V 2V t S t H 0.8V Figure 4. Timing Sequence for Latching the Switch Address and Enable Inputs Figure 4 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR SWITCH OUTPUT 0V t OFF () V 0 0.8V 0 Figure 5. Reset Pulse Width and Reset Turn Off Time Figure 5 shows the reset pulse width, trs, and the reset turn off time, toff (). Note that all digital input signals rise and fall times are measured from 10% to 90% of 3 V; tr = tf = 20 ns Rev. B Page 7 of 20

8 ABSOLUTE MAXIMUM RATINGS TA = 25 C unless otherwise noted. Table 3. Parameter Rating V to VSS 44 V V to GN 0.3 V to +25 V VSS to GN +0.3 V to 25 V Analog, igital Inputs 1 VSS 2 V to V + 2 V or 20 ma, whichever occurs first Continuous Current, S or 20 ma Peak Current, S or 40 ma (Pulsed at 1 ms, 10% duty cycle max) Operating Temperature Range Industrial (B Version) 40 C to +85 C Storage Temperature Range 65 C to +150 C Junction Temperature 150 C Plastic Package θja, Thermal Impedance 75 C/W Lead Temperature, Soldering 260 C (10 sec) PLCC Package θja, Thermal Impedance 80 C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215 C Infrared (15 sec) 220 C SSOP Package θja, Thermal Impedance 122 C/W Lead Temperature, Soldering Vapor Phase (60 sec) 215 C Infrared (15 sec) 220 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ES CAUTION 1 Overvoltages at A, S,, WR, or will be clamped by internal diodes. Current should be limited to the maximum ratings given. Rev. B Page 8 of 20

9 PIN CONFIGURATIONS AN FUNCTION ESCRIPTIONS 1 NC 2 NC S9 11 GN 12 NC 13 A3 14 AG406 TOP VIEW (Not to Scale) S8 25 S7 24 S6 23 S5 22 S4 21 S3 20 S A0 16 A1 15 A2 NC = NO CONNECT Figure Lead PIP S NC NC S PIN 1 INTFIER AG406 TOP VIEW (Not to scale) GN NC A3 A2 A1 A0 NC = NO CONNECT Figure Lead PLCC S7 S6 S5 S4 S3 S Table 4. Pin Function escriptions Pin No. Mnemonic escription 1 V Most Positive Power Supply Potential. 2, 3, 13 NC No Connect. 4 to 11 6 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. 12 GN Ground (0 V) Reference. 14 to 17 A3 to A0 Logic Control Input. 18 Active High igital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 to 8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. 27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 rain Terminal. This pin can be an input or an output. Table 5. Truth Table (AG406) A3 A2 A1 A0 On Switch X X X X 0 None Rev. B Page 9 of 20

10 1 B 2 NC 3 S8B 4 S7B 5 S6B 6 28 A S8A 25 S7A 24 S6A 23 S5A S5B 7 (Not to Scale) 22 S4A S4B 8 21 S3A S3B 9 20 S2A S2B 10 B 11 GN 12 NC 13 NC 14 AG407 TOP VIEW NC = NO CONNECT 19 A A0 16 A1 15 A2 Figure Lead PIP S7B S6B S5B S4B S3B S2B B S8B NC B A S8A PIN 1 INTFIER AG407 TOP VIEW (Not to scale) GN NC NC A2 A1 A0 NC = NO CONNECT Figure Lead PLCC S7A S6A S5A S4A S3A S2A A Table 6. Pin Function escriptions Pin No. Mnemonic escription 1 V Most Positive Power Supply Potential. 2 B rain Terminal B. This pin can be an input or an output. 3, 13, 14 NC No Connect. 4 to 11 S8B to B Source Terminal 8B to Source Terminal 1B. These pins can be inputs or outputs. 12 GN Ground (0 V) Reference. 15 to 17 A2 to A0 Logic Control Input. 18 Active High igital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 A to S8A Source Terminal 1A to Source Terminal 8A. These pins can be inputs or outputs. 27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 A rain Terminal A. This pin can be an input or an output. Table 7. Truth Table (AG407) A2 A1 A0 On Switch Pair X X X 0 None Rev. B Page 10 of 20

11 1 NC S8 25 S S6 AG S5 TOP VIEW (Not to Scale) S S S S9 11 GN 12 WR 13 A3 14 NC = NO CONNECT A0 16 A1 15 A2 Figure Lead PIP/SSOP Table 8. Pin Function escriptions Pin No. Mnemonic escription 1 V Most Positive Power Supply Potential. 2 NC No Connect. 3 Active Low Logic Input. When this pin is low, all switches are open, and address and enable latches registers are cleared to 0. 4 to 11 6 to S9 Source Terminal 16 to Source Terminal 9. These pins can be inputs or outputs. 12 GN Ground (0 V) Reference. 13 WR The rising edge of the WR signal latches the state of the address control lines and the enable line. 14 to 17 A3 to A0 Logic Control Input. 18 Active High igital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the Ax logic inputs determine which switch is turned on. 19 to 26 to S8 Source Terminal 1 to Source Terminal 8. These pins can be inputs or outputs. 27 VSS Most Negative Power Supply Potential. In single-supply applications, this pin can be connected to ground. 28 rain Terminal. This pin can be an input or an output. Table 9. Truth Table (AG426) A3 A2 A1 A0 WR On switch X X X X X 1 Retains previous switch condition X X X X X X 0 None (address and enable latches cleared) X X X X None Rev. B Page 11 of 20

12 TYPICAL PERFORMANCE CHARACTERISTICS = +5V = 5V T A = 25 C = +5V =0V T A = 25 C R ON (Ω) = +10V = 10V = +15V = 15V = +12V = 12V R ON (Ω) = +15V = 0V = +10V =0V = +12V =0V V (V S ) (V) V (V S ) (V) Figure 11. RON as a Function of V (VS): ual Supplies Figure 14. RON as a Function of V (VS): Single Supplies 100 = +15V = 15V 150 = 12V =0V R ON (Ω) C 25 C 125 C R ON (Ω) C 25 C 125 C LEAKAGE CURRT (na) V (V S ) (V) Figure 12. RON as a Function of V (VS) for ifferent Temperatures = +15V = 15V T A =+25 C V (V S ) (V) I S (OFF) I (ON) I (OFF) Figure 13. Leakage Currents as a Function of V (VS) LEAKAGE CURRT (na) V (V S ) (V) Figure 15. RON as a Function of V (VS) for ifferent Temperatures = +12V =0V T A =+25 C I S (OFF) I (OFF) I (ON) V (V S ) (V) Figure 16. Leakage Currents as a Function of V (VS) Rev. B Page 12 of 20

13 100 = +15V = 15V = +15V = 15V 10 1 I (ma) = 2.4V I SS (ma) 0.1 = 2.4V = 0V k 10k 100k 1M 10M FREQUCY (Hz) = 0V Figure 17. Positive Supply Current vs. Switching Frequency k 10k 100k 1M 10M FREQUCY (Hz) Figure 20. Negative Supply Current vs. Switching Frequency t ON = +15V = 15V t ON = +12V =0V 180 t TRANSITION t (ns) t TRANSITION t (ns) t OFF V IN (V) Figure 18. Switching Time vs. VIN (Bipolar Supply) t OFF V IN (V) Figure 21. Switching Time vs. VIN (Single Supply) V IN = +5V V IN = +5V 400 t TRANSITION 200 t ON 300 t (ns) t ON t (ns) 100 t TRANSITION 200 t OFF t OFF ±5 ±7 ±9 ±11 ±13 ±15 ±17 ±19 ±21 SUPPLY VOLTAGE (V) Figure 19. Switching Time vs. Bipolar Supply SUPPLY VOLTAGE (V) Figure 22. Switching Time vs. Single Supply Rev. B Page 13 of 20

14 140 = +15V = 15V 140 = +15V = 15V OFF ISOLATION (db) CROSSTALK (db) k 10k 100k 1M 10M k 10k 100k 1M 10M FREQUCY (Hz) Figure 23. Off Isolation vs. Frequency FREQUCY (Hz) Figure 24. Crosstalk vs. Frequency Rev. B Page 14 of 20

15 TEST CIRCUITS I S V S S V1 R ON = V1/I S V S S2 6 I (OFF) A +0.8V V Figure 25. On Resistance Figure 27. I (Off) I S (OFF) A S2 I (ON) A V S V 6 Figure 26. IS (Off) +0.8V V S 6 Figure 28. I (On) +2.4V V V V IN 50Ω A3 A2 S2 THRU 5 A1 6 A0 AG V GN WR 1 SIMILAR CONNECTION FOR AG406/AG407 V 1 V 2 R L 300Ω C L 35pF V OUT ARESS RIVE (V IN ) V OUT t TRANSITION 50% 50% 90% 90% t TRANSITION Figure 29. Switching Time of Multiplexer, ttransition 3V V IN 50Ω 2.4V A3 A2 S2 THRU 5 A1 6 A0 AG426 1 GN WR R L 300Ω V S C L 35pF ARESS RIVE (V IN ) V OUT OUTPUT 0V 80% 80% 1 SIMILAR CONNECTION FOR AG406/AG407 t OP Figure 30. Break-Before-Make elay, top Rev. B Page 15 of 20

16 V IN 2.4V 50Ω A3 A2 S2 THRU 6 A1 A0 AG426 1 GN WR V S R L 300Ω 3V ABLE RIVE (V IN ) 50% 50% 0V V O V OUT OUTPUT C L 90% 90% 35pF 0V t OFF () 1 SIMILAR CONNECTION FOR AG406/AG407 t ON () Figure 31. Enable elay, ton (), toff () A3 A2 S2 THRU 6 A1 A0 AG426 V S 3V WR 0V V 0 50% 2.4V V WR GN R L 300Ω C L 35pF V OUT OUTPUT 0V t ON (WR) 0.2V 0 V WR Figure 32. Write Turn-On Time, ton (WR) V V IN A3 A2 S2 THRU 6 A1 A0 AG426 GN WR V S R L 300Ω C L 35pF V OUT 3V 0V V 0 OUTPUT 0V 50% t OFF () 0.8V Figure 33. Reset Turn-Off Time, toff () Rev. B Page 16 of 20

17 V S R S V IN A3 A2 A1 A0 AG426 1 S GN WR 2.4V C L 1nF V OUT 3V LOGIC INPUT (V IN ) V OUT Q INJ = C L ΔV OUT ΔV OUT 1 SIMILAR CONNECTION FOR AG406/AG407. Figure 34. Charge Injection V A3 A2 A1 A0 6 AG426 1 GN WR R L 1kΩ V IN V OUT V IN 2.4V 1kΩ S2 A0 A1 AG426 1 A2 A3 GN WR 1kΩ V OUT 1 SIMILAR CONNECTION FOR AG406/AG SIMILAR CONNECTION FOR AG406/AG Figure 35. Off Isolation Figure 36. Crosstalk Rev. B Page 17 of 20

18 TERMINOLOGY V Most positive power supply potential. VSS Most negative power supply potential in dual supplies. In single supply applications, it may be connected to ground. GN Ground (0 V) reference. RON Ohmic resistance between the and S terminals. RON Match ifference between the RON of any two channels. IS (Off) Source leakage current when the switch is off. I (Off) rain leakage current when the switch is off. I, IS (On) Channel leakage current when the switch is on. V (VS) Analog voltage on Terminal, Terminal S. CS (Off) Channel input capacitance for off condition. C (Off) Channel output capacitance for off condition. C, CS (ON) On switch capacitance. CIN igital input capacitance. ton () elay time between the 50% and 90% points of the digital input and switch on condition. toff () elay time between the 50% and 90% points of the digital input and switch off condition. ttransition elay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. top Off time measured between 80% points of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. I Positive supply current. ISS Negative supply current. Rev. B Page 18 of 20

19 OUTLINE IMSIONS (39.75) (35.05) (14.73) (12.31) (6.35) MAX (5.08) (2.92) (0.56) (0.36) (2.54) BSC (1.78) (1.27) (0.38) GAUGE PLANE (0.38) MIN SEATING PLANE (0.13) MIN (15.88) (15.24) (17.78) MAX (4.95) (3.17) (0.38) (0.20) COMPLIANT TO JEEC STANA MS-011 CONTROLLING IMSIONS ARE IN INCHES; MILLIMETER IMSIONS (IN PARTHESES) ARE ROUNE-OFF INCH EQUIVALTS FOR REFERCE ONLY AN ARE NOT APPROPRIATE FOR USE IN ESIGN. CORNER LEAS MAY BE CONFIGURE AS WHOLE LEAS. Figure Lead Plastic ual In-Line Package {PIP} Wide Body (N-28-2) imensions shown in inches and (millimeters) A (1.22) (1.07) (1.22) (1.07) PIN 1 ITIFIER TOP VIEW (PINS OWN) (11.582) SQ (11.430) (12.57) (12.32) SQ (1.42) (1.07) (1.27) BSC (3.04) (2.29) (4.57) (4.19) (0.51) MIN (0.53) (0.33) (0.81) (0.66) (1.14) (0.64) R (10.92) (9.91) BOTTOM VIEW (PINS UP) COMPLIANT TO JEEC STANA MO-047-AB CONTROLLING IMSIONS ARE IN INCHES; MILLIMETER IMSIONS (IN PARTHESES) ARE ROUNE-OFF INCH EQUIVALTS FOR REFERCE ONLY AN ARE NOT APPROPRIATE FOR USE IN ESIGN. Figure Lead Plastic Leaded Chip Carrier [PLCC] (P-28) imensions shown in inches and (millimeters) A Rev. B Page 19 of 20

20 MAX MIN COPLANARITY BSC SEATING PLANE COMPLIANT TO JEEC STANA MO-150-AH Figure Lead Shrink Small Outline Package [SSOP] (-28) imensions shown in millimeters A ORERING GUIE Model 1 Temperature Range Package escription Package Option 2 AG406BN 40 C to +85 C 28-Lead PIP N-28-2 AG406BNZ 40 C to +85 C 28-Lead PIP N-28-2 AG406BP 40 C to +85 C 28-Lead PLCC P-28 AG406BP-REEL 40 C to +85 C 28-Lead PLCC P-28 AG406BPZ 40 C to +85 C 28-Lead PLCC P-28 AG406BPZ-REEL 40 C to +85 C 28-Lead PLCC P-28 AG407BN 40 C to +85 C 28-Lead PIP N-28-2 AG407BNZ 40 C to +85 C 28-Lead PIP N-28-2 AG407BP 40 C to +85 C 28-Lead PLCC P-28 AG407BP-REEL 40 C to +85 C 28-Lead PLCC P-28 AG407BPZ 40 C to +85 C 28-Lead PLCC P-28 AG407BPZ-RL 40 C to +85 C 28-Lead PLCC P-28 AG407BCHIPS 40 C to +85 C IE AG426BN 40 C to +85 C 28-Lead PIP N-28-2 AG426BNZ 40 C to +85 C 28-Lead PIP N-28-2 AG426B 40 C to +85 C 28-Lead SSOP -28 AG426B-REEL 40 C to +85 C 28-Lead SSOP -28 AG426B-REEL7 40 C to +85 C 28-Lead SSOP -28 AG426BZ 40 C to +85 C 28-Lead SSOP -28 AG426BZ-REEL 40 C to +85 C 28-Lead SSOP Z = RoHS Compliant Part. 2 N = Plastic IP, P = Plastic Leaded Chip Carrier (PLCC), = Shrink Small Outline Package (SSOP) Analog evices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners /10(B) Rev. B Page 20 of 20