Efficient Big Data Analytics Computing: A Research Challenge

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1 Efficient Big Data Analytics Computing: A Research Challenge Wilfred Pinfold Director, Extreme Scale Programs 1

2 Agenda Intel Big Data Context Overview Key Research Areas Challenges Partnerships 2

3 Meeting Today s Big Data Challenges Optimize for performance Performance Challenges Performance/$ Performance/Watt Performance/Sq. ft Versatile, scalable solutions to enable innovation 3

4 The Future Looks Bright 10nm 14nm 22nm 45nm 32nm Breakthrough technology year after year 4

5 Agenda Intel Big Data Context Overview Key Research Areas Challenges Partnerships 5

6 Investing Through the Recession 10 year total = $51.2B 10 year total = $51.8B Capital Additions to Property, Plant and Equipment (Dollars in Billions) Research and Development (Dollars in Billions)

7 Mission To fuel Intel s growth, we deliver breakthrough technologies that bring the benefits of the ongoing digital revolution to everyone. 7 kp

8 : Broad Agenda People and Practices Eco Innovation & Energy Efficiency Immersive Connected Experiences Trust and Privacy Si Photonics Enterprise and Cloud Mobility and Communications Terascale to Exascale Health and DNA Sequencing Everyday Sensing and Perception And much more. 8

9 Agenda Intel Big Data Context Overview Key Research Areas Challenges Partnerships 9

10 Research Programs PRODUCT ROADMAPS Technology Transfer prototype Advanced Development Proof of Concept Applied Research Intel Concept VT Concept Concept Exploratory Research Program I Program II Program III 10

11 Logic Energy/Transistor (Relative) 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 Power reduction Over Time* 1.E Core Integer Performance Over Time* Pentium 4 Processor EE Pentium 4 Processor Pentium -IIi Processor Pentium -II Processor Pentium Pro Processor Pentium Processor i486dx2 i486 Core 2 Duo Extreme QX6700 Core 2 Duo Processor X6800 Pentium -D Processor Single Core Moore s Law ~ 1 Million Factor Reduction In Energy/Transistor Over 30+ Years 11

12 Memory Enabling Large Capacity Last Level Cache (MB) Source: Intel 12

13 Storage 13

14 Enterprise Energy Management Instrument and visualize Real-time sensing Measure and control Weather Map modeling Integrate with ecosystem Console management Sensors, location Automation: policies, models Thermally-aware load balancing Unused capacity in sleep Reduce cooling costs 14

15 Agenda Intel Big Data Context Overview Key Research Areas Challenges Partnerships 15

16 Power Improvements Require Discontinuity Other Compute 10 Disk 1 Today UHPC Memory Interconnect 16

17 Technical Risk and Market Risk 1985: IA-32, : Native 32 bit support Windows 95 Option Analysis 17

18 Device Power Operations/Unit Energy Low Operating Power Devices High Performance Devices Based on ITRS roadmap logic device projections from the ExaScale Computing Study: Technology Challenges in Achieving Exascale Systems September 28,

19 Near Threshold Logic Maximum Frequency (MHz) nm CMOS, 50 C 320mV Supply Voltage (V) Total Power (mw) Energy Efficiency (GOPS/Watt) nm CMOS, 50 C X mV Supply Voltage (V) Subthreshold Region H. Kaul et al, 16.6: ISSCC08 Active Leakage Power (mw) 19

20 Agenda Intel Big Data Context Overview Key Research Areas Challenges Partnerships 20

21 Runnemede Program Assured Operation <10% overhead Checkpoint with flash/cpm Security through sandboxing University of Illinois 1000X Energy reduction Heterogeneous, tightly coupled Simple architecture Resiliency CPU HW/SW Co Design Execution Model System Management & Concurrency Event driven codelets Self aware introspection Code and data motion ET International, Inc. Data Movement Heterogeneous & tapered Large local memory Interconnect Fabric Memory Productivity Application Efficiency Model based Goal oriented Self morphing 1000X energy reduction Overhauled DRAM Arch Resilient memory Our Collaborators 21