EFMPlus Data Recovery Circuit with a Fast Locking Scheme for 12X Speed DVD-ROM Drivers

Transcription

1 Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002, pp EFMPlus Data Recovery Circuit with a Fast Locking Scheme for 12X Speed DVD-ROM Drivers Jae-Chul Lee, Jae-Shin Lee and Suki Kim Department of Electronics Engineering, Korea University, Seoul Shin-Il Lim Department of Computer Engineering, Seokyeong University, Seoul (Received 11 February 2001) In this paper, we propose an EFMplus (Eight to Fourteen Modulation plus code) data recovery circuit for 12X speed DVD-ROM drivers. This data recovery circuit consists of a frequency locking loop (FLL) and a phase locking loop (PLL). The frequency locking loop in the proposed data recovery circuit has the characteristic of a variable system transfer function, depending on the number of frequency errors. For large frequency errors, the FLL increases the loop gain to achieve fast locking while for small frequency errors, this FLL decreases the loop gain to reduce the settling time. Also, this FLL has a function that adaptively controls the loop bandwidth according to the input frequencies. By using this function, the FLL can always retain a constant loop gain, regardless of variations in the input frequency, and a stable phase locked loop (PLL) can be achieved over a wide input frequency range. This circuit is implemented in a 0.25 um 1-poly, 5-metal CMOS process and occupies an active area of mm. PACS numbers: Keywords: Intergrated circuits I. INTRODUCTION In recent multimedia systems, large storage and fast transmission devices for high capacity digital data are widely required. The DVD-ROM driver is a key device for handling large amounts of information. These days, 8X speed DVD-ROM drivers are widely used due to their fast readout speed and massive storage capacity. In the constant angular velocity (CAV) rotation type DVD-ROM drivers, a PLL (phase locked loop) having a wide locking range is needed for data recovery due to the difference in linear velocity between the inner-most edge of the disk and the outer-most edge of the disk [1]. Also, low jitter and fast locking characteristics are required in this PLL. A common approach to improve the locking speed of the PLL is to use a gear-shifting method for loop bandwidth control. In such a PLL, the loop bandwidth of the PLL is expanded by increasing the charge pump current or by increasing the gain of the phase detector [2]. However these techniques tend to have stability problems and poor jitter characteristics. To solve these problems in the PLL design of a wide locking range, we designed a PLL with a dual loop ar- chitecture to achieve a wide locking range and low jitter [15]. Also, to reduce locking time, we adopted a frequency lock loop having the characteristics of a variable loop gain depending on the number of frequency errors [3]. The designed PLL has a locking range of MHz and can be used for 12X speed DVD-ROM drivers. II. PLL ARCHITECTURE A block diagram of the proposed data recovery circuit is shown in Fig. 1. Due to DVD-ROM driver s fast read- [email protected] [email protected]; Fax : Fig. 1. Block diagram of the proposed data recovery circuit

2 -558- Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002 Fig. 2. Block diagram of the frequency detector. Fig. 3. Frequency-to-voltage converter and its operation. out speed and massive storage capacity, a PLL having a wide locking range, low jitter, and fast locking characteristics is required. The data recovery consists of a dual loop-frequency locking loop and phase locking loop to achieve a wide locking range and low jitter. Since the input signal of the DVD-ROM drivers is the EFMplus signal, which is a nonreturn-to-zero (NRZ) type, a general phase frequency detector (PFD) can not be used; rather, a phase detector (PD) which detects every edge of the EFM signal has to be used. The locking sequence of the proposed PLL is as follows: when the EFM signal is applied, the frequency locking loop is activated and the VCO clock frequency is locked within ±5 % of the input frequency; then, the phase locking loop is operated to lock the phase. In this way, the frequency and the phase are locked with the input signal. Figure 2 shows a block diagram of the frequency detector. The frequency detector is composed of an EFM pulse width counter, three registers, a frame pulse generator, a digital comparator, a frequency to voltage converter, and a function generator and pulse width modulation (PWM) generator. The EFM pulse width counter block measures the input pulse width and stores it in Register #1 for every pulse edge. The digital comparator block compares the data of Register #1 with those of Register #2. If the value in Register #1 is larger than that of Register #2, the value in Register #1 is stored in Register #2. In the case where the value in Register #1 is smaller than that in Register #2, the value in Register #2 is held. The value in Register #2 is transferred to Register #3 by using the output signal of the frame pulse generator in every frame. Through these processes, the pulse having the maximum width compared to the VCO clock frequency is detected. This pulse is treated as the sync pulse. The PWM generator block makes up/down pulse signals that control the charge pump. The pulse width varies depending on the value of the frequency error stored in Register #3. In the constant angular velocity (CAV) type DVD- ROMs, the frequency at the outer-most edge of the disk is over 2.5 times higher than that at the inner-most edge of the disk, so the loop stability is degraded as the input frequency varies. The frequency-to-voltage converter (FVC) [7] shown in Fig 3 is used to retain the constant system transfer function, regardless of the input frequency variation, by controlling the current of charge pump. Fig. 4 shows characteristic curve of the PWM generator. The gain of this block κ d, is given by κ d (n + 1) = α κ d (n) + β n, (1) where α is a weighting factor, β is a coefficient that converts the value of the input-output frequency error from a frequency dimension to a gain dimension, and n is the integer number representing the value of the frequency error. Our proposed PWM generator has a nonlinear characteristic curve as the frequency error varies, as shown in Fig. 4. When the system has large frequency errors, the FLL increases the loop gain to achieve fast locking. On the other hand, for small frequency errors, this FLL decreases the loop gain to reduce the settling time and jitter. With the loop gain varying with the number of frequency errors, we can achieve fast locking and reduced jitter at the same time. Performance comparisons with a conventional architecture will be described in the next section. To minimize the jitter due to the supply voltage variation, we adopted a fully differential delay cell in the 3-stage ring VCO. The circuits of the ring VCO and the delay cell are shown in Fig. 5. The delay of one delay Fig. 4. Transfer curve of the PWM (pulse width modulator) generator.

3 EFMPlus Data Recovery Circuit with a Fast Locking Scheme Jae-Chul Lee et al Fig. 5. Delay cell and ring VCO. cell is represented as t d = KR ds4 C p, (2) where C p is the stray capacitance at the Vout+ node and K is a multiplication constant. Since the ring VCO has 3 stages, its oscillation frequency is given by F (frequency) = g m4 6KC P, (3) g m4 = 2u P C ox (W/L)I tail. (4) By combining Eqs. (2) and (3), we find the oscillation frequency of the ring VCO to be 2uP C ox (W/L)I tail F (frequency) = (5) 6KC P For the input frequency range of 12X speed DVD-ROMs, which is approximately MHz, the operating frequency range of the VCO is set to about 600 MHz, which is twice the input signal frequency range. In general, if a VCO with a wide tuning range is to be achieved, the VCO gain should be large. However, a large VCO gain degrades jitter characteristics and causes instability [4]. In order to implement a VCO with a wide tuning range and a small VCO gain, we adopted a V-I converter with a wide input range. Fig. 6 shows the used V-I converter. Since the oscillation frequency of the VCO can be given by Eq. (5), the V-I converter output Fig. 7. Input signal frequency vs. charge pump output voltage. current, I tail, should be proportional to the square of the control voltage, V ctl. In Fig. 6, M5 and M2 operate in the triode region, so the input voltage range of M1 can be enlarged. For a general V-I converter, the VCO control voltage range is less than 60 % of the supply voltage. For the used V-I converter, the VCO control voltage range was as wide as 76 % of the supply voltage. As a result, the VCO gain was 315 MHz/V. Table 1 shows a comparison of several VCO characteristics with those for recently presented VCOs. If M11 does not exist and V ctl < V th, I va = I max occurs. In this situation, I tail =0, so the VCO does not oscillate. To prevent this phenomenon, I min (80 µa) is always driven at M11. As a result, the output current, I tail, can be represented as I tail = I max + I min I va = K 1 V 2 ctl + I min, (6) where K 1 is a constant value. If the input signal frequency is extremely high or low, the charge pump output voltage in the frequency lock loop is near the supply voltage or the ground. Fig. 7 illustrates this phenomenon. In this case, the output voltage of the charge pump in the phase lock loop is nearly the same as that in the frequency lock loop. Therefore, a source/sink current mismatch of the charge pump due to the difference in the drain-source voltages of the PMOS and the NMOS in the phase lock loop can occur. This source/sink current mismatch degrades the locking range and the jitter. To avoid these problems, we used a charge pump circuit with perfect source/sink current matching [1]. III. IMPLEMENTATION & RESULTS Fig. 6. Voltage to current converter. The proposed data recovery circuit was implemented in a chip with 0.25 um 1-poly, 5-metal CMOS technology and occupie a die area of mm. The tuning range

4 -560- Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002 Table 1. Comparison with recently presented VCOs. VCO Process Supply Control Voltage Frequency VCO Voltage (V) Range (V) Range (MHz) Gain (MHz/V) Boerstler 0.4 um CMOS (JSSC 99 [12]) Yang 0.8 um CMOS (JSSC 97 [13]) M. Rau 0.5 um CMOS (JSSC 97 [14]) This Work 0.25 um CMOS of VCO was about 600 MHz ( MHz), as shown in Fig. 8. Since the operating frequency range of the VCO was set to about twice that of the input signal frequency range, as we described in prior section, the lock range was about 300 MHz ( MHz). Fig. 9 shows the simulation results for the proposed PLL locking process. At first, the VCO oscillates at its free running frequency (75 MHz). Then, the reference signal (350 MHz) is applied. The lock signal is activated within about 50 clock cycles after the initial reference signal is applied. The advantage is a faster acquisition time compared to those for recently published PLLs, as shown in Table 2. Fig. 10 shows the layout of the implemented chip, and the performance of the proposed PLL is summarized in Table 3. IV. CONCLUSION In this paper, we have described an EFMplus data recovery circuit with a fast locking scheme for 12X speed DVD-ROM drivers. A PLL with a dual loop architecture is proposed to achieve a wide locking range and low jitter. In order to increase the lock speed, we also proposed a PWM generator circuit with a gain that varied with the value of the frequency error. The proposed data recovery circuit was implemented in a 0.25 um 1-poly, 5- metal CMOS process and occupied a die area of mm. The designed PLL had a locking range of Table 2. Comparison of the acquisition time with the times for recently presented PLLs. CPPLL [8] CPPLL [9] Mixed PLL [10] Digital DLL [11] ADPLL [6] This work (simulation results) 375 cycles 220 cycles 100 cycles 60 cycles 50 cycles About 50 cycles Fig. 8. VCO tuning range. Fig. 9. Locking process of the proposed data recovery circuit. Fig. 10. Layout of the proposed data recovery circuit.

5 EFMPlus Data Recovery Circuit with a Fast Locking Scheme Jae-Chul Lee et al Table 3. PLL. VCO tuning range Locking range Acquisition time Technology Die area Supply voltage Power dissipation Summary of the performance of the proposed MHz MHz About 50 Reference cycles 0.25 um standard CMOS 1-poly, 5-metal mm 2.5 V About 55 mw MHz, and a acquisition within about 50 clock cycles was achieved. REFERENCES [1] Jae-Shin Lee, Woo Kang Jin, Dong Myung Choi, Gun Sang Lee and Suki Kim, IEEE Trans. Consumer Electronics 46, 487 (2000). [2] Turgut S. Aytur and Behzad Razavi, IEEE J. Solid State Circuits 30, 1457 (1995). [3] Joonsuk Lee and Beomsup Kim, IEEE J. Solid State Circuits 35, 1137 (2000). [4] John A. McNeil, IEEE J. Solid State Circuits 32, 870 (1997). [5] M. Mizuno, K. Furuta, T. Andoh, A. Tanabe, T. Tamura, H. Miyamot, A. Furukawa and M. Yamashina, ISSCC Dig. Tech. Papers (San Francisco, Feb., 1995), p [6] J. Dunning et al., IEEE J. Solid State Circuits 30, 412 (1995). [7] A. Djemouai, M. Sawan and M. Slamani, International Conference on Microelectronics (Tunisia, Dec., 1998), p. 63. [8] Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer and Steve Wyatt, IEEE J. Solid State Circuits 30, 1259 [9] Vincent von Kaenel, Daniel Aebischer, Christian Piguet, Evert Dijkstr, IEEE J. Solid State Circuits 31, 1715 [10] P. Roo, R. Spencer, P. Hurst, in ISSCC Dig. Tech. Papers (San Francisco, Feb., 1998), p [11] Satoru Tanoi, et al., IEEE J. Solid State Cicuits 31, 487 [12] David W. Boerstler, IEEE J. Solid State Circuits 34, 513 (1999). [13] Howard C. Yang, Lance K. Lee and Ramon S. Co, IEEE J. Solid State Circuits 32, 582 (1997). [14] M. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer and N. Menoux, IEEE J. Solid State Circuits 32, 1156 (1997). [15] Yeon Kug Moon, Kwang Sub Yoon and Chang Ho Han, J. Korean Phys. Soc. 37, S803 (2000).