A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector

Transcription

1 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 1, MARCH A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector Chao-Ye Wen, Zhi-Ge Zou, Wei He, Jian-Ming Lei, and Xue-Chen Zou Abstract The need for wide-band clock and data recovery (CDR) circuits is discussed. A 2 Gbps to 12 Gbps continuous-rate CDR circuit employing a multi-mode voltage-control oscillator (VCO), a frequency detector, and a phase detector (FD&PD) is described. A new automatic frequency band selection (FBS) without external reference clock is proposed to select the appropriate mode and also solve the instability problem when the circuit is powering on. The multi-mode VCO and FD/PD circuits which can operate at full-rate and half-rate modes facilitate CDR with six operation modes. The proposed CDR structure has been modeled with MATLAB and the simulated results validate its feasibility. Index Terms Clock and data recovery, frequency band selection, frequency detector, phase detector. 1. Introduction The clock and data recovery (CDR) circuit plays an important role in wired communication systems. With the wave-length division multiplexing technique, the information can be exchanged at different bit rates in optical domain. In addition, since the power scales down as the operating frequency decreases, low speed operations can substantially reduce the power consumption of the chips. In order to meet the requirements of both high and low speed transmission, a certain type of wide-range CDR is essential to the serial link communication [1]. At last, this wide-range CDR circuit should meet the data rate requirements of various standards so that the cost of link system could be reduced [2]. These reasons serve as the Manuscript received June 20, 2011; revised August 31, This work was supported by the Hubei Natural Science Foundation of China under Grant No. 2010CDB02706 and the Fundamental Research Funds for the Central Universities under Grant No. C2009Q060. C.-Y. Wen and W. He are with the Graduate School, Huazhong University of Science and Technology, Wuhan , China ( wenchaoye1987@163.com; hewei0019@126.com). Z.-G. Zou, J.-M. Lei, and X.-C. Zou are with the Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan , China ( zouzhige@mail.hust.edu.cn; leijianming@mail.hust.edu.cn; and estxczou@mail.hust.edu.cn). Digital Object Identifier: /j.issn X motivation of designing a wide-band CDR circuit. Several techniques have been used to broaden the CDR bandwidth. In [3], a dual-mode voltage-control-oscillator (VCO) with two central frequencies was used to implement the CDR circuit. However, due to the restrictions of jitter characteristics, the gain of the VCO cannot be high [4], which makes these CDR circuits operate at isolated rates. In [5], a VCO with more modes was adopted in order to make CDR s range continuous. Compared with the architecture used in [3] and [5], the proposed CDR includes not only a multi-modes VCO but also a new frequency detector and a new phase detector (FD&PD). The FD&PD can operate at full-rate and halfrate modes. With this improvement, a 2 Gbps to 12 Gbps continuous-rate CDR circuit without a reference clock is realized. The difficulty of the wide-band continuous-rate CDR circuit is how to choose an appropriate operating frequency band. To solve the problem, a new frequency band selector (FBS) is proposed. In addition, how to reduce the dual-modes FD&PD s power consumption is also considered. The paper is arranged as followed. Section 2 describes the CDR architecture. Operation principle and details of the building block are discussed in Section 3. The simulation results are shown in Section 4. Section 5 gives the conclusion of this work. 2. CDR Architecture Six modes of the proposed CDR are summarized in Table 1. The CDR circuit contains four-mode VCO and dual-mode FD&PD. Fig. 1 shows the block diagram of the CDR circuit, consisting of the proposed FBS, dual-mode FD&PD, a charge pumps (CPs), a second-order low-pass filter (LPF), and a multi-mode VCO. And the FBS consists of a coarse frequency detection and a control logic. The CDR design in this paper utilizes a novel FBS to judge an approximate scope of data rate, and create control signals to select an appropriate mode of FD&PD and VCO. The enable signal (EN) disables FBS when a mode has been selected. How to select a mode to solve the instability problem when the circuit is powering on must be carefully considered in this circuit.

2 68 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 1, MARCH 2012 Table 1: Six modes of the proposed CDR Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Data rate (Gbps) Center-frequency of VCO (GHz) FD/PD Full-rate Full-rate Half-rate Half-rate Half-rate Half-rate Fig. 1. Architecture of the CDR. Fig. 2. Proposed frequency band selector. Fig. 3. Coarse frequency detector. 3. Building Blocks of the CDR 3.1 Frequency Band Selector The proposed FBS is shown in Fig. 2. In order to select an appropriate mode when the circuit is powering on, FBS should have the ability of detecting frequency. But a conventional rotational frequency detector has a limited acquisition range of about ±50%, and is susceptible to harmonic locking [6], so it can not satisfy this application. This paper presents a new coarse frequency detector (CFD) to solve the problem. The CFD counts the presence of rising edge during ΔT as shown in Fig. 3. N can be expressed as N kfδ T (1) where f is data rate and k is transition rate. f can be concluded from (1) when the values of N, k, and ΔT are already known. When data type is non-return-to-zero (NRZ) pseudo-random-binary-sequence (PRBS) or NRZ clock pattern, k is 0.25 or 0.5, respectively [7]. The delay cell creates ΔT, the six D flip-flops (DFFs) sample the output of CFD after ΔT, obtaining the control signals of FD&PD and VCO. Meanwhile, OR_1 generates EN to disable FBS. If the ΔT is too long, the counter would need more digits and consume more power; but if the ΔT is too short, the counter could not satisfy the application of wideband frequency detection. Based on the frame structure of IEEE 802.3, which has 7 bytes clock pattern in the front, k is 0.5. We can obtain ΔT=2 ns from (1). Supposing N f, as a result, a four bit binary counter (B3B2B1B0) would be enough. T1 is the instable period when the circuit is powering on as shown in Fig. 4. Unfortunately, T 1 is uncertain, so if CFD works immediately when the circuit is powering on, it would obtain a wrong result, as shown in Fig. 4 and. A NOR_1 is added into the circuit to solve this problem, which makes sure that CFD starts to work when B3B2B1B0=0000 and T 1 no longer affects the frequency detection result, as shown in Fig. 4 (c). 3.2 Frequency Detector The proposed FD is shown in Fig. 5. Signals from FBS control S 1 and S 2. When S 1 is on and S 2 is off, FD is a rotary frequency detector in [3]; in contrary FD works as half-rate mode like [8]. We can conclude from Table 1 that Mode 3 and Mode 1 have the maximum 20% offset between data rate and VCO center-frequency compared with other modes. According to [7] and [8], the FD can satisfy this offset. 3.3 Phase Detector PD starts to work when VCO s frequency is within PD s acquisition band. The proposed dual-mode PD is shown in Fig. 5. When S 1 is on and S 2 is off, PD works in full-rate mode and ERROR_1 and REF_1 are effective. The two latches in dotted line box form master-slave DFF just like Hogge full-rate PD dose. In contrary, PD works at half-rate mode. Compared with the method in [4], the proposed PD consumes less power and saves area.

3 WEN et al.: A 2Gbps to 12Gbps Wide-Range CDR with Automatic Frequency Band Selector 69 (c) Fig. 4. T 1 instable period: wrong result when T 1 is long, wrong result when T 1 is short, and (c) CFD starts to work after T 1. Fig. 5. Dual-modes: dual-mode FD and dual-mode PD. Fig. 6. Proposed CDR circuit. 4. Simulation Results Fig. 6 show s the model of the proposed CDR in MATLAB. All input datas have a 7-byte clock pattern header and change to PRBS to simulate the frame structure of IEEE To verify the acquisition ability of the CDR, we set the input data rate from 2 Gbps to 12 Gbps. Fig. 7 shows the VCO s frequency. VCO s frequency is equal to data rate in Fig. 7 and is as half times as data rate in Fig. 7, because the FD/PD works at full-rate mode at the former and at half-rate at the later. And the acquisition time is less than 12 μs.

4 70 JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 1, MARCH (b ) Fig. 7. VCO s output frequency when acquisitio n: when data rates are 2 Gbps, 3 Gbps, and 4 Gbps, respectively and when data rates are 6 Gbps, 8 Gbps, 10 Gbps, and 12 Gbps, respectively Tim e (μs) Tim e (μs) Fig. 8. VCO s frequency: when the phase step responds when the frequency step responds. Voltage (V) Voltage (V) Fig. 9. Input and output data of the proposed CDR: D in and D out Ti me (μs) 0.5 W orks Table 2: Performance comparisons Acquisition time Data rate (Gbps) This work <12 μs 2 12 ASSCC 10 [1] Architecture Required Ext. Ref. clock To verify CDR s ph ase locking abi lity, the input data has 0.5-UI p has e step at 1 5 μs. Fig. 8 ( a) shows th e result that VCO s frequency has a tremble at 15 μs and goes back to stead y after that. Fig. 8 shows the circuit s frequency tracking ability. The data rate changes from 6 Gbps to 5 Gbps at 10 μs, as a result, the VCO s frequency changes from 3 GHz to GHz. At last, Fig. 9 shows the recovered data output from the circuit. We can see that output data lags behead input data by 1-UI. The performance comparisons of this work are listed in Table 2. 5 Conclusions Full-rate/ Half-rate ISSCC 11 [2] < 0.25 ms 0.5 Half-rate No ISSCC 06 [9] < 25 ms 0.15/0.6/ 1.2/ ISSCC 05 [10] <1 ms Full-rate No This work pr esents a design procedure of wideband CDR, and presents a continuous-rate CDR with the procedure. With t he proposed FBS and dual-m ode FD&PD, the receivable data rate of CDR is from 2 Gbps to 12 Gbps. We can broaden the acquisition band through combining multi-mode VCO and multi-mode FD&PD. No NA quarter-rate Yes Full-rate No

5 WEN et al.: A 2Gbps to 12Gbps Wide-Range CDR with Automatic Frequency Band Selector 71 References [1] S.-Y. Lee, H.-R. Lee, Y.-H. Kwak, et al., 250Mbps-5Gbps wide-range CDR with digital vernier phase shifting and dual mode control in 0.13μm CMOS, in Proc. of IEEE Asian Solid-State Circuits Conf., Beijing, 2010, pp [2] R. Inti, W.-J. Yin, A. Elshazly, N. Sasidhar, and P. K. Hanumolu, A 0.5-to-Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance, in Proc. of IEEE International Solid-State Circuits Conf., San Francisco, 2011, pp [3] K. Min and C. Yoo, A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport, IEEE Trans. on Consumer Electronics, vol. 56, no. 4, pp , [4] B. Razavi, Design of Integrated Circuits for Optical Communications, New York: McGraw-Hill, 2003, ch. 6. [5] I. Jung, D. Shin, T. Kim, and C. Kim, A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays, IEEE Trans. on Circuits and Systems-II, vol. 56, no. 10, pp , [6] D. G. Messerschmitt, Frequency detectors for PLL acquisition in timing and carrier recovery, IEEE Trans. on Communications, vol. COM-27, no. 9, pp , [7] B. Stilling, Bit rate and protocol independent clock and data recovery, Electronics Letters, vol. 36, no. 9, pp , [8] R.-J. Yang, S.-P. Chen, and S.-I. Liu, A Gb/s clock and data recovery circuit for the 10-Gbase-LX4 ethernet, IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp , [9] M. H. Perrott, Y. Huang, R. T. Baird, et al., A Gb/s multi-rate 0.25μm CMOS CDR utilizing a hybrid analog/digital loop filter, in Proc. of IEEE International Solid-State Circuits Conf., San Francisco, CA, 2006, pp [10] D. Dalton, K. Chai, E. Evans, et al., A 1Mb/s to 2.7Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate read back, in Proc. of IEEE International Solid-State Circuits Conf., San Francisco, CA, 2005, pp Chao-Ye Wen was born in Guangxi Province, China, in He received the B.E. degree in electronic science & technology from Huazhong University of Science and Technology (HUST), Wuhan, in He is currently pursuing the M.S. degree with the Department of Electronic Science & Technology, HUST. His research interests include analog IC design and mixed-signal IC design. Zhi-Ge Zou was born in Hubei Province, China, in He received the M.S. degree in electrical & electronic engineering from HUST in He received the Ph.D. degree in micro-electronics and solid state electronics from HUST in He is currently an associate professor with the Department of Electronic Science & Technology, HUST. His research interests include analog IC design and mixed-signal IC design. Wei He was born in Hubei Province, China, in He received the B.S. degree in physics from Wuhan University, Wuhan, in He is currently pursuing the M.S. degree with the Department of Electronic Science & Technology, HUST. His research interests include analog IC design and mixed-signal IC design. Jian-Ming Lei was born in Hunan Province, China, in He received the M.S. degree and the Ph.D. degree in micro-electronics and solid-state electronics from HUST in 2001 and 2004, respectively. Now he is an associate professor with the Department of Electronic Science and Technology, HUST. His research interests include mix-signal IC design, CMOS-RF IC design, semiconductor, and CMOS-MEMS technology, especially in ultra-high-speed communication circuit. Xue-Chen Zou received the M.S. degree and the Ph.D. degree in micro-electronics and solid-state electronics from HUST in 1988 and 1995, respectively. He did postdoctoral research with City University of Hong Kong from 1996 to Now he is the Chairman of the Department of Electronic Science and Technology, HUST. His research interests include VLSI, microelectronic device, and Internet of things.