it4036f 120-ps Wideband Phase Delay Description Features Device Diagram Timing Diagram

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1 Description The it436f is an ultra-wideband phase delay with an ECL topology to ensure high-speed operation that accepts either single-ended or differential data input. Its high output voltage, excellent rise and fall times, and high eye diagram quality at data rates up to 12.5 Gb/s make the it436f suitable for timing adjustment in data and clock distribution at very high speed. Complex digital applications benefit from the it436f, including clock data recovery, edge detectors, NRZ-to-RZ converters, MUX/DEMUX, and data restoration. The device features a single delay element that provides up to 12-ps delay. Delay control can be either differential (using both Cp and Cm) or single-ended (Cm is the active control pad while Cp is shorted to Cref). The control voltage range for the delay input is from -1.3 to -1.9 whether the control is single-ended or differential. The device can delay NRZ streams with data rates up to 12.5 Gb/s or a clock signal up to 12.5 GHz. Both inputs and outputs are DC-coupled. At the input side, internal 5-ohm resistors avoid the need for external impedance matching terminations. The it436f is housed in a 5x5-mm RoHS-6-compliant QFN package. Features Device Diagram Ultra wideband: Up to 12.5 Gb/s NRZ Delay adjustment up to 12 ps 45 mpp single-ended output Low RMS jitter degradation Output rise time (2% 8 %): <24 ps Output fall time (2% 8 %): <22 ps 5-ohm matched DC-coupled inputs and outputs Differential or single-ended I/O Power consumption: 56 mw 5x5-mm RoHS-6-compliant QFN package Timing Diagram 1

2 Absolute Maximum Ratings Symbol Parameters/conditions Min. Max. Units Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this document is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EE IH IL C TA TSTG Power supply voltage Input voltage level, high level Input voltage level, low level Delay control voltage Operating temperature range die Storage temperature C C Recommended Operating Conditions Symbol Parameters/conditions Min. Typ. Max Units T A Operating temperature range die 85 C EE Power supply voltage -3.3 C IH IL INDC Delay control voltage Input voltage level, high level (single ended). Input voltage level, low level (single ended) -.4 DC input voltage (with DC-coupled input) -.2 Electrical Characteristics Symbol Parameters Min. Typ. Max. Units At ambient temperature and ee = -3.3 EE IH Power supply voltage Input voltage level, high level (single ended) IL Input voltage level, low level (single ended) With a single-ended input, the unused pad must be tied to INDC. 2. With a single-ended output, the unused pad must be terminated with 5 ohms to ground. INDC OUT TR TF DC input voltage (with DC-coupled input) (1) Data output voltage amplitude (2) Output rise time (2% 8%) Output fall time (2% 8%) ps ps 2

3 Electrical Characteristics Symbol T ADJ S 11 Parameters Output phase delay adjustment Input return loss (up to 15 GHz) Min. Typ. 12 Tbd Max. Units ps db S 22 Output return loss (up to 15 GHz) Tbd db F MAX Maximum clock frequency 12.5 GHz I EE Power supply current ma P D Power dissipation W Through eye at 12.5 Gb/s 3

4 Evaluation board measurement at ee = Single-ended input: 45 mpp Input data rate: 12.5 Gb/s Control voltage: Cp = Cref, Cm = -1.6 Jitter degredation : 1.1 (Delay 5 ps, 225 deg.) Input data rate: 12.5 Gb/s Control voltage: Cp = Cref, Cm = -1.9 Jitter degredation :.6 (delay 12 ps, 54 deg.) 4

5 Evaluation board measurement at ee = Single-ended input: 45 mpp Input data rate: 1.7 Gb/s Control voltage: Cp = Cref, Cm = -1.6 Jitter degradation :.5 (Delay ps, deg.) Input data rate: 1.7 Gb/s Control voltage: Cp = Cref, Cm = -1.9 Jitter degradation :.2 (Delay 15 ps, 57 deg.) 5

6 EB measurement at ee = -3.3 Clock signal at 12.5 GHz Single-ended data input: +/-2 mpp Clock signal at 11.5 GHz Single-ended data input: +/-2 mpp 6

7 Evaluation board measurement at ee = -3.3 Clock signal at 1.7 GHz Single-ended data input: +/-2 mpp Clock signal at 9 GHz Single-ended data input: +/-2 mpp 7

8 Clock signal at 12.5 GHz Single-ended data input: +/-2 mpp cm span from 1.3 to 1.9 Jitter Degradation 2.5 Jitter degradation vs cm 2 Jdeg (ps) NRZ 12.5 Gb/s NRZ 1.7 Gb/s Clock 12.5 GHz cm () 8

9 Temperature Characterization Power Supply Current ma Degrees Celsius Output Amplitude m Degrees Celsius 9

10 Delay vs cm Delay (ps) cm () Amplitude vs GHz for clock signals Out Ampl (m) Frequency (GHz) Recommended Operational Setup it436f 1

11 F Package Drawing and Pinouts Dimensions in inches (mm) Except where noted, tolerance on dimensions is: ±.39 (.1) Pinouts P1: ee P11: ee P2: Din P12: Dout P3: N/C P13: N/C P4: Din/ P14: Dout/ P5: ee P15: ee P6: N/C P16: ee P7: Cm P17: N/C P8: Cp P18: N/C P9: cref P19: N/C P1: ee P2: N/C 11