PLL DESIGN AND CLOCK/FREQUENCY GENERATION (PLL 设 计 与 时 钟 / 频 率 产 生 ) Woogeun Rhee Institute of Microelectronics Tsinghua University

Transcription

1 PLL DESIGN AND CLOCK/FREQUENCY GENERATION (PLL 设 计 与 时 钟 / 频 率 产 生 ) Woogeun Rhee Institute of Microelectronics Tsinghua University

2 Course Objective This course gives insights into phase-locked clocking as well as the ability of gaining system perspectives and circuit design aspects of phase-locked loop (PLL) for various applications. In the first half of this course, basic theoretical analysis of the PLL and system/circuit design considerations will be discussed. The second half of the course consists of extensive lectures covering practical design aspects in various PLL applications. Some advanced topics such as coupling, testability, and on-chip compensation will be also useful for those who are interested in system-on-chip (SoC) design and advanced mixed-signal IC design. From this course, the students expect to learn followings; - role of clock generation/synchronization in modern communication systems - basic concept and theoretical analysis of PLL - system design perspectives and architectures - practical circuit design aspects - advanced topics; coupling, testability, on-chip compensation, Simply speaking, we will learn where to, when to, and how to use PLL for various applications. 2 W. Rhee, Institute of Microelectronics, Tsinghua University

3 Course Outline First Half I. Overview of Clocking and Frequency Generation 1. Course introduction 2. Phase-locked clocking in modern communication systems II. Phase-Lock Basics 1. PLL linear model 2. Loop components 3. Loop dynamics 4. Transient response and acquisition 5. PLL behavioral simulations III. PLL Design 1. System design perspectives - spur and modulation - phase noise/jitter - settling time - bandwidth optimization 2. Circuit design aspects - phase detector - charge pump - frequency divider - voltage-controlled oscillator 3. Delay-locked loop (Midterm Examination) 3 W. Rhee, Institute of Microelectronics, Tsinghua University

4 Course Outline Second Half IV. Applications 1. Frequency synthesizers for RF applications - system design consideration; phase noise, spur, and settling time - integer-n/fractional-n frequency synthesizers - direct digital frequency synthesizer 2. Clock-and-data recovery for serial link and optical communications - system design considerations; jitter transfer, jitter tolerance, and jitter generation - circuit design aspects in multi-gb/s SerDes systems - DLL-based CDR for serial-link backplane applications - D/PLL-based CDR for SONET applications 3. Clock multiplier unit for digital clock generation - system design considerations; RJ, DJ, long-term jitter, and short-term jitter - circuit design for high supply rejection - examples; PLL design for FB-DRAM, multiplying DLL (MDLL) for low jitter accumulation 4. PLL for design on demand V. Advanced Topics 1. Recent PLL works and trends 2. Coupling effects on PLL performance 3. Various in-situ calibration/compensation methods for technology-friendly PLL 4. Future challenges VI. Project Discussion (Final Examination) 4 W. Rhee, Institute of Microelectronics, Tsinghua University

5 Course Assessment Homework: 10% Midterm exam: 20% Final exam: 30% Term project: 40% 5 W. Rhee, Institute of Microelectronics, Tsinghua University

6 Role of Clocking in Digital Systems Quantization (ADC) Discrete Time (PLL) As digital systems grow, the role of PLL/ADC are getting more important. 6 W. Rhee, Institute of Microelectronics, Tsinghua University

7 PLL/ADC Related Papers in ISSCC PLL/DLL/CDR 6 30 VCO/DIV Clocking/Jitter ADC/DAC Other Almost 30% papers from clocking and data conversion. Conference theme: Multimedia for a Mobile World 7 W. Rhee, Institute of Microelectronics, Tsinghua University

8 Importance of Clocking Digital Analog Clock Clock jitter Ground Ground noise As clock frequency increases, achieving low jitter clock is important. 8 W. Rhee, Institute of Microelectronics, Tsinghua University