CS/ECE 250: Computer Architecture Designing a Single Cycle Datapath
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1 : Computer Architecture Designing a Single Cycle Datapath Copyright 213 Alvin Lebeck Duke University
2 What is Computer Architecture? Coordination of levels of abstraction Application Compiler Operating System Firmware Software Interface Between HW and SW CPU Memory I/O system Digital Design Circuit Design Instruction Set Architecture, Memory, I/O Hardware Under a set of rapidly changing technology Forces 2
3 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory Input Datapath Output Today s Topic: Datapath Design 3
4 Datapath Design How do we build hardware to implement the MIPS instructions? Add, LW, SW, Beq, Jump 4
5 An Abstract View of the Implementation PC Instruction Address Ideal Instruction Memory Rd 5 Instruction Rs 5 Rt 5 Imm Rw Ra Rb -bit Registers A B ALU Data Address Data In Ideal Data Memory DataOut 5
6 The MIPS Instruction Formats All MIPS instructions are bits long. The three instruction formats: R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-type op rs rt immediate 6 bits 5 bits 5 bits bits J-type op target address 6 bits 26 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction 6
7 The MIPS Subset (We can t implement them all!) ADD and subtract add rd, rs, rt sub rd, rs, rt OR Immediate: ori rt, rs, imm LOAD and STORE lw rt, rs, imm sw rt, rs, imm BRANCH: beq rs, rt, imm JUMP: j target op rs rt rd shamt funct op bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits bits target address 6 bits 26 bits
8 The Hardware Program How do we build the hardware to implement the MIPS instructions and their sequencing? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction 8
9 Combinational Logic (Basic Building Blocks) A Adder B Adder CarryIn Sum Carry Select MUX A B MUX Y OP ALU A B ALU Result Zero 9
10 Storage Element: Register (Basic Building Block) Register Similar to the D Flip Flop except N-bit input and output Write Enable input Write Enable: negated (): Data Out will not change Write Enable Data In asserted (1): Data Out will become the same as Data In. N Data Out N 1
11 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: RA selects the register to put on busa RB selects the register to put on busb RW selects the register to be written via busw when Write Enable is 1 Clock input (CLK) Write Enable busw The CLK input is a factor ONLY during write operation RW RA RB bit Registers During read operation, behaves as a combinational logic block: RA or RB valid => busa or busb valid after access time. busa busb 11
12 Storage Element: Idealized Memory Memory (idealized) One read/write port On access per cycle (read or write) One input Data bus: Data In One output Data bus: Data Out One Address bus: Address Memory word is selected by: Data In Write Enable Write Enable = : Address selects the word to put on the Data Out bus Write Enable = 1: Address selects the memory word to be written via the Data In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: Address valid => Data Out valid after access time. Address DataOut 12
13 An Abstract View of the Implementation PC Ideal Instruction Memory Instruction Address Rd 5 Instruction Rs 5 Rt 5 Imm Can think of computer as large finite state machine State is stored in registers and memory. For this simple design: every clock updates state based on previous state We don t want to enumerate all the states! Rw Ra Rb -bit Registers A B ALU Data Address Data In Ideal Data Memory DataOut 13
14 Clocking Methodology Setup Hold Setup Hold Don t Care All storage elements are clocked by the same clock edge (ignore NOT on clock) Cycle Time >= CLK-to-Q + Longest Delay Path + Setup + Clock Skew Longest delay path = critical path 14
15 An Abstract View of the Critical Path Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: Address valid => Output valid after access time. PC Instruction Address Ideal Instruction Memory Rd 5 Instruction Rs 5 Rt 5 Imm Rw Ra Rb -bit Registers ALU Data Address Data In Ideal Data Memory DataOut 15
16 The Steps of Designing a Processor Instruction Set Architecture => Register Transfer Language Register Transfer Language => Datapath components Datapath interconnect Datapath components => Control signals Control signals => Control logic
17 Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[pc] Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- something else PC Next Address Logic Address Instruction Memory Instruction Word 17
18 RTL: The ADD Instruction add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The ADD operation PC <- PC + 4 Calculate the next instruction s address 18
19 RTL: The Load Instruction lw rt, rs, imm mem[pc] Fetch the instruction from memory Address <- R[rs] + SignExt(imm) Calculate the memory address R[rt] <- Mem[Address] Load the data into the register PC <- PC + 4 Calculate the next instruction s address 19
20 31 RTL: The ADD Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the next instruction s address 2
21 31 RTL: The Subtract Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits sub rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] - R[rt] The actual operation PC <- PC + 4 Calculate the next instruction s address 21
22 Datapath for Register-Register Operations R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt Ra, Rb, and Rw comes from instruction s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction fields: op and func op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 11 6 RegWr busw Rd Rs Rw Ra Rb -bit Registers Rt busa busb ALUctr ALU Result 22
23 Register-Register Timing Inst fetch Decode Opr. fetch Execute Write Back PC Old Value Rs, Rt, Rd, Op, Func ALUctr RegWr busa, B busw busw -to-q New Value Old Value Old Value Old Value Old Value Old Value RegWr Instruction Memory Access Time New Value Rd Rs Rt Rw Ra Rb -bit Registers Delay through Control Logic New Value busa busb New Value Register File Access Time New Value ALUctr ALU Result ALU Delay New Value Register Write Occurs Here 23
24 RTL: The OR Immediate Instruction bits 5 bits 5 bits bits ori rt, rs, imm 21 op rs rt immediate mem[pc] Fetch the instruction from memory R[rt] <- R[rs] or ZeroExt(imm) The OR operation PC <- PC + 4 Calculate the next instruction s address bits immediate bits 24
25 Datapath for Logical Operations with Immediate R[rt] <- R[rs] op ZeroExt[imm] Example: ori rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits bits Rd Rt RegDst Mux Rs RegWr busw imm Rw Ra Rb -bit Registers Don t Care (Rt) busb ZeroExt busa Mux ALUSrc ALUctr ALU Result 25
26 lw rt, rs, imm RTL: The Load Instruction op rs rt immediate 6 bits 5 bits 5 bits bits mem[pc] Fetch the instruction from memory Address <- R[rs] + SignExt(imm) Calculate the memory address R[rt] <- Mem[Address] Load the data into the register PC <- PC + 4 Calculate the next instruction s address immediate bits bits immediate bits bits 26
27 Datapath for Load Operations R[rt] <- Mem[R[rs] + SignExt[imm]] Example: lw rt, rs, imm Rd Rt RegDst Mux Rs RegWr busw imm op rs rt immediate 6 bits 5 bits 5 bits bits Rw Ra Rb -bit Registers Don t Care (Rt) busb Extender busa Mux ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data Memory MemtoReg Mux ExtOp 27
28 31 RTL: The Store Instruction op rs rt immediate 6 bits 5 bits 5 bits bits sw rt, rs, imm mem[pc] Fetch the instruction from memory Address <- R[rs] + SignExt(imm) Calculate the memory address Mem[Address] <- R[rt] Store the register into memory PC <- PC + 4 Calculate the next instruction s address 28
29 Datapath for Store Operations Mem[R[rs] + SignExt[imm] <- R[rt]] Example: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits bits RegDst busw Rd RegWr Mux imm Rt 5 5 Rs 5 Rw Ra Rb -bit Registers Rt busb Extender busa Mux ALUSrc ALUctr Data In ALU MemWr WrEn Adr Data Memory MemtoReg Mux ExtOp 29
30 RTL: The Branch Instruction beq rs, rt, imm 21 op rs rt immediate 6 bits 5 bits 5 bits bits mem[pc] Fetch the instruction from memory Cond <- R[rs] - R[rt] Calculate the branch condition if (COND eq ) Calculate the next instruction s address PC <- PC ( SignExt(imm) x 4 ) else PC <- PC + 4 3
31 Datapath for Branch Operations beq rs, rt, imm We need to compare Rs and Rt! op rs rt immediate 6 bits 5 bits 5 bits bits Rd Rt RegDst Mux Rs RegWr busw imm Rw Ra Rb -bit Registers Rt busb Extender busa Mux ALUSrc ALUctr ALU imm Branch Zero PC Next Address Logic To Instruction Memory ExtOp 31
32 Binary Arithmetic for the Next Address In theory, the PC is a -bit byte address into the instruction memory: Sequential operation: PC<31:> = PC<31:> + 4 Branch operation: PC<31:> = PC<31:> SignExt[Imm] * 4 The magic number 4 always comes up because: The -bit PC is a byte address And all our instructions are 4 bytes ( bits) long In other words: The 2 LSBs of the -bit PC are always zeros There is no reason to have hardware keep the 2 LSBs In practice, we can simplify the hardware by using a 3-bit PC<31:2>: Sequential operation: PC<31:2> = PC<31:2> + 1 Branch operation: PC<31:2> = PC<31:2> SignExt[Imm] In either case: Instruction-Memory-Address = PC<31:2> concat Concat means join using a splitter backward
33 Next Address Logic: Expensive and Fast Solution Using a 3-bit PC: Sequential operation: PC<31:2> = PC<31:2> + 1 Branch operation: PC<31:2> = PC<31:2> SignExt[Imm] In either case: Instruction-Memory-Address = PC<31:2> concat PC 3 1 imm Instruction<15:> Adder SignExt Adder 3 Mux 1 Addr<31:2> Addr<1:> Instruction Memory Instruction<31:> Branch Zero 33
34 Next Address Logic 3 PC imm Instruction<15:> 3 SignExt 3 Mux Carry In Adder 3 Addr<31:2> Addr<1:> Instruction Memory Instruction<31:> Branch Zero 34
35 31 j target RTL: The Jump Instruction 26 op target address 6 bits 26 bits mem[pc] Fetch the instruction from memory PC <- PC+4<31:28> concat target<25:> concat <> Calculate the next instruction s address 35
36 Instruction Fetch Unit j target PC<31:2> <- PC+4<31:28> concat target<25:> PC+4<31:28> Target Instruction<25:> Mux Addr<31:2> Addr<1:> Instruction Memory PC 3 1 imm Instruction<15:> Adder SignExt 3 Adder 3 3 Mux 1 Jump Instruction<31:> Branch Zero 36
37 Putting it All Together: A Single Cycle Datapath We have everything but the control signals. RegDst busw 1 RegWr Rd Mux imm Rt 5 5 Rs 5 Rw Ra Rb -bit Registers Rt busb Extender Branch Jump busa Mux 1 ALUSrc Instruction Fetch Unit ALUctr Data In ALU Zero Instruction<31:> Rt <21:25> WrEn Rs <:2> MemWr Adr Data Memory Rd <11:15> <:15> Imm Mux 1 MemtoReg ExtOp 37
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