Chapter 8 Basic Processing Unit. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Transcription

1 Chapter 8 Basic Processing Unit Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

2 Outline Fundamental Concepts Hardwired Control Microprogrammed Control Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

3 Content Coverage Main Memory System Address Data/Instruction Central Processing Unit (CPU) Cache memory Operational Registers Program Counter Arithmetic and Logic Unit Instruction Sets Control Unit Input/Output System Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

4 Instruction Execution To execute an instruction, the processor has to perform the following three steps: Step : fetch the contents of the memory location pointed by the PC. The contents of this location are interpreted as an instruction to be executed. Hence, they are loaded into the IR. Symbolically, this can be written as IR [[PC]] Step 2: assuming that the memory is byte addressable, increment the contents of the PC by 4, that is, PC [PC]+4 Step 3: carry out the actions specified by the instruction in the IR Step and Step 2 fetch phase Step 3 decode phase, execution phase, and/or write phase Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

5 Single-Bus Organization of the Datapath Memory bus Select Address lines Data lines Constant 4 PC MAR MDR Y Control signals Instruction decoder and control logic IR R0 ALU control lines A ALU Z B Carry-in R(n-) TEMP Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

6 Instruction Execution An instruction can be executed by performing one or more of the following operations in some specified sequence Transfer a word of data from one processor register to another or to the ALU Perform an arithmetic or a logic operation and store the result in a processor register Fetch the contents of a given memory location and load them into a processor register Store a word of data from a processor register into a given memory location Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

7 Register Transfers Ri in Ri Rj out Ri out Y in Rj Constant 4 Y Rj in Select A ALU B Z in Z out Z Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7

8 Input and Output Gating for -bit Register Bus 0 D D Ri in Ri out Clock Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

9 Arithmetic Operation Add R3, R, R2 R in R R2 out R out Y in R2 Constant 4 Select 0 Y R2 in R3 out Z in A ALU B R3 Z out Z R3 in Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9

10 Fetching a Word from Memory Memory data bus Internal processor bus MDR oute MDR out Move (R), R2 MDR ine MDR MDR in. R out, MARin, Read 2. MDRinE, WMFC 3. MDRout, R2in WMFC: is the control signal that causes the processor s control circuitry to wait for the arrival of the MFC signal. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 0

11 Execution of a Complete Instruction Ass (R3), R: adds the contents of a memory location pointed to by R3 to register R. Executing this instruction requires the following actions: Fetch the instruction Fetch the first operand (the contents of the memory location pointed to by R3) Perform the addition Load the result into R Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

12 Control Sequence Ri in Rj out Ri Ri out Y in Rj Constant 4 Y Rj in Instruction fetch Step Action Select Z in A ALU Z B PC out, MAR in, Read, Select4 Add, Z in 2 Z out, PC in, Y in, WMFC 3 MDR out, IR in 4 R3 out, MAR in, Read 5 R out, Y in, WMFC 6 MDR out, SelectY, Add, Z in 7 Z out, R in, End Z out Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

13 Control To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence. Computer designers use a wide variety of techniques to solve this problem. The approaches used fall into one of two categories: hardwired control and microprogrammed control Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3

14 Control Unit Organization Clock CLK Control step counter External inputs IR Decoder/encoder Conditional codes Control signals Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4

15 Finite State Machine for Control Control logic Outputs PCWrite PCWriteCond IorD MemRead MemWrite IRW rite MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst Inputs NS3 NS2 NS NS0 Op5 Op4 Op3 Op2 Op Op0 S3 S2 S S0 Instruction register opcode field State register Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5

16 PLA Implementation Op5 Op4 Op3 Op2 Op Op0 S3 S2 S S0 PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource PCSource0 ALUOp ALUOp0 ALUSrcB ALUSrcB0 ALUSrcA RegWrite RegDst NS3 NS2 NS NS0 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6

17 ROM Implementation ROM = "Read Only Memory" values of memory locations are fixed ahead of time A ROM can be used to implement a truth table if the address is m-bits, we can address 2 m entries in the ROM. our outputs are the bits of data that the address points to. m n m is the "height", and n is the "width" Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU

18 Microprogrammed Control Microprogrammed control Control signals are generated by a program similar to machine language programs Control unit Microcode memory Input Outputs PCWrite PCWriteCond IorD MemRead MemWrite IRWrite BWrite MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst AddrCtl Datapath Adder Microprogram counter Address select logic Instruction register opcode field Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8

19 Microinstruction format Field name Value Signals active Comment Add ALUOp = 00 Cause the ALU to add. LU control Subt ALUOp = 0 Cause the ALU to subtract; this implements the compare for branches. Func code ALUOp = 0 Use the instruction's function code to determine ALU control. RC PC ALUSrcA = 0 Use the PC as the first ALU input. A ALUSrcA = Register A is the first ALU input. B ALUSrcB = 00 Register B is the second ALU input. RC2 4 ALUSrcB = 0 Use 4 as the second ALU input. Extend ALUSrcB = 0 Use output of the sign extension unit as the second ALU input. Extshft ALUSrcB = Use the output of the shift-by-two unit as the second ALU input. Read Read two registers using the rs and rt fields of the IR as the register numbers and putting the data into registers A and B. Write ALU RegWrite, Write a register using the rd field of the IR as the register number and egister RegDst =, the contents of the ALUOut as the data. ontrol MemtoReg = 0 Write MDR RegWrite, Write a register using the rt field of the IR as the register number and RegDst = 0, the contents of the MDR as the data. MemtoReg = Read PC MemRead, Read memory using the PC as address; write result into IR (and lord = 0 the MDR). emory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR. lord = Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as the lord = data. ALU PCSource = 00 Write the output of the ALU into the PC. PCWrite C write control ALUOut-cond PCSource = 0, If the Zero output of the ALU is active, write the PC with the contents PCWriteCond of the register ALUOut. jump address PCSource = 0, Write the PC with the jump address from the instruction. PCWrite Seq AddrCtl = Choose the next microinstruction sequentially. equencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction. Dispatch AddrCtl = 0 Dispatch using the ROM. Dispatch 2 AddrCtl = 0 Dispatch using the ROM 2. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU